Low Power Domino Circuit Design 邱威豪、林浩仁
E-mail: [email protected]
ABSTRACT
With the advanced processing, the difference region between supply voltage and threshold voltage is scaled gradually. The scaled noise margin causes the leakage current to be one of the critical issues in the very deep submicron designs, and will seriously cause unnecessary power consumption. Domino keeper is always using to keep the noise margin in high fan-in domino gate. However, both the increasing power consumption and slower performance are significant problems due to the causing DC contention. In this paper, we present a new high-speed domino technique, called Conditional Isolator Domino (CI-Domino) , for wide fan-in domino logic. The CI-Domino logic not only improves the noise margin without sacrifices performance, moreover, subthreshold current can be significantly reduced in CI-Domino operations. By the simulation results on 0.18μm processing, CI-Domino significantly achieves the 48.14% noise margin improvement respective to conventional domino in the comparison of 32 fan-in OR gate, and further, CI-Domino reduces active power by 49.14%, standby power by 35.99%, and delay time by 60.27%.
Keywords : Noise Margin, Leakage Current, Domino Logic Circuit, DC Contention, Subthreshold Current, Dynamic Power, Static Power, Delay time.
Table of Contents
第一章緒論 1.1研究背景與目的...1 1.2CMOS的靜態耗能分析...4 1.3論文結構大綱...8 第二 章傳統骨牌式電路 2.1CMOS電路分析...10 2.2傳統Footed-Domino電路...12 2.3傳統Footless-Domino電 路...15 2.4骨牌式電路於複雜電路中的應用...17 2.5複雜骨牌式電路的問題分析...18 第三章當前相關的骨牌式 電路結構 3.1骨牌式技術的發展...24 3.2Conditional Keeper Domino...25 3.3High-Speed Domino...26 3.4Skew-Tolerant High-Speed Domino...28 3.5Clock-Delayed Sleep-Mode Domino...29 3.6Four-Phase Non-Full-Swing Keeper Domino..30 第四章Conditional-Isolator技術 4.1Conditional Isolator Domino...32 4.2動態耗能分析...34 4.3次臨 界電流耗能分析...35 4.4雜訊免疫力與運算速度的分析...37 第五章實驗結果與比較 5.1實驗環境說
明...39 5.2運算速度與雜訊免疫能力的模擬結果...40 5.3時脈頻率拉升觀察...43 5.4動態耗能與靜態耗 能的模擬結果...46 第六章 結論 6.1本篇論文總結...50 6.2未來發展方向...50 參考文獻
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