Implementation of DC/DC Converter Driver IC 楊志偉、郭永超
E-mail: [email protected]
ABSTRACT
In order to reduce the power consumption the SOC(system on chip) design usually needs to use the different voltage levels.
Moreover, the variable frequency technology is employed to change the frequency for the different function. Thus the power consumption can be reduce by using slow clock in low frequency circuits. Such variable voltage/variable frequency power management strategy is more important in the modern power management chip design. Therefore, in this paper, we employed a new variable voltage/variable frequency PWM(pulse-width modulation) circuit design. The variable voltage/variable frequency sawtooth generator (sawtooth oscillatior) is used to produce a stable sawtooth waveform in this paper. Moreover, some protection function is designed to fit the industrial requirements. This circuit is implemented by the 0.35μm processing of TSMC (Taiwan Semiconductor Manufacture Company). It can operate from 500KHz to 3MHz, supply voltage is 3.3V, total area is 0.436*0.436m2, and the power consumption is 4mW. From the simulation results, this excellent performance of the variable voltage/variable frequency PWM chip is verified.
Keywords : 系統晶片 ; 電源管理晶片 ; 脈波寬度調變器
Table of Contents
第一章 緒論 1.1 研究背景與目的 1.2 論文大綱 第二章 原理分析與設計 2.1 前言 2.2 誤差放大器 2.2.1 參考準位之設計 2.2.1.1 基本分壓電路 2.2.1.2 帶差參考電路 2.2.1.3 電流鏡電路 2.2.2 雙級組態放大器之設計 2.2.2.1 雙級 式運算放大器之增益 2.2.2.2 雙級式運算放大器之頻率響應 2.2.2.3 雙級式運算放大器之迴轉率 2.3 比較器 2.3.1 比較器的基本模型 2.3.2 比較器的架構 2.4 斜坡產生器 2.4.1 震盪器 2.4.2 環形震盪器 2.4.3 斜坡產生器 第三章 實作與電路效能之測試 3.1 誤差放大器之實作與效能測試 3.2 比較器之實作與效能測試 3.3 斜坡產生器之實作與效能 測試 3.4 各元件電路模擬與測試 3.5 實際晶片測試 3.6 完整電 路模擬與測試 第四章 結論
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