控制器(FSM) library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity controller is
Port ( Reset : in std_logic;
Clk : in std_logic;
start : in std_logic;
Pb1 : in std_logic;
Pb2 : in std_logic;
Winer : out std_logic_vector(3 downto 0)); --贏家 end controller;
architecture Behavioral of controller is type State_type is (s0,s11,s12,s21,s22);
signal State,Next_State : State_type;
begin
process(Reset,Clk,start,Pb1,Pb2) begin
if (Reset = '0') then Winer <= "0000";
State <= s0;
elsif (Clk'event and Clk='1') then
State <= Next_State; --切換狀態 end if;
case State is
when s0 => --初始狀態
Winer <= "0000"; --Moore Model if (Pb1='0' and start='0') then --1 號偷跑 Next_State <= s11;
elsif (Pb2='0' and start='0') then
Next_State <= s21; --2 號偷跑
elsif (Pb1='0' and start='1' and State /= s22) then --時間己到，１號 有按且 2 號尚未贏
Next_State <= s12;
elsif (Pb2='0' and start='1' and State /= s12) then Next_State <= s22;
else
Next_State <= s0;
end if;
when s11 => --1 號偷跑狀態
Winer <= "0000";
if (Pb1='1' and start = '0') then --1 號又放開 Next_State <= s0;
elsif (Pb2 = '0' and start = '1') then --2 號先按 Next_State <= s22;
else
Next_State <= s11; ----1 號持續按住 end if;
when s21 => --2 號偷跑狀態
Winer <= "0000";
if (Pb2='1' and start='0') then Next_State <= s0;
elsif (Pb1 = '0' and start = '1') then --１號先按 Next_State <= s12;
else
Next_State <= s21;
end if;
when s12 => --1 號贏狀態
Winer <= "0001";
Next_State <= s12;
when s22 => --2 號贏狀態
Winer <= "0010";
Next_State <= s22;
end case;
end process;
end Behavioral;
