RESEARCH AND DESIGN IN HARDWARE ARCHITECTURE OF DIGITAL BEAMFORMING RECEIVER
賴曉輝、黃其泮
E-mail: 9019011@mail.dyu.edu.tw
ABSTRACT
THE THESIS FOCUSES ON THE RESEARCH AND DESIGN OF DIGITAL BEAMFORMING RECEIVER'S HARDWARE ARCHITECTURE. THE RECEIVING FRONT-END CONSISTS OF AN ARRAY OF SENSORS (ANTENNAS) BY THE BEAMFORMING TECHNIQUES, WE CAN ARRIVE AT THE GOAL OF SPACE DIVISION MULTIPLE ACCESS IN WIRELESS ENVIRONMENT. THE ADAPTIVE PROCESSOR DETECTS THE DIRECTION OF ARRIVAL (DOA) OF EACH SOURCE SPREADING IN SPACE AND ESTIMATES THE OPTIMAL WEIGHT VECTOR.
CONSEQUENTLY, ADAPTIVE BEAMFORMING CAN BE USED TO INCREASE SYSTEM CAPACITY. ONE OF THE MAIN ISSUES IN SPACE DIVISION MULTIPLE ACCESS (SDMA) IS A TECHNIQUE OF SMART ANTENNA. THE SMART ANTENNA CAN IMPROVE PERFORMANCE IN SEVERAL WAYS ：(1) TO INCREASE SPECTRAL EFFICIENCY AND SYSTEM CAPACITY.(2) TO REDUCE MULTI-PATH INTERFERENCE.(3) TO COMBAT CO-CHANNEL INTERFERENCE(CCI).(4) RANGE EXTENSION. IN THIS TEXT, WE APPLY THE BAND-PASS SAMPLING THEOREM FOR IF SAMPLING OF THE ARCHITECTURE OF SOFTWARE RADIO. FURTHERMORE, WE COMPLETED INTERFACE-CIRCUIT AND CONTROL-SOFTWARE WHICH CAN CONTROL MULTI-DIGITAL DOWN CONVERTER IN ONE COMPUTER SIMULTANEOUSLY, AND REALIZE THE DIGITAL
BEAMFORMING(DBF) MODULE BY FIELD PROGRAMMABLE GATE ARRAY (FPGA). THE CONTROL-SOFTWARE OF VIEW INTERFACE SOFTWARE IS WRITTEN BY BORLAND C++ BUILDER (BCB) . IT CONTAINS THREE VIEW FORM ：(1) TO EXPLAIN ANY DIGITAL DOWN CONVERTER (DDC) MAGNITUDE INTERFACE (2) TO MONITOR EIGHTEEN DDC MAGNITUDE INTERFACE SIMULTANEOUSLY (3) TUNING INTERFACE. THE EIGHT-BITS ADJUST-ADDRESSER ON THE INTERFACE CIRCUIT CAN BE USED TOTAL TWO HUNDRED FIFTY-SIX ADDRESSES. THIS REACHES PURPOSE OF CONTROL MULTI-DDC. THE VERY HIGH DESCRIPTION LANGUAGE (VHDL) DESCRIBES DBF CIRCUIT TO ACCOMPLISH DBF BY XILINX 4036-3'S CHIP.
Keywords : BEAMFORMING, DIGITAL DOWN CONVERTER, BAND-PASS SAMPLING, DIGITAL RECEIVER Table of Contents
第一章 緒論--P1 1.1 數位式波束成形接收機簡介--P 1 1.2 研究背景--P 4 1.3 研究動機--P5 1.4 論文架構--P 5 第二章 取樣原 理--P 7 2.1 取樣原理--P 7 2.2 低通訊號取樣(SAMPLING LOW-PASS SIGNAL) --P 13 2.3 帶通訊號取樣(BANDPASS
SAMPLING) --P 15 2.4 HI5767 介紹--P 22 第三章 數位降頻器分析--P 27 3.1 前言--P 27 3.2 正交(QUADRATURE )取樣--P30 3.3 數位升頻器--P31 3.4 數位降頻器--P38 3.5 數位式降頻模組--P46 3.6 介面軟體--P48 3.7 介面電路--P51 第四章 DBF 之實 作--P55 4.1 DBF 特色--P55 4.2 功能--P56 4.3 實作方法--P58 第五章 模擬與實際量測--P61 5.1 模擬--P61 5.2 實際量測--P70 第 六章 結論與未來展望--P75 6.1 結論--P75 6.2 未來展望--P76 參 考 文 獻--P78
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