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//除頻電路---
`timescale 1ns / 1ps
module div( clk, reset, clkm );
input clk, reset;
output clkm;
wire clkm;
reg [31:0] divider;
always@(posedge clk or negedge reset ) begin
if ( ! reset )
divider <= 32'h0000_0000 ; else
divider <= divider + 1;
end
assign clkm = divider[23]; // 40M/2^24=0.2 sec endmodule
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