[PDF] Top 20 Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection
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Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection
... of SCR devices with different embedded PMOS and NMOS transistors have been compared and investigated in this ...R on , of the MOS-triggered SCR devices is enhanced by decreasing the ... See full document
7
Optimization on Layout Style of Diode Stackup for On-Chip ESD Protection
... effective on-chip ESD protection device due to the small parasitic loading effect and high ESD robustness ...adapt for some applications in which the I/O signal swing is higher ... See full document
3
A NEW ON-CHIP ESD PROTECTION CIRCUIT WITH DUAL PARASITIC SCR STRUCTURES FOR CMOS VLSI
... Based upon the understanding of CMOS transient latch-up [lo]-[ 131, the low trigger voltage can be achieved through the proper design of device capaci- tances within [r] ... See full document
7
Initial-on ESD protection design with PMOS-triggered SCR device
... Arrangements for On-Chip Applications The on-chip ESD protection designs for input, output, and power-rail ESD clamp circuits with PMOS-triggered ... See full document
4
SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes
... used for on-chip ESD protection cir- cuits has been successfully investigated in a ...n-well triggered currents, the switching voltage and turn-on time of DT_SCR ... See full document
11
Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-mu m CMOS process
... used for on-chip ESD protection cir- cuits has been successfully investigated in a ...high ESD robustness in a smaller layout area 16 V/ m . On-chip ESD ... See full document
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Low-capacitance SCR with waffle layout structure for on-chip ESD protection in RF ICs
... The MOS transistors in waffle layout structures had been studied ...layout structures for diodes had also been proposed to reduce its parasitic capacitance for ESD ... See full document
4
Implementation of initial-on ESD protection concept with PMOS-triggered SCR devices in deep-submicron CMOS technology
... the on resistance of the PMOS-triggered SCR devices needs to be fur- ther decreased to reduce the raised voltage across the ultra- thin gate oxide of the internal ...the SCR devices are ... See full document
11
Native-NMOS-triggered SCR With faster turn-on speed for effective ESD protection in a 0.13-mu m CMOS process
... SPEED FOR ESD PROTECTION IN A ...be triggered on in time. Once the NANSCR and LVTSCR are turned on, the HBM and MM-ESD-stressed energies are discharged through the lateral ... See full document
12
ESD Protection Design for 60-GHz LNA With Inductor-Triggered SCR in 65-nm CMOS Process
... ESD protection devices cause RF performance degradation with several undesired effects [13], ...the ESD protection device is one of the most important design considerations for RF ... See full document
10
SCR device fabricated with dummy-gate structure to improve turn-on speed for effective ESD protection in CMOS technology
... TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, ...dummy-gate structures under different substrate-triggered ...turn on this STSCR device during ESD-zapping ...suitable ... See full document
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ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit
... used for the protection circuits with reliability consideration, and the low-voltage transistors with thinner gate oxides used for the in- ternal circuits for high-speed and high-performance ... See full document
10
Dummy-gate structure to improve turn-on speed of silicon-controlled rectifier (SCR) device for effective electrostatic discharge (ESD) protection
... dummy-gate structures have been fabricated with the same layout area in a ...dummy-gate structures on the substrate-triggered current are compared in ... See full document
4
ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology
... PS-mode ESD stress with silicide blocking on pMOS and nMOS devices is 3 A, and that without silicide blocking is 2 ...embedded SCR structures are fully silicided in these I/O ...voltage ... See full document
10
Low-capacitance SCR with waffle layout structure for on-chip ESD protection in RF ICs
... other SCR devices. The trigger voltages among the SCR devices under different trigger diffusion areas are compared in ...modified SCR, the trigger voltages can be significantly ...all SCR de- ... See full document
9
Test structure on SCR device in waffle layout for RE ESD protection
... trigger diffusion is added across the N-well/P-well junction intrinsic characteristics of the SCR device in high frequency in the stripe modified SCR (SMSCR), as shown in Fig. 3(c), are [r] ... See full document
4
Low-capacitance and fast turn-on SCR for RF ESD protection
... Based on the measurement results in this paper and the prior work [11], the qualitative comparisons among SCR-based devices in terms of turn-on voltage, turn-on speed, parasitic capacita[r] ... See full document
10
Latchup-free ESD protection design with complementary substrate-triggered SCR devices
... design for CMOS integrated circuits, he has published over 150 technical papers in international journals and ...patents on reliability and quality design for integrated circuits, including 53 ...in ... See full document
13
Substrate-triggered technique for on-chip ESD protection design in a 0.18-mu m salicided CMOS process
... improve ESD robustness of ESD protection devices without sudden degradation as that found in the traditional gate-driven ...power-rail ESD protection circuits have been successfully ... See full document
8
SCR device with dynamic holding voltage for on-chip ESD protection in a 0.25-mu m fully salicided CMOS process
... the SCR de- vice ...under ON state, the channel resistance of NM2 is smaller than the resistance of R sub , therefore, the holding voltage of DHVSCR can be raised up greater than the supply ...happen ... See full document
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