第四章 正交相位壓控振盪器
4.4 實作一 Series Coupling Quadrature VCO
4.4.3 模擬結果
Die photo
6 Pin DC Pad
_ _
IF IQ input
_ Out I _ Ou t Q
SSB SSB
圖4.22 3D trifilar series QVCO die photo 預計規格表
Item Spec Technology TMSC 0.13µm CMOS
Supply Voltage 1.2 V
Current of QVCO core 5.4 mA Current of Output buffer 12.84mA Power Consumption of core ~ 6.5mW
Tuning frequency range 4.49GHz~5.25GHz
KVCO 760MHz/V
Phase Noise -108dBc/Hz @ 1MHz offset Sideband rejection -32dB
FOM -173.8 Die size 1030µm× 1210µm
表4.1 3D trifilar series QVCO預計規格表
4.4.4結果與討論
由模擬結果顯示，相位雜訊在1MHz offset處為-108dBc/Hz，因為 相位雜訊與輸出功率有關係，VCO輸出較大功率時，會有較佳的相位 雜訊表現，若為了得到較大的輸出功率，我們可以要使VCO核心電路
（負阻抗）操作電流增大，使得回路增益變大而得到較大的輸出功 率，但相對的會使電路的消耗功率增大，而且根據[36]增加電流只在 振盪器是在inductance-limited的情況下，相位雜訊特性才會變好。
由模擬的sideband rejection得到是-32dB，假設VCO輸出正交訊號 的振幅大小皆相同的話，可以得到正交訊號的相位誤差約是3o，但若 振幅大小存在有誤差的話，相位誤差應是小於3o。Die size被量測上所 需的pad所限，導致面積較大，實際上VCO核心電路的面積只有 600x500μm2
4.5 實作二 Quadrature VCO Based on Trifilar Coupling （TSMC 0.18μm CMOS）
4.5.1 研究動機
使用series coupling的QVCO架構因為電晶體的疊接，所以需要較 高的操作電壓，但低壓操作為目前的趨勢，故有人提出直接使用變壓 器來達成二個VCO的訊號耦合，我們更進一步將共振腔的電感與耦合 用的變壓器整合在一起，再次使用trifilar這個一對二的雙壓器來達成 此概念，如此不僅可以降低操電壓更可以減少被動元件所佔的面積。
4.5.2 實作電路架構
圖4.23 QVCO based on trifilar coupling電路圖
上一節中我們提到需要一個passive SSB up-converter間接來量測 相位準度，而我們從外面注入低頻訊號IF正交四個相位的訊號，但在
這次實作中我們將主動式的balun整合在晶片中，所以只需從外面注
(3)Phase noise
圖4.27 QVCO based on trifilar coupling phase noise
(4) Side band rejection
圖4.28 QVCO based on trifilar coupling side band rejction
Chip performance
Item Spec Technology TMSC 0.18µm CMOS
Supply Voltage 1.2 V Current of QVCO core 35 mA Power Consumption of core 52.5mW
Tuning frequency range 4.7GHz~5.16GHz
KVCO 657MHz/V
Phase Noise -122.5dBc/Hz @ 1MHz offset Sideband rejection 33.7dB
FOM -180.1dBc Die size 1200µm× 1310µm
表4.2 QVCO based on trifilar coupling performance summary
Die photo
6 Pin DC Pad
IF IQ Input
_OutI
_OutQ
DC GND
SSB SSB
圖4.29QVCO based on trifilar coupling die photo
4.5.4結果與討論
實作一因為疊接架構，操作電壓需要1.2V，實作二的架構則只 須要0.7V 即可正常操作，但是為了相位雜訊最佳點的量測，工作電 壓需要提升至1.2V。
Side-band rejection 為 33.7dB，由圖 3.57 可以得知：假設在正交 訊號的大小皆相等的情況下，相位誤差約為2.5 度，但實際上正交訊 號大小並不會相等，則相位誤差會小於2.5 度；若假設正交訊號的相 位誤為0 度，則訊號的大小誤差為 0.35dB。相位雜訊為-122.5dBc/Hz
@ 1MHz offset，是可以接受的數字，但 FOM 只有 180.1dBc，主要的 原因是消耗功率的增加，因為當工作電壓由0.7V 提升到 1.2V 時，核 心電路的電流從24.8mA 增加到 35mA，消耗功率大幅的上升。
第五章
結論
本論文利用了 TSMC 0.18μm CMOS 之製程，實作與量測了不同 類型 Marchand balun 電路，不管是 0o, 0o或 0o, 180o的 Marchand，實 測結果與理論推導皆一致，需要較大耦合量的結構確實有較寬的頻 寬。除了 Marchand 測試件的實作以外，更利用 TSMC SiGe 0.35μm BiCMOS 製程將被動 Marchand 與主動混頻器結合，結果亦是相同。
在除頻器部分，採取了一個新型電流交換 D flip-flop 電路來達成 產生 50%工作週期的除五電路，並利用 TSMC SiGe 0.35μm BiCMOS 製程來驗證電路，結果與推測相符。在類比高速除頻器，我們則利用 Win 0.15m PHEMT 與 MHEMT 來實作 RFD 與 ILFD，其中 RFD 的實 作包含差動輸出的傳統 RFD 與正交輸出的 RFD，量測結果亦顯示可 高頻操作特性；而 ILFD 則實作了除 2 與除 3 的除頻器，模擬結果顯 示 ILFD 適合於高頻操作的特性與窄頻寬之特性。
最後，利用了 TSMC 0.18μm CMOS 與 TSMC 0.13μm CMOS 製程技術實作正交輸出的振盪器，電路利用了 trifilar 這個元件來達成 訊號的耦合，為新型的正交相位振盪器架構，量測結果顯示了這個新 型電路架構的可行性。
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