Chapter 4 A Low Power ADPLL Circuit Design
4.2 Circuit Design of The ADPLL
4.2.4 The Sub-Circuit Design
(1) D Flip-Flop:
In the ADPLL, D Flip-Flop (DFF) have been used in many circuits, such as: the DCO counter, the synchronizers of PFD, the frequency gain register, the phase gain register, and the DCO control register. The DFFs are all realized by the true single-phase clocked circuits (TSPC), shown in Fig. 4-7, because of its good performance well-known at high frequency.
Fig.4-7 TSPC DFF
(2) Adder / Subtractor:
In the ADPLL design, there is roughly half of the reference cycle (i.e.,10nsec) for full operation of the control unit, therefore, for the power and area consideration, we can just use a 11-bit modified ripple adder/subtractor, which is shown in Fig. 4-9. In addition, the logical diagram and the transistor-level circuit of 1-bit full adder (FA) is also shown in Fig. 4-8 (a) and (b), respectively.
(a)
(b)
Fig.4-8 1-bit FA (a) logic diagram, (b) transistor-level circuit
Fig.4-9 11-bit modified ripple adder/subtractor
Chapter 5
The Implementation of Frequency Synthesizer
In this chapter, at first, we will introduce the fundamentals of frequency synthesizer. Then, the ADPLL-based frequency synthesizer based on the adjustable counter length mechanism will be presented. Finally, it also shows the implementation of layout and the simulation results.
5.1 Frequency Synthesizer Architecture
As mentioned in the chapter 1, synthesizers often require that the output frequency of a PLL be a multiple of the input frequency. The high accuracy for the different output frequency often mandates the use of PLLs in synthesizers because under locked condition, the output frequency of a PLL bears an exact relationship with the input frequency. In this section, we will introduce several architectures for the frequency synthesizer [16].
5.1.1 Integer-N Architecture
Depicted in Fig. 1-2, as mentioned above, such a topology produces fout=M‧fREF, where M (i.e., modulus) varies in unity steps from ML to MH. The frequency divider employed in Fig. 1-2 must provide a variable modulus given by M = ML + k, k = 0,1,…,N. An example of such a circuit is a “pulse-swallow divider,” illustrated in Fig.
5-1. The divider consists of a “prescaler,” a “program counter,” and a “swallow counter.” We briefly describe the operation of the circuit here. Let us first make three observations: (1) the prescaler divides the input by either N + 1 or N according to the logical state of the modulus control line, (2) the program counter always divides the prescaler output by P, and (3) the swallow counter divides the prescaler output by S, where S is determined by the digital input and can vary from 1 to the maximum number of channels. This counter also has a reset input. We will show that fout = fin / (NP + S).
Fig.5-1 Pulse swallow frequency divider
When the circuit begins from the reset state, the prescaler divides by N + 1. The prescaler output is divided by both the program counter and the swallow counter until the latter is “full,” i.e., it has counted S pulses. At this point, that is, after (N + 1)S cycles at the main input, the swallow counter changes the state of the modulus control line, making the prescaler divide fin by N. Note that before this change, the program counter has sensed a total of S pulses. After the modulus changes, the prescaler and program counter continue to divide until the latter is full. Since the program has already sensed S pulses, it requires P–S cycles at its input, and hence (P–S)N pulses at the main input, to reach overflow. Thus, the output generates one complete cycle for every (N + 1)S + (P–S)N = PN + S cycles at the input. The operation repeats after the swallow counter is reset.
The simplicity of the integer-N architecture has made it a popular choice for many decades. In RF systems, the synthesizer has commonly been partitioned into three separate chips: the VCO; the dual-modulus prescaler; and the combination of the program counter, the swallow counter, the PFD, and the charge pump. As the fast parts of the system, the VCO and the prescaler has typically been fabricated in silicon bipolar or GaAs technologies and the rest in CMOS technology. Note that a buffer is usually interposed between the VCO and the prescaler to isolate the former from the switching noise in the latter.
5.1.2 Fractional-N Architecture
In the integer-N architecture, the loop bandwidth is limited because the input
reference frequency must be equal to the channel spacing. This, in turn, results from the property that the output frequency changes by only integer multiples of fREF , In
“fractional-N” synthesizers, on the other hand, the output frequency can vary by a fraction of the input frequency, allowing the latter to be much greater than the channel spacing.
Fig. 5-2 (a) shows a simple phase-locked fractional-N architecture. In addition to the PFD, LPF, and VCO, the loop incorporates a pulse remover, a circuit that blocks one input pulse upon assertion of the remove command. Since under locked condition, the two frequencies presented to the phase detector must be equal, the average output frequency of the pulse remover equals fREF , and hence fout = fREF + 1/Tp , where 1/Tp is the period with which the remove command is applied. Note that fout can vary by a fraction of fREF because the frequency fp = 1/Tp can be derived from fREF by simple division. Provided by a crystal oscillator, fREF is typically limited to a few tens of megahertz. Thus, as shown in Fig. 5-2 (b), fractional-N loops incorporate a divider in the feedback to generate high output frequencies.
(a)
(b)
Fig.5-2 (a) Simple fractional-N synthesizer, (b) use of divider in the loop
While the original fractional-N topology was based on the pulse remover concept [17], modern implementations of this architecture operate on a somewhat different principle. Depicted in Fig.5-3, such a synthesizer replaces the pulse remover and the divider of Fig. 5-2 (b), with a dual-modulus prescaler. If the prescaler divides by N for A output pulses of the VCO and by N + 1 for B output pulses, then the equivalent divide ratio is equal to (A + B) / [A / N + B / (N + 1)]. This value can vary between N and N + 1 in fine steps by proper choice of A and B. The resulting modulus is sometimes written as N.f , where the dot denotes a decimal point and N and f represent the integer and fractional parts of the modulus.
Fig.5-3 Fractional-N synthesizer using a dual-modulus divider
As an example, consider the circuit in Fig. 5-4, where fREF = 1 MHz and N = 10.
Let us assume the prescaler divides by 10 for 9 reference cycles and by 11 for one reference cycle. The total number of output pulses is therefore equal to 9 x 10 + 11 = 101, whereas the reference produces 10 pulses. In other words, the divide ratio is equal to 10.1 and fout = 10.1 MHz.
With fREF in the range of tens of megahertz, the loop bandwidth of a fractional-N synthesizer can be as high as a few megahertz, yielding a fast lock transient as well as suppressing the VCO close-in phase noise.
Fig.5-4 Example of a fractional-N synthesizer
5.2 Frequency Dividers
Frequency dividers are important in the study of frequency synthesizers. In addition to the issue of speed and power dissipation, the phase noise of dividers is also critical for it corrupts the feedback signal in synthesizers. In this section, we will introduce some divider topologies.
5.2.1 Divide-by-Two Circuits
As shown in Fig.5-5, a divide-by-two circuit can be realized as two latches in a negative feedback loop. Only if CK andCKare precisely complementary and the two latches match perfectly, this configuration can provide quadrature phases at X and Y.
Device mismatches typically result in phase imbalances as large as 5o. In addition, additional phase imbalances could arise if CK andCKare not differential exactly.
Fig.5-5 Divide-by-two circuit
We can also use dynamic latches in the high speed CMOS divide-by-two circuits.
Fig. 5-6 shows two examples, in which the TSPC divider has been mentioned in the chapter 2. In the circuit of Fig. 5-6 (a), the first two CMOS inverters operate as dynamic latches controlled by CK andCKand the third inverter provides the overall inversion required in the negative feedback loop. Fig. 5-6 (b) is a divide-by-two circuit realized by the TSPC register, which can achieve high speed. Lack of precise complementary or quadrature outputs is the disadvantage of both these circuits.
(a)
(b)
Fig.5-6 Dynamic dividers using (a) inverters, (b) TSPC
5.2.2 Dual-Modulus Dividers
Dual or multi-modulus dividers have been used in many phase-locked synthesizers. Such circuits divide the input frequency by one of the module according to a control input. A divide-by-2/3 circuit is a commonly used dual-modulus divider.
First, we consider a simple
÷
3 circuit, shown in Fig. 5-7 (a). It uses two master-slave D-flipflops together with an AND gate to create three states: Q Q1 2 =01, 10, 11. Note that the state Q Q1 2 =00 can never occur (except at start-up).(a)
(b)
Fig.5-7 (a) Divide-by-3 circuit (b) Divide-by-2/3 circuit
We can simply control Q1 by interposing an OR gate between the first flipflop and the AND gate, so as to convert the topology of Fig. 5-7 (a) to a
÷
2/3 circuit, shown in Fig. 5-7 (b). When MC is high, the divider is configured as a÷
2 circuit, and when MC is low, it is a÷
3 circuit. In addition, divide-by-three circuits are generally much slower than the divide-by-two counterparts. As shown in Fig. 5-7 (a), for example, following the clock edge on which Q must change, sufficient time 2have to be allowed for the delay of G1 and the input stage of FF2 before the next clock transition. Besides, in Fig. 5-7 (a), the output of FF2 have to drive the input capacitance of both G1 and FF1 . Therefore,
÷
3 circuits typically exhibit a maximum speed roughly half that of÷
2 circuits.By using a
÷
2/3 circuit or a÷
3/4 circuit serving as the core, a dual-modulus divider with other modulus can be realized. In Fig. 5-8, for example, a÷
15/16 circuit can be designed. In the circuit, FF1 , FF2 , G1 , and G2 compose a synchronous÷
3/4 circuit, which divides the FF2 output by four when MC is high and by threewhen both MC and MF are low. In addition, FF3 , FF4 , and G3 form the asynchronous section, which divides the output of FF2 by four and drives MF high when Q Q3 4 =11. Hence, the overall circuit divides the input frequency by 16 when MC is high. If MC is low, the circuit avoids the state 0000 since if Q Q3 4 =00, the
÷
3/4 circuit will go through only three states: 01, 10, 11. Note that the critical path in the circuit includes both G1 and G2 , which makes it slower than the divider of Fig. 5-7 (b).Fig.5-8 Divide-by-15/16 circuit
5.3 The Proposed ADPLL-Based Frequency Synthesizer
Based on the proposed ADPLL circuit, we can realize a frequency synthesizer for high speed clock generation by modifying the design of DCO counter in the PFD. As we know, the function of the counter in the PFD is just like the frequency divider in the feedback loop of the ADPLL. Hence, it can be implemented as an Integer-N synthesizer with multiple multiplication factors by using the adjustable counter length mechanism, as shown in Fig. 5-9.
Fig.5-9 Adjustable DCO counter length
For example, if 500 MHz clock output is desired, the S500M input control signal will be asserted, then the fifth D Flip-Flop output signal would be selected to compare with the matched delay reference clock by the synchronizer made of a D flip-flop.
Therefore, the ADPLL will generate 500 MHz clock output when the state is lock.
In addition, as mentioned above, since the middle point of the reference cycle is set as the detected point in our design, we also have to add an inverting path for DCO output so as to provide the output clocks with odd multiplications.
Besides, by referring to the different specifications in high speed DSP application, our frequency synthesizer has been designed for providing the 300M, 400M, 500M, 600M, 850M ,and 1GHz output clock. Finally, the relationship between input control signal and output clock frequency is summarized in Table 5-1.
Table 5-1 Frequency of output clock V.S. input control signal Input control signal Frequency of the output clock
S300M=1, others=0 300MHz
5.4 Layout Implementation and Simulation Result
In this section, we will show the layout and simulation result of our ADPLL design. In the layout implementation phase, we should take care about the floor plan first, then, also consider the shape of each block, as well as the matching and
Fig. 5-10 and Fig. 5-11 show the layout implementation and floor plan respectively. The main signal path among these building blocks in ADPLL is roughly counterclockwise, in this way we can place these blocks compactly. Fig. 5-12 shows the area occupation ratio of each building block in ADPLL; 32% of the overall area is for DCO and its replica delay element, 56% for control unit, and 12% for PFD. With regard to power-consumption distribution in the ADPLL, as shown in Fig. 5-13, because of the high operating frequency of DCO, the DCO and its replica circuit dissipate a large part of total power dissipation in spite of their smaller area occupation than all of other circuits in the ADPLL.
Fig.5-10 Layout of the ADPLL
Fig.5-11 Floor Plan of the ADPLL
Area Distribution
PFD 12%
Control Unit 56%
DCO (+replica)
32%
Fig.5-12 Area Distribution of the ADPLL
Power Consumption Distribution (@ 1GHz)
DCO (+replica) 58%
PFD 7%
Control Unit 35%
Fig.5-13 Power-Consumption Distribution of the ADPLL
Thereupon, we will present the overall simulation results with different operating frequency, and the input reference clock frequency is always set as 50 MHz. Fig. 5-14, Fig. 5-15, Fig. 5-16, Fig. 5-17, Fig. 5-18, and Fig. 5-19 show the lock process of ADPLL in output clock of 300 M, 400 M, 500 M, 600 M, 850 M, and 1-GHz respectively. Each figure includes three sub-figures, they are the overall lock process, the zoom in of lock process, and the locked state of ADPLL individually.
Besides, within each sub-figure, there are four main signals are shown: the reference clock, DCO output clock, LOCK signal, and value of DCO control word.
The reference clock is from the matched delay clock of the input reference signal.
Fig.5-14 (a) The overall lock process of 300MHz target frequency.
Fig.5-14 (c) The locked state of 300MHz target frequency.
Fig.5-15 (a) The overall lock process of 400MHz target frequency.
Fig.5-15 (b) The zoom in of lock process of 400MHz target frequency.
Fig.5-16 (a) The overall lock process of 500MHz target frequency.
Fig.5-16 (b) The zoom in of lock process of 500MHz target frequency.
Fig.5-16 (c) The locked state of 500MHz target frequency.
Fig.5-17 (a) The overall lock process of 600MHz target frequency.
Fig.5-17 (b) The zoom in of lock process of 600MHz target frequency.
Fig.5-17 (c) The locked state of 600MHz target frequency.
Fig.5-18 (a) The overall lock process of 850MHz target frequency.
Fig.5-18 (b) The zoom in of lock process of 850MHz target frequency.
Fig.5-18 (c) The locked state of 850MHz target frequency.
Fig.5-19 (a) The overall lock process of 1GHz target frequency.
Fig.5-19 (b) The zoom in of lock process of 1GHz target frequency.
Fig.5-19 (c) The locked state of 1GHz target frequency.
14
300 400 500 600 850 1000
operating freq.(MHz)
lock cycle
Fig.5-20 Lock cycle VS. operating frequency
0
300 400 500 600 850 1000
operationg freq.(MHz)
jitter(p-p, psec)
Fig.5-21 Jitter VS. operating frequency
0
300 400 500 600 850 1000
operating freq.(MHz)
power dissipation(mW)
Fig.5-22 Power dissipation VS. operating frequency
Finally, Fig. 5-20, Fig. 5-21, and Fig. 5-22 present performance summaries of the ADPLL-based frequency synthesizer in different operating frequency. As shown in Table 5-2, compare to other ADPLL circuit design, our ADPLL owns the largest frequency range and the monotonicity characteristic due to the new DCO design. In addition, our ADPLL needs the smallest area and power cost because of its simplicity, and also has the fewer lock cycles by using the modified PFD.
Table 5-2 Performance comparison of ADPLL
Design JSSC04 [3] JSSC03 [23] JSSC03 [28] This Work
Chapter 6
Conclusion and Future Work
6.1 Conclusion
In this thesis, an ADPLL-based frequency synthesizer with low power and area cost, wide frequency range, and short lock cycle is proposed.
A DCO with features of wide frequency range, and low power consumption is proposed. By using the new type digitally controlled delay element (DCDE), a digitally controlled oscillator (DCO) with characteristics of its monotonicity is presented, which makes the DCO design more straightforward. In addition, compared with the conventional architecture, a dual-mode one-cycle PFD used to reduce the lock cycle time is also presented.
Table 6-1. Performance Summary of the Frequency Synthesizer ADPLL-based Frequency Synthesizer
Reference clock 50MHz
Output Clock Frequency 300MHz / 400MHz / 500MHz / 600MHz / 850MHz / 1GHz
Jitter (p-p) 46ps @ 1GHz
120ps @ 300MHz (worst case) Locked time <=16 input cycles
Power consumption 3.1mW @ 1GHz
Area 100um x 120um
Supply voltage 1.2V
Process TSMC 0.13um CMOS process
DCO
Frequency Range 260MHz ~ 1.15GHz
Resolution 11bits (0.4ps ~ 20ps / LSB)
Power consumption 0.9mW @ 1GHz
In conclusion, with the specification, the proposed ADPLL-based frequency synthesizer is suitable for high speed clock generation in high speed DSPs applications.
6.2 Future Work
In the recent year, low power is a more and more important issue in circuit design. However, most techniques to reduce power dissipation of integrated circuits are to choose system and circuit parameters at design time. In fact, in some applications, it is a more efficiency way of adjusting the circuit during operation, such as: voltage scaling or lowering the operating clock frequency. The related control schemes have been proposed in [24]-[27].
To reduce the power dissipation, it usually needs different voltage or frequency in a low power system. Hence, in our future work, we can take advantage of the adaptive voltage scaling (AVS) scheme in our ADPLL to decrease the power
provide several different supply voltage for the DCO, which consumes a great part of the total power dissipation in the ADPLL. Therefore, by scaling down the supply voltage of DCO, we can save much power dissipation while still meeting the same specification.
S300M S400M S500M S600M S850M S1-G
PFD
Fig.6-1 The ADPLL with AVS
Reference
[1] Behzad Razavi, Design of Analog CMOS Integrated Circuits, Boston:
McGraw-Hill, 2001.
[2] T. Olsson, and P. Nilsson, “A digital PLL made from standard cell,” in Proc.
15th ECCTD, pp. 277-280, 2001.
[3] T. Olsson, and P. Nilsson, “A digitally controlled PLL for SoC applications,”
IEEE J. Solid-State Circuits, Vol. 39, pp. 751 - 760, May 2004.
[4] R. E. Best, Phase-Locked Loops: Theory, Design and Applications, 2nd ed.
New York: McGraw-Hill, 1993.
[5] J. Dunning, G. Garcia, J. Lundberg, and E. Nuckolls, “An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors,” IEEE J. Solid-State Circuits, vol. 30, pp. 412–422, Apr.
1995.
[6] J.-S. Chiang, and K.-Y. Chen, “A 3.3 V all digital phase-locked loop with small DCO hardware and fast phase lock,” in ISCAS, vol. 3, pp. 554–557, 1998.
[7] Eric Pascal Roth, “All-Digital Standard-Cell Based Audio Clock Synthesis,”
Ph.D Dissertation of ETH, No. 15667, E.E. Department, Zurich, Swiss, 2004
[8] F. M. Gardner,” Phase-lock Techniques,” 2nd Edition. John Wiley & Sons, New York, NY 1979.
[9] J. Craninckx, M. Steyaert, ”Wireless CMOS Frequency Synthesizer Design,”
Kluwer Academic Publishers, 1998.
[10] D. C. Cox and R. P. Leek, “Component signal separation and recombination for linear amplification with nonlinear components,” IEEE Trans. Comm., vol. 23, pp.1281-1287, Nov. 1975.
[11] J. Craninckx, M. Steyaert, “Low-noise voltage-controlled oscillators using enhanced LC-tanks,” IEEE Trans. On Circuit and System II, vol. 42, no. 12, Dec. 1995.
[12] Paul Gray, Iasson F. Vassiliou, “Top-Down Design of a Phase Locked Loop For a Video Driver System,” University of California at Berkeley master thesis.
[13] M. Saint-Laurent and M. Swaminathan, “A digitally adjustable resistor for path delay characterization in high frequency microprocessors,” in Proc. Southwest Symp. Mixed-Signal Design, 2001, pp. 61–64.
[14] M. Maymandi-Nejad and M. Sachdev, “A digitally programmable delay element: Design and analysis,” IEEE Trans. Very Large Scale Integration (VLSI) Syst., vol. 11, no. 5, pp. 871–878, Oct. 2003.
[15] M. Maymandi-Nejad, and M. Sachdev, “A monotonic digitally controlled delay element” IEEE J. Solid-State Circuits, Vol. 40, no. 11, pp. 2212-2219, Nov.
2005.
[16] Behzad Razavi, RF Microelectronics, NJ: Prentice Hall, 1998.
[17] R. G. Meyer, R. Eschenbach, and W. M. Edgerley, ”A Wideband Feedforward Amplifier,” IEEE J. Solid-State Circuits, Vol. 9, pp. 422-488, Dec. 1974.
[18] E. E. Eid, F. M. Ghannouchi, and F. Beauregard, “Optimal Feedforward Linearization System Design,” Microwave J., pp. 78-86, November 1995.
[19] Amr M. Fahim, ”A Compact, Low-Jitter Digital PLL,” in Proc. IEEE ESSCIRC, pp. 101-104, Sep. 2003.
[20] T.-Y Hsu and C.-Y Lee, ”An All-Digital Phase-Locked Loop (ADPLL)-Based Clock Recovery Circuit,” IEEE J. Solid-State Circuits, Vol. 34, no. 8, pp.
[20] T.-Y Hsu and C.-Y Lee, ”An All-Digital Phase-Locked Loop (ADPLL)-Based Clock Recovery Circuit,” IEEE J. Solid-State Circuits, Vol. 34, no. 8, pp.