Chapter 2 An Overview of PLL
3.4 Digitally Controlled Oscillator Architecture
The architecture of DCO is presented in Fig. 3-10. The DCO is composed of eight Digitally Controlled Delay Elements (DCDE), several transmission gates, balance inverters, output driving inverters, and one controlling NAND gate to enable the DCO. The proposed DCO circuit has total 11-bit resolution, including coarse tune and fine tune parts. In coarse tune part, the number of delay element is chosen to cover different frequency band. The number of delay element will increase rapidly through the increasing path-selecting control bits, thus, the circuit will consume much more power. Furthermore, the cover band between band to band will also decrease the operational frequency range. In a nutshell, only 1-bit control word has been used for path selector. This selection occurs based on the first frequency comparison at the
beginning of the phase lock.
In fine tune part, the new DCDE [14], [15] is adopted with 7-bit resolution in consideration of linearity. As mentioned above, the delay of the DCDE changes monotonically with respect to the digital input vector. The main idea of the DCDE is to adjust the delay difference by using current mirror-based circuit in binary-weighed fashion. The most significant advantages of such delay element are its monotonic charateristic and PVT variations immunity.
Fig.3-10 The proposed DCO architecture
Fig.3-11 The Modified DCDE
The minimum delay difference caused by an LSB, which corresponds to the smallest control device in the DCDE. Thus, when the LSB asserts, the smallest control device is ON in each DCDE. However, the minimum delay difference would increase in proportion to the increase of delay element. Based on that, a modified DCDE to extend the resolution is presented, shown in Fig. 3-11. Initially, we could take every two DCDE as a group, and choose one of them to add a smallest control pMOS. In other words, the control bit 3 affects four DCDEs and higher order bits affect eight DCDEs. Hence, it will increase extra 1-bit resolution of the DCO circuit.
Similarly, two more bits of resolution result from using the same pMOS device in only two of eight and one of eight DCDEs respectively. To sum up, 10-bit resolution is achieved by the fine tune part of proposed DCO.
The simulation result is shown in Fig. 3-12. Table 3-1 shows frequency ranges of the two modes of DCO. The total operation frequency range is in 260 MHz – 1.15 GHz, and the LSB resolution is 0.4 – 20 ps. Power consumption is 0.9 mW at 1 GHz.
0
0 500 1000 1500 2000 2500
number presentation of the input word
DCO output frequency (MHz)
Fig.3-12 DCO Frequency V.S. number of the input vector
Table 3-1 Frequency Range of DCO with Different Environments Frequency Range (MHz)
The Mode of DCO
25OC 1.2V 25OC 1.1V 75OC 1.2V High Frequency Mode 500 – 1150 465 – 1040 454 –1060 Low Frequency Mode 260 – 635 240 – 578 233 – 588
Chapter 4
A Low Power ADPLL Circuit Design
In this chapter, we will introduce the proposed ADPLL circuit design. The ADPLL has gained increased attention in recent years. All analog building blocks are replaced with digital representations in ADPLL. The term “all-digital PLL” is used for a particular reasons: all signals within this PLL are digital values; no analog signal is used.
4.1 Architecture of The ADPLL
As mentioned above, the conventional ADPLL uses four loosely coupled modes of operation: frequency acquisition, phase acquisition, phase maintenance, and frequency maintenance [5], [6]. However, by using a modified PFD architecture in the ADPLL design, we can combine the frequency acquisition and phase acquisition modes in the conventional ADPLL to the frequency/phase acquisition mode, and also combine the frequency maintenance and phase maintenance modes to the frequency/phase maintenance mode in our ADPLL design.
Fig. 4-1 depicts a block diagram of the ADPLL. The DCO control register in the control unit holds the 11 b, binary weighted DCO control word, which dictates the frequency of the DCO. Arithmetically incrementing or decrementing the DCO control
word modulates DCO frequency and phase. The frequency-gain register or phase-gain register in the control unit will provide operands to the adder/subtractor, hence the adder/subtracter can provide the updates to the DCO control register.
Fig.4-1 The ADPLL Block Diagram
Frequency/phase maintenance mode begins with frequency/phase acquisition mode. The goal of this mode is to lock frequency and phase of the DCO to that of the match-delay reference clock. In this mode, a modified binary-search algorithm sweeps the frequency range of the output of DCO counter in the PFD to match that of the reference clock. The search algorithm which has been introduced in previous chapter is also shown in Fig. 4-2. It makes incremental changes to the DCO control word based on the output of the PFD. The value held in the frequency-gain register determines the magnitude of the changes.
Fig.4-2 The Modified Binary Search
After the frequency/phase acquisition is complete, in other words, the ADPLL enters the lock state, the frequency or phase of the reference clock and that of the DCO output would still be changed by the PVT variations. For this reason, the system will enter the frequency/phase maintenance mode to make sure of the phase error being under control. In this mode, the value held in the phase-gain register determines the magnitude of the changes, and we will use another algorithm to adjust the phase-gain value, which will be introduced in the section of Control Unit later.
4.2 Circuit Design of The ADPLL
4.2.1 Phase/Frequency Detector
In the conventional ADPLL design, PFD is composed of frequency comparator and phase detector. The frequency comparator (FC) accepts the reference clock and the DCO output as its inputs. By these two signals, the FC generates FAST, SLOW,
and ENABLE output signals for the DCO. The PFD uses the reference clock edge to assert the DCO Enable signal, which forces the reference clock edge and the DCO output edge to align in phase. This initial phase alignment makes an accurate frequency comparison possible after one reference cycle. Then, the phase detector (PD) also uses the same two signals to generate AHEAD or BEHIND output signals.
Fig.4-3 Phase/Frequency Detector
As mentioned in the chapter 2, the conventional FC takes one-half reference cycle for synchronization before asserting SLOW or FAST. In the rest clock, the DCO is disabled. That would need two reference clock cycles to finish a full FC iteration.
To settle such difficulty, a dual-mode one-cycle PFD is proposed, shown is Fig. 4-3.
(a)
(b)
Fig.4-4 Timing diagram of the Phase/Frequency Detector (a) unlock state, (b) lock state (for example: divider ratio=2)
Above all, let us see Fig. 4-4 (a) and (b), which show the timing diagrams of two frequency comparison iterations in the unlock state and lock state, respectively. The operation flow of the modified PFD is roughly similar to the conventional PFD, shown in Fig. 2-18. However, compared to the conventional PFD, there are some
modifications in our design so as to reduce lock cycle of the ADPLL: First, the frequency and phase detection point is set at the falling edge of the reference clock.
Second, a new flag signal is generated by DCO enable generator circuit, shown in Fig.
4-5. It is realized based on a pulse generator, which is mainly composed of a delay element and a NADN gate. The DCO Enable signal will only disable the DCO before the rising edge of next reference clock cycle, and by using the replica of the DCO as the delay element, it will last half of the DCO output cycle to synchronize with the reference clock.
Fig.4-5 DCO Enable Generator
Then, the operation flow of the modified PFD will be introduced briefly in the following. As shown in Fig. 4-3, at first, for an accuracy frequency/phase comparison, the PFD uses the rising edge of the external reference clock to assert the DCO Enable at A, and the following falling edge captures the output and the inversion of DCO counter at B, the input to the synchronizer. Then, the synchronizer will pull up or pull down the FAST and Lock signal at C, depending on the early or late relation between the matched-delay reference clock and the output of DCO counter. If the output of
DCO counter is defined as FAST, and pulled up the FAST signal. Otherwise, it will be defined as SLOW, and pulled down the FAST signal. In addition, only when both the two synchronizers’ outputs are high, the Lock signal will be asserted, and the ADPLL will enter the lock state. Afterwards, the FAST and Lock signal will be transferred to the control unit, which will be introduced in the later section.
After the control unit operates completely, it will update the control word of DCO, therefore the DCO will operate in a new oscillation frequency to trace the reference clock further. Finally, the DCO Enable generator will force the DCO to be disabled at D, waiting for the next comparison cycle. Furthermore, as mentioned above, the disable time of DCO will last half of the DCO output cycle to synchronize with the reference clock. Consequently, the PFD could finish frequency and phase comparison in only one reference clock cycle.
4.2.2 Control Unit
Control unit (CU) will adjust the DCO control word to change DCO output frequency according to the FAST signal and Lock signal received from PFD.
Architecture of the control unit is shown in Fig. 4-6 (a), and it will adopt the modified binary search algorithm when the system is in the phase/frequency acquisition mode.
In implementing the gain strategy of the binary search algorithm, an adder/subtracter receive both the value of a frequency gain register and the DCO control word. The frequency gain register is a 11-b, unidirectional shift register with binary weighted bits, analogous to the DCO control word.
(a)
(b)
Fig.4-6 (a) Block diagram of the Control Unit (b) An example of the phase gain strategy
In the phase/frequency acquisition mode, first, CU will decide if it needs to shift the frequency gain word once to the right (i.e., decreases the gain by a factor of two) by telling if polarity of the FAST signal has changed. Then, the control word will be added to value in the frequency gain register (i.e., the frequency gain word) if the
signal is asserted. In a conventional implementation [5], the add MUX receives the odd bits of the frequency gain register (the add gain), and the subtract MUX receives the even bits of the frequency gain register (the subtract gain). However, in our design, the frequency gain word is used as both the add gain and subtract gain, as well as, the adder and subtracter are combined together such that it can save an adder or a subtractor circuit and also the associated logic in the muxes.
After the ADPLL is locked, the frequency of reference clock or DCO clock would still be influenced by the PVT variations, for this reason, the system have to enter the maintenance mode at this moment, the same as the conventional design [5]
[6]. Additionally, as mentioned above in this chapter, the phase maintenance and frequency maintenance modes in the conventional ADPLL are also combined to a phase/frequency maintenance mode in our design. Hence, the goal of this mode is to preserve the analogous match in frequency and the phase alignment of the DCO clock relative to the reference clock at the same time.
Similar to the operation of the phase/frequency acquisition mode, based on the PFD output, the ADPLL increments or decrements the DCO control word every reference cycle in the phase/frequency maintenance mode. However, the difference to the phase/frequency acquisition mode is that the magnitude of the changes to the DCO control word (i.e., the gain value) has changed to the value held in the phase gain register. Besides, in the maintenance mode, the ADPLL adopts a different gain strategy to adjust the gain value (the phase gain strategy). While the phase gain register still uses the bit-shifted gain technique of the acquisition mode, it now employs a variable shift displacement. This modification gives the ADPLL increased flexibility to reduce gain for improved DCO output jitter or increase gain for
improved phase and frequency tracking in the presence of drift.
Fig. 4-6 (b) shows an example of the procedure of gain value adjustment. The step 1. is to set the initial value of the 4-bit phase gain word as 1. The phase gain register will be shifted once (i.e., increases the phase gain value by a factor of 2) to the left whenever the control unit detects polarity of the FAST signal from the PFD remains the same for eight successive reference cycles. The register will be shifted once to the right (i.e., decreases the phase gain value by a factor of 2), otherwise, whenever the polarity of the FAST signal has changed. In conclusion, the gain register can only be 0001, 0010, 0100, and 1000. Therefore, the phase gain strategy can make sure of the phase error of the phase-lock loop being minimized.
4.2.4 The Sub-Circuit Design
(1) D Flip-Flop:
In the ADPLL, D Flip-Flop (DFF) have been used in many circuits, such as: the DCO counter, the synchronizers of PFD, the frequency gain register, the phase gain register, and the DCO control register. The DFFs are all realized by the true single-phase clocked circuits (TSPC), shown in Fig. 4-7, because of its good performance well-known at high frequency.
Fig.4-7 TSPC DFF
(2) Adder / Subtractor:
In the ADPLL design, there is roughly half of the reference cycle (i.e.,10nsec) for full operation of the control unit, therefore, for the power and area consideration, we can just use a 11-bit modified ripple adder/subtractor, which is shown in Fig. 4-9. In addition, the logical diagram and the transistor-level circuit of 1-bit full adder (FA) is also shown in Fig. 4-8 (a) and (b), respectively.
(a)
(b)
Fig.4-8 1-bit FA (a) logic diagram, (b) transistor-level circuit
Fig.4-9 11-bit modified ripple adder/subtractor
Chapter 5
The Implementation of Frequency Synthesizer
In this chapter, at first, we will introduce the fundamentals of frequency synthesizer. Then, the ADPLL-based frequency synthesizer based on the adjustable counter length mechanism will be presented. Finally, it also shows the implementation of layout and the simulation results.
5.1 Frequency Synthesizer Architecture
As mentioned in the chapter 1, synthesizers often require that the output frequency of a PLL be a multiple of the input frequency. The high accuracy for the different output frequency often mandates the use of PLLs in synthesizers because under locked condition, the output frequency of a PLL bears an exact relationship with the input frequency. In this section, we will introduce several architectures for the frequency synthesizer [16].
5.1.1 Integer-N Architecture
Depicted in Fig. 1-2, as mentioned above, such a topology produces fout=M‧fREF, where M (i.e., modulus) varies in unity steps from ML to MH. The frequency divider employed in Fig. 1-2 must provide a variable modulus given by M = ML + k, k = 0,1,…,N. An example of such a circuit is a “pulse-swallow divider,” illustrated in Fig.
5-1. The divider consists of a “prescaler,” a “program counter,” and a “swallow counter.” We briefly describe the operation of the circuit here. Let us first make three observations: (1) the prescaler divides the input by either N + 1 or N according to the logical state of the modulus control line, (2) the program counter always divides the prescaler output by P, and (3) the swallow counter divides the prescaler output by S, where S is determined by the digital input and can vary from 1 to the maximum number of channels. This counter also has a reset input. We will show that fout = fin / (NP + S).
Fig.5-1 Pulse swallow frequency divider
When the circuit begins from the reset state, the prescaler divides by N + 1. The prescaler output is divided by both the program counter and the swallow counter until the latter is “full,” i.e., it has counted S pulses. At this point, that is, after (N + 1)S cycles at the main input, the swallow counter changes the state of the modulus control line, making the prescaler divide fin by N. Note that before this change, the program counter has sensed a total of S pulses. After the modulus changes, the prescaler and program counter continue to divide until the latter is full. Since the program has already sensed S pulses, it requires P–S cycles at its input, and hence (P–S)N pulses at the main input, to reach overflow. Thus, the output generates one complete cycle for every (N + 1)S + (P–S)N = PN + S cycles at the input. The operation repeats after the swallow counter is reset.
The simplicity of the integer-N architecture has made it a popular choice for many decades. In RF systems, the synthesizer has commonly been partitioned into three separate chips: the VCO; the dual-modulus prescaler; and the combination of the program counter, the swallow counter, the PFD, and the charge pump. As the fast parts of the system, the VCO and the prescaler has typically been fabricated in silicon bipolar or GaAs technologies and the rest in CMOS technology. Note that a buffer is usually interposed between the VCO and the prescaler to isolate the former from the switching noise in the latter.
5.1.2 Fractional-N Architecture
In the integer-N architecture, the loop bandwidth is limited because the input
reference frequency must be equal to the channel spacing. This, in turn, results from the property that the output frequency changes by only integer multiples of fREF , In
“fractional-N” synthesizers, on the other hand, the output frequency can vary by a fraction of the input frequency, allowing the latter to be much greater than the channel spacing.
Fig. 5-2 (a) shows a simple phase-locked fractional-N architecture. In addition to the PFD, LPF, and VCO, the loop incorporates a pulse remover, a circuit that blocks one input pulse upon assertion of the remove command. Since under locked condition, the two frequencies presented to the phase detector must be equal, the average output frequency of the pulse remover equals fREF , and hence fout = fREF + 1/Tp , where 1/Tp is the period with which the remove command is applied. Note that fout can vary by a fraction of fREF because the frequency fp = 1/Tp can be derived from fREF by simple division. Provided by a crystal oscillator, fREF is typically limited to a few tens of megahertz. Thus, as shown in Fig. 5-2 (b), fractional-N loops incorporate a divider in the feedback to generate high output frequencies.
(a)
(b)
Fig.5-2 (a) Simple fractional-N synthesizer, (b) use of divider in the loop
While the original fractional-N topology was based on the pulse remover concept [17], modern implementations of this architecture operate on a somewhat different principle. Depicted in Fig.5-3, such a synthesizer replaces the pulse remover and the divider of Fig. 5-2 (b), with a dual-modulus prescaler. If the prescaler divides by N for A output pulses of the VCO and by N + 1 for B output pulses, then the equivalent divide ratio is equal to (A + B) / [A / N + B / (N + 1)]. This value can vary between N and N + 1 in fine steps by proper choice of A and B. The resulting modulus is sometimes written as N.f , where the dot denotes a decimal point and N and f represent the integer and fractional parts of the modulus.
Fig.5-3 Fractional-N synthesizer using a dual-modulus divider
As an example, consider the circuit in Fig. 5-4, where fREF = 1 MHz and N = 10.
Let us assume the prescaler divides by 10 for 9 reference cycles and by 11 for one reference cycle. The total number of output pulses is therefore equal to 9 x 10 + 11 = 101, whereas the reference produces 10 pulses. In other words, the divide ratio is equal to 10.1 and fout = 10.1 MHz.
With fREF in the range of tens of megahertz, the loop bandwidth of a fractional-N
With fREF in the range of tens of megahertz, the loop bandwidth of a fractional-N