Frequency Synthesizer Architecture

As mentioned in the chapter 1, synthesizers often require that the output frequency of a PLL be a multiple of the input frequency. The high accuracy for the different output frequency often mandates the use of PLLs in synthesizers because under locked condition, the output frequency of a PLL bears an exact relationship with the input frequency. In this section, we will introduce several architectures for the frequency synthesizer [16].

5.1.1 Integer-N Architecture

Depicted in Fig. 1-2, as mentioned above, such a topology produces f_out=M‧f_REF, where M (i.e., modulus) varies in unity steps from ML to MH. The frequency divider employed in Fig. 1-2 must provide a variable modulus given by M = M_L + k, k = 0,1,…,N. An example of such a circuit is a “pulse-swallow divider,” illustrated in Fig.

5-1. The divider consists of a “prescaler,” a “program counter,” and a “swallow counter.” We briefly describe the operation of the circuit here. Let us first make three observations: (1) the prescaler divides the input by either N + 1 or N according to the logical state of the modulus control line, (2) the program counter always divides the prescaler output by P, and (3) the swallow counter divides the prescaler output by S, where S is determined by the digital input and can vary from 1 to the maximum number of channels. This counter also has a reset input. We will show that f_out = f_in / (NP + S).

Fig.5-1 Pulse swallow frequency divider

When the circuit begins from the reset state, the prescaler divides by N + 1. The prescaler output is divided by both the program counter and the swallow counter until the latter is “full,” i.e., it has counted S pulses. At this point, that is, after (N + 1)S cycles at the main input, the swallow counter changes the state of the modulus control line, making the prescaler divide fin by N. Note that before this change, the program counter has sensed a total of S pulses. After the modulus changes, the prescaler and program counter continue to divide until the latter is full. Since the program has already sensed S pulses, it requires P–S cycles at its input, and hence (P–S)N pulses at the main input, to reach overflow. Thus, the output generates one complete cycle for every (N + 1)S + (P–S)N = PN + S cycles at the input. The operation repeats after the swallow counter is reset.

The simplicity of the integer-N architecture has made it a popular choice for many decades. In RF systems, the synthesizer has commonly been partitioned into three separate chips: the VCO; the dual-modulus prescaler; and the combination of the program counter, the swallow counter, the PFD, and the charge pump. As the fast parts of the system, the VCO and the prescaler has typically been fabricated in silicon bipolar or GaAs technologies and the rest in CMOS technology. Note that a buffer is usually interposed between the VCO and the prescaler to isolate the former from the switching noise in the latter.

5.1.2 Fractional-N Architecture

In the integer-N architecture, the loop bandwidth is limited because the input

reference frequency must be equal to the channel spacing. This, in turn, results from the property that the output frequency changes by only integer multiples of fREF , In

“fractional-N” synthesizers, on the other hand, the output frequency can vary by a fraction of the input frequency, allowing the latter to be much greater than the channel spacing.

Fig. 5-2 (a) shows a simple phase-locked fractional-N architecture. In addition to the PFD, LPF, and VCO, the loop incorporates a pulse remover, a circuit that blocks one input pulse upon assertion of the remove command. Since under locked condition, the two frequencies presented to the phase detector must be equal, the average output frequency of the pulse remover equals fREF , and hence fout = fREF + 1/Tp , where 1/Tp is the period with which the remove command is applied. Note that fout can vary by a fraction of fREF because the frequency fp = 1/Tp can be derived from fREF by simple division. Provided by a crystal oscillator, fREF is typically limited to a few tens of megahertz. Thus, as shown in Fig. 5-2 (b), fractional-N loops incorporate a divider in the feedback to generate high output frequencies.

(a)

(b)

Fig.5-2 (a) Simple fractional-N synthesizer, (b) use of divider in the loop

While the original fractional-N topology was based on the pulse remover concept [17], modern implementations of this architecture operate on a somewhat different principle. Depicted in Fig.5-3, such a synthesizer replaces the pulse remover and the divider of Fig. 5-2 (b), with a dual-modulus prescaler. If the prescaler divides by N for A output pulses of the VCO and by N + 1 for B output pulses, then the equivalent divide ratio is equal to (A + B) / [A / N + B / (N + 1)]. This value can vary between N and N + 1 in fine steps by proper choice of A and B. The resulting modulus is sometimes written as N.f , where the dot denotes a decimal point and N and f represent the integer and fractional parts of the modulus.

Fig.5-3 Fractional-N synthesizer using a dual-modulus divider

As an example, consider the circuit in Fig. 5-4, where fREF = 1 MHz and N = 10.

Let us assume the prescaler divides by 10 for 9 reference cycles and by 11 for one reference cycle. The total number of output pulses is therefore equal to 9 x 10 + 11 = 101, whereas the reference produces 10 pulses. In other words, the divide ratio is equal to 10.1 and fout = 10.1 MHz.

With fREF in the range of tens of megahertz, the loop bandwidth of a fractional-N synthesizer can be as high as a few megahertz, yielding a fast lock transient as well as suppressing the VCO close-in phase noise.

Fig.5-4 Example of a fractional-N synthesizer