Digitally Controlled Delay Element

There are several different architectures that have been used to implement a digitally controlled delay element (DCDE). However, they can generally be classified into the parallel-inverter-based and the single-inverter-based delay elements, individually. First, we take the parallel-inverter-based DCDEs into consideration, which are summarized in [22].

One simple DCO consists of a bank of tri-state inverter buffers was proposed in [3], [20], [21], as shown in Fig. 3-4. By enabling the numbers of tri-state inverter buffers, we can control the resolution of DCO. It is simple and easy to implement;

however, it needs large area and high power dissipation for the fine tune necessarily in the DCO design. Besides, the resolution is hard to be uniform.

Fig.3-4 DCDE composed of a tri-buffer matrix

The other example, as shown in Fig. 3-5, a DCO is implemented by an add-or-inverter (AOI) cell and or-and-inverter (OAI) cell with two parallel tri-state inverters was proposed in [23]. The basic method is to adjust the driving capability with resistance control. The advantage is that this fine tune method of DCO cell has less area and power dissipation compared with [3], [20], [21]. However, since it’s based on AOI-OAI cell to change the delay resolution, the resolution step is also hard to be uniform and sensitive to power-supply variation. Besides, is also requires an additional decoder for mapping the control input of AOI-OAI cell.

OAI

Fig.3-5 DCDE composed of an AOI-OAI

Moreover, we will keep on discussing the single-inverter-based DCDEs. Within most of the architectures, usually, a switch network of nMOS transistors is placed at the source of the nMOS transistor in a CMOS inverter, as shown in Fig. 3-6. In this circuit only the delay of the falling edge of the output voltage can be controlled by the

switch network of pMOS transistors should be placed at the source of the pMOS transistor (M2) in the inverter.

Fig.3-6 Basic structure of a delay element

The number of nMOS transistors in the switch network depends on the desired number of different separate delays and the required delay resolution. Depending upon the digital input vector, the equivalent resistor of the switch network (or the current passing through it) changes and causes the delay of the inverter to change [5], [13].

One of the main drawbacks of these delay elements is that the delay of the circuit may not change monotonically with respect to the input vector. It makes the design of the circuit more difficult, hence the circuit should be thoroughly simulated for all the possible combinations of the input vector. For example, in the case of the circuit used in [13], finding the sizes of the transistors in the switching network is a matter of optimal coding.

Fig. 3-7 illustrates a DCDE based on the current-starved inverter. The charging and discharging currents of the output capacitance (CL1) of the inverter, composed of M1 and M2, are controlled by two sets of current-controlling nMOS (Mn0, Mn1, … ) and pMOS (Mp0, Mp1, … ) transistors at the source of M1 and M2, respectively. The current controlling transistors are sized in a binary fashion. It allows us to achieve binary incremental delays. As can be seen, by applying a specific binary vector to the controlling transistors, a combination of transistors is turned on at the sources of M1

and M2 transistors. Such an arrangement controls the rise time and fall time, and hence the delay, of the output voltage of the inverter.

Fig.3-7 Current-starved delay element

Fig. 3-8 illustrates another technique for implementing a DCDE. In this circuit, a variable resistor is used to control the delay. A stack of n rows by m columns of nMOS transistors is used to make the variable resistor. This resistor subsequently controls the delay of M1. In the circuit of Fig. 3-8, only the falling edge of the Out can be changed with the input vector. Similarly, another stack of pMOS transistors can be used at the source of the pMOS transistor, M2, to have control over the delay of the rising edge.

Fig.3-8 Another delay element

One of the problems with the above mentioned single-inverter-based DCDE architectures is the nonmonotonic delay behavior with ascending binary input pattern.

As can be seen in the circuits of Figs. 3-7 and 3-8, the input vector changes the effective resistance of transistor(s) placed at the source of the nMOS or pMOS transistors of the inverter. This not only changes the resistance at the source of M1 or

M2, but also changes the parasitic capacitance associated with transistors at these nodes. This is because the parasitic capacitance at the drain of a MOSFET is different in the ON and OFF states. Therefore, there are two factors depending on the input vector to affect the delay:

(1) The resistance of the controlling transistors:

The circuit delay can be increased/decreased by increasing/decreasing the effective ON resistance of the controlling transistors at the source of M1 (M2).

(2) The effective parasitic capacitance of the controlling transistors:

As the effect capacitance of the controlling transistors at the source of M1 (M2) increases due to the input vector, the charge sharing effect causes the capacitance at the output of the current-starved inverter to be (dis)charged faster and the overall delay of the circuit decreases.

Because the W/L ratio of the controlling transistors have to change in binary fashion, usually, the channel length L, is thus increased to realize a small W/L ratio. A longer transistor puts a higher resistance and a lager parasitic capacitance at the source of M1 (M2). A larger resistance increases the delay; however, a larger parasitic capacitance decreases the delay. Therefore, it may make monotonic characteristic of the DCDE can not be ensured with ascending input vector. This situation will be further complicated as the number of delay controlling transistors increases.

For this reason, it becomes difficult to predict the circuit delay for a given input vector and will cause the circuit to be simulated for all the possible input combinations during the design phase. The design of high-resolution delay element becomes a nontrivial task due to the lack of a one-to-one relationship between

not met, it is not very clear whether the size of a transistor in the nMOS or pMOS network should be increased or decreased.

A new architecture, which eliminates the above-mentioned non-monotonic delay behavior, is proposed in [14]. Fig. 3-9 shows the new delay element. As can be seen in this figure, the delay of a current-starved inverter, M8 – M11, is controlled by the current passing through M8 and M11. Transistor M8 controls the fall time of the output of this inverter while M11 controls the rise time. The current passing through M8 is determined by M5 and the current passing through M5. Meanwhile, the current passing though M11 is determined by transistors M5 – M7 and the current passing through M5.

Fig.3-9 New DCDE architecture

The delay controlling pMOS transistors M_1, M_2, M_3,… should be sized in a binary fashion. The input vector turns these pMOS transistors on or off. In this way, the current passing through M5 will be determined by the input vector. This

controlling current will later be mirrored to M8 and M11, and controls the delay of the inverter. Note that transistor Mp is always on. This circuit can implement 2^N different delays where N is the number of pMOS controlling transistors. Note that the parasitic capacitances at the source of M9 and M10 are the same for all the input vector combinations.

Therefore, when the input vector changes, only the (dis)charging current of the inverter changes, and the charge sharing remains the same. This causes the delay of the circuit to change monotonically with respect to the input vector, which makes the design of this circuit straightforward compared to the other delay elements.

Another point which is worth mentioning is that both the rising and falling edge delays can be varied by this circuit. This has come at the expense of three more transistors (M6, M7, and M11), while in the conventional delay elements, the number of added transistors for this purpose is more. Note that transistors M6, M7, and M11 do not need to be very large, while the delay-controlling transistors in conventional delay elements are large and consume extra area due to their binary sizing scheme.

The design procedures of the new DCDE are explained as follows [15]:

(1) Transistor M8 / M11 should be much smaller than M9 / M10 such that the discharging current is controlled by M8 / M11. The ratio of transistors M10 and M9

should be μⁿ /μ^p where μⁿ and μ^p represent electron and hole mobilities. Transistor (M5, M6) / M7 can be the same size as M8 / M11, since these transistors make the current mirrors. However, these transistors may have different sizes to reduce the static power consumption of the DCDE, as explained in [14].

(2) The number of pMOS controlling transistors (N) can be obtained from the desired

N

contain one more pMOS transistor (M4) which is always on. In our case, we have selected 7+1 pMOS controlling transistors, which provide us 128 different delays.

(3) Assuming transistors M1 to M7 are not present, transistor Mp is sized to get the maximum desired delay.

(4) After sizing Mp, we put another pMOS transistor (e.g., M0) in parallel to Mp to obtain the minimum desired delay. Note that M0 is not shown in the figure since this transistor is subsequently fragmented into N (7, in our case) smaller transistors.

(5) Transistor M0 is now fragmented into N=7 transistors, (M1 to M7), in a binary