Chapter 5 The Implementation of Frequency Synthesizer
5.4 Layout Implementation and Simulation Result
In this section, we will show the layout and simulation result of our ADPLL design. In the layout implementation phase, we should take care about the floor plan first, then, also consider the shape of each block, as well as the matching and
Fig. 5-10 and Fig. 5-11 show the layout implementation and floor plan respectively. The main signal path among these building blocks in ADPLL is roughly counterclockwise, in this way we can place these blocks compactly. Fig. 5-12 shows the area occupation ratio of each building block in ADPLL; 32% of the overall area is for DCO and its replica delay element, 56% for control unit, and 12% for PFD. With regard to power-consumption distribution in the ADPLL, as shown in Fig. 5-13, because of the high operating frequency of DCO, the DCO and its replica circuit dissipate a large part of total power dissipation in spite of their smaller area occupation than all of other circuits in the ADPLL.
Fig.5-10 Layout of the ADPLL
Fig.5-11 Floor Plan of the ADPLL
Area Distribution
PFD 12%
Control Unit 56%
DCO (+replica)
32%
Fig.5-12 Area Distribution of the ADPLL
Power Consumption Distribution (@ 1GHz)
DCO (+replica) 58%
PFD 7%
Control Unit 35%
Fig.5-13 Power-Consumption Distribution of the ADPLL
Thereupon, we will present the overall simulation results with different operating frequency, and the input reference clock frequency is always set as 50 MHz. Fig. 5-14, Fig. 5-15, Fig. 5-16, Fig. 5-17, Fig. 5-18, and Fig. 5-19 show the lock process of ADPLL in output clock of 300 M, 400 M, 500 M, 600 M, 850 M, and 1-GHz respectively. Each figure includes three sub-figures, they are the overall lock process, the zoom in of lock process, and the locked state of ADPLL individually.
Besides, within each sub-figure, there are four main signals are shown: the reference clock, DCO output clock, LOCK signal, and value of DCO control word.
The reference clock is from the matched delay clock of the input reference signal.
Fig.5-14 (a) The overall lock process of 300MHz target frequency.
Fig.5-14 (c) The locked state of 300MHz target frequency.
Fig.5-15 (a) The overall lock process of 400MHz target frequency.
Fig.5-15 (b) The zoom in of lock process of 400MHz target frequency.
Fig.5-16 (a) The overall lock process of 500MHz target frequency.
Fig.5-16 (b) The zoom in of lock process of 500MHz target frequency.
Fig.5-16 (c) The locked state of 500MHz target frequency.
Fig.5-17 (a) The overall lock process of 600MHz target frequency.
Fig.5-17 (b) The zoom in of lock process of 600MHz target frequency.
Fig.5-17 (c) The locked state of 600MHz target frequency.
Fig.5-18 (a) The overall lock process of 850MHz target frequency.
Fig.5-18 (b) The zoom in of lock process of 850MHz target frequency.
Fig.5-18 (c) The locked state of 850MHz target frequency.
Fig.5-19 (a) The overall lock process of 1GHz target frequency.
Fig.5-19 (b) The zoom in of lock process of 1GHz target frequency.
Fig.5-19 (c) The locked state of 1GHz target frequency.
14
300 400 500 600 850 1000
operating freq.(MHz)
lock cycle
Fig.5-20 Lock cycle VS. operating frequency
0
300 400 500 600 850 1000
operationg freq.(MHz)
jitter(p-p, psec)
Fig.5-21 Jitter VS. operating frequency
0
300 400 500 600 850 1000
operating freq.(MHz)
power dissipation(mW)
Fig.5-22 Power dissipation VS. operating frequency
Finally, Fig. 5-20, Fig. 5-21, and Fig. 5-22 present performance summaries of the ADPLL-based frequency synthesizer in different operating frequency. As shown in Table 5-2, compare to other ADPLL circuit design, our ADPLL owns the largest frequency range and the monotonicity characteristic due to the new DCO design. In addition, our ADPLL needs the smallest area and power cost because of its simplicity, and also has the fewer lock cycles by using the modified PFD.
Table 5-2 Performance comparison of ADPLL
Design JSSC04 [3] JSSC03 [23] JSSC03 [28] This Work
Chapter 6
Conclusion and Future Work
6.1 Conclusion
In this thesis, an ADPLL-based frequency synthesizer with low power and area cost, wide frequency range, and short lock cycle is proposed.
A DCO with features of wide frequency range, and low power consumption is proposed. By using the new type digitally controlled delay element (DCDE), a digitally controlled oscillator (DCO) with characteristics of its monotonicity is presented, which makes the DCO design more straightforward. In addition, compared with the conventional architecture, a dual-mode one-cycle PFD used to reduce the lock cycle time is also presented.
Table 6-1. Performance Summary of the Frequency Synthesizer ADPLL-based Frequency Synthesizer
Reference clock 50MHz
Output Clock Frequency 300MHz / 400MHz / 500MHz / 600MHz / 850MHz / 1GHz
Jitter (p-p) 46ps @ 1GHz
120ps @ 300MHz (worst case) Locked time <=16 input cycles
Power consumption 3.1mW @ 1GHz
Area 100um x 120um
Supply voltage 1.2V
Process TSMC 0.13um CMOS process
DCO
Frequency Range 260MHz ~ 1.15GHz
Resolution 11bits (0.4ps ~ 20ps / LSB)
Power consumption 0.9mW @ 1GHz
In conclusion, with the specification, the proposed ADPLL-based frequency synthesizer is suitable for high speed clock generation in high speed DSPs applications.
6.2 Future Work
In the recent year, low power is a more and more important issue in circuit design. However, most techniques to reduce power dissipation of integrated circuits are to choose system and circuit parameters at design time. In fact, in some applications, it is a more efficiency way of adjusting the circuit during operation, such as: voltage scaling or lowering the operating clock frequency. The related control schemes have been proposed in [24]-[27].
To reduce the power dissipation, it usually needs different voltage or frequency in a low power system. Hence, in our future work, we can take advantage of the adaptive voltage scaling (AVS) scheme in our ADPLL to decrease the power
provide several different supply voltage for the DCO, which consumes a great part of the total power dissipation in the ADPLL. Therefore, by scaling down the supply voltage of DCO, we can save much power dissipation while still meeting the same specification.
S300M S400M S500M S600M S850M S1-G
PFD
Fig.6-1 The ADPLL with AVS
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Vita
PERSONAL INFORMATION Birth Date: January. 04, 1981 Birth Place: Taipei, Taiwan, R.O.C.
Address: Department of Electronics Engineering National Chiao Tung University 1001 Ta-Hsueh Road
Hsin-chu, Taiwan 30010, R.O.C.
E-Mail Address: ujcc.ee92g@nctu.edu.tw
EDUCATION
B.S. [2003] Department of Electronical Engineering, National Cheng-Kung University.
M.A. [2006] Institute of Electronics, National Chiao-Tung University.