Research Motivation

The phase-locked loop (PLL) has been widely used in electronics, communication, and instrumentation today. Examples include memories, microprocessors, hard disk drive electronics, RF and wireless transceivers, and optical fiber receivers. In this section, we show some applications that demonstrate the versatility of phase locking. They are Frequency Multiplication and Synthesis, Skew Reduction, and Jitter Reduction, separately [1].

Frequency Multiplication A PLL can be modified such that it multiplies its input frequency by a factor of M. As shown in Fig.1-1, if the output frequency of a PLL is divided by M and applied to the phase detector, we have fout=M‧fin. From another point of view, since f_D= f_out /M and f_D and f_in must be equal in the locked condition, the PLL multiplies fin by M. The %M circuit is realized as a counter that produces one output pulse for every M input pulses.

Fig.1-1 Frequency multiplication

The frequency-multiplying loop exhibits two interesting properties. First, the PLL provides a multiplication factor exactly equal to M. Second, the output frequency can be varied by changing the divide ratio M, an extremely useful property in synthesizing frequencies.

Frequency Synthesis Some systems require a periodic waveform whose frequency (a) must be very accurate (e.g., exhibit an error less than 10ppm), and (b) can be varied in very fine steps (e.g., in steps of 30 kHz from 900 MHz to 925 MHz).

Commonly encountered in wireless transceivers, such requirements can be met through frequency multiplication by PLLs.

Fig.1-2 Frequency synthesizer

Fig.1-2 shows the architecture of a phase-locked frequency synthesizer. The channel control input is a digital word that varies the value of M. Since f_out=M‧f_REF , the relative accuracy of fout is equate to that of fREF . For this reason, fREF is derived from a stable, low-noise crystal oscillator. Note that fout varies in steps equal to fREF if M changes by one each time.

CMOS frequency synthesizers achieving gigahertz output frequency have been reported. Issues such as noise, sidebands, settling speed, frequency range, and power dissipation continue to challenge synthesizer designers.

Skew Reduction The earliest usage of phase locking in digital systems was for skew reduction. Suppose a synchronous pair of data and clock lines enter a large digital chip as shown in Fig.1-3. Since the clock typically drives a large number of transistors and long interconnects, it is first applied to a large buffer. Thus, the clock distributed on the chip may suffer from substantial skew with respect to the data, an undesirable effect because it reduces the timing budget for on-chip operations.

Fig.1-3 Skew between data and buffered clock

Now consider the circuit shown in Fig.1-4, where CKin is applied to an on-chip PLL and the buffer is placed inside the loop. Since the PLL guarantees a nominally-zero phase difference between CKin and CKB , the skew is eliminated.

From another point of view, the constant phase shift introduced by the buffer is divided by the infinite loop gain of the feedback system. Note that the VCO output, VVCO , may not be aligned with CKin , a nonetheless unimportant issue because VVCO

is not used.

Fig.1-4 Use of a PLL to eliminate skew

Jitter Reduction Many applications must deal with jittery waveforms. Random binary signals experience jitter because of (a) crosstalk on the chip and in the package (b) package parasitics, (c) additive electronic noise of devices, etc. Such waveforms are typically “retimed” by a low-noise clock so as to reduce the jitter. Illustrated in Fig.1-5(a), the idea is to resample the midpoint of each bit by a D flipflop that is driven by the clock. However, in many applications, the clock may not be available independently. For example, an optical fiber carries only the random date stream, providing no separate clock waveform at the receive end. The circuit of Fig.1-5(a) is therefore modified as shown in Fig.1-5(b), where a “clock recovery circuit” (CRC) produces the clock from the data. Employing phase locking with a relatively narrow

loop bandwidth, the CRC minimizes the effect of the input jitter on the recovered clock.

(a)

(b)

Fig.1-5 (a) Retiming data with D flipflop driven by a low-noise clock (b) use of a phase-locked clock recovery circuit to generate the clock

Phase locked loop (PLL) based clock generators for microprocessor are often required for on-chip clock generation and multiplication to produce several unrelated clocks with different frequency for other sub-systems. In traditional mixed mode circuit system, PLL is usually implemented in analog building block. Recently, the SoC (system-on-a-chip) architecture has become the underlying architecture for many embedded systems. That means conventional analog PLL integrated with digital circuits is inevitable. Integrating an analog circuit on a die with digital circuits,

however, has a large amount of generated digital noise. Besides, analog PLL is much more sensitive to process variation. It is too hard to use the same analog PLL design in different process [2], [3]. On the other hand, ADPLL are much easier to implement without targeting a specific technology. Their area would also scale down rapidly as the technology shrinks if only active components are used.

Since the implementation of analog component in a digital environment is not a simple task, the linear phase-locked loop (LPLL) and classical digital phase-locked loop (DPLL) which relay on analog component have been replaced by the all digital phase-locked loop (ADPLL) [4]-[7]. The ADPLL becomes more and more popular in recently year. In addition, the ADPLL has characteristics of fast frequency locking, full digitization, and good stability.