Summary

In this chapter, we propose a novel, simple, reproducible, and reliable technique for the design of high-density HfO2 nanocrystals through the spinodal decomposition of hafnium silicate. Our nanocrystal memory exhibits superior characteristics in terms of negligible lateral or vertical migration of stored charge and good disturbance characteristics. The cells after 10k P/E cycling also show a long retention time and excellent endurance. With these superior performance, we believe that HfO2

nanocrystal Flash memory is quite suitable for the two-bit operation and that it has

great potential for replacing the ONO stack in conventional SONOS-type Flash memories.

Fig. 2.1 Schematic representation of the HfO2 nanocrystal Flash memory cell structure and localized charge storage.

Fig. 2.2 Planar-view HRTEM image of the HfO2 nanocrystals for the 10nm thickness sample. The cell size is 5-8 nm and the dot density is 0.9-1.9 ¯ 10¹² cm^–2. The inset shows the diffraction patterns of the as-deposited and 900°C-RTA-treated samples.

Table 2.1 Average elemental compositions in the HfSiOx silicate layers, as examined through EDS analysis of the as-deposited and 900°C-RTA-treated samples.

Fig. 2.3 (a) Planar-view HRTEM image of the HfO2 nanocrystals for the 2nm thickness sample. The cell size is 3-7 nm and the dot density is 1.2-2.0 ¯ 10¹² cm^–2. The inset shows the diffraction pattern of the RTA-treated samples.

Fig. 2.3 (b) Planar-view HRTEM image of the HfO2 nanocrystals for the 2nm thickness sample. The cell size is 4-7 nm and the dot density is 2.1-3.2 ¯ 10¹² cm^–2. The inset shows the diffraction pattern of the RTA-treated sample.

Table 2.2 Comparison table of the different thickness samples of HfSiOx silicate layers after 900°C-RTA-treated.

Fig. 2.4 XPS spectra of the as-deposited and 900°C-RTA-treated samples. (a) Hf 4f;

(b) Si 2p. These spectra indicate that the Hf-silicate was fully converted to HfO2 and SiO2 through phase separation after PDA at 900 °C under O2.

Fig. 2.4 XPS spectra of the as-deposited and 900°C-RTA-treated samples. (a) Hf 4f;

(b) Si 2p. These spectra indicate that the Hf-silicate was fully converted to HfO2 and SiO2 through phase separation after PDA at 900 °C under O2.

Fig. 2.5 Ids-Vgs curves of programmed memories with different programming conditions. The programming time is 10μs. A memory window of larger than 3V can be achieved with Vg= Vd=10V programming operation.

Gate voltage (V)

Fig. 5(a)

(a)

Fig. 2.6 (a) Program characteristics of HfO2 nanocrystal memory devices with different programming conditions. A memory window of about 5V can be achieved with Vg=Vd=10V, and time=100μs programming operation. (b). Erase characteristics of HfO2 nanocrystal memory devices with different erasing voltages.

Time (sec)

10^-7 10^-6 10^-5 10^-4 10^-3 10^-2 10^-1 10⁰

Vt shift (V)

0 1 2 3 4 5 6

Vd=5V, Vg=9V Vd=7V, Vg=9V Vd=9V, Vg=9V Vd=10V, Vg=10V

Time (sec)

10

^-6

10

^-5

10

^-4

10

^-3

10

^-2

10

^-1

10

⁰

Vt shift (V)

-3 -2 -1

0 ^V

^g

^{= -5V, V}

^d

^=10V

V

_g

= -4V, V

_d

=10V V

_g

= -3V, V

_d

=10V

(b)

Fig. 2.6 (a) Program characteristics of HfO2 nanocrystal memory devices with different programming conditions. A memory window of about 5V can be achieved with Vg=Vd=10V, and time=100μs programming operation. (b). Erase characteristics of HfO2 nanocrystal memory devices with different erasing voltages.

Fig. 2.7 Retention characteristics of HfO2 nanocrystal memory devices at T=25°C and 125°C. Very low charge loss is seen even after 10⁵ seconds.

Time (sec)

10⁰ 10¹ 10² 10³ 10⁴ 10⁵ 10⁶ 10⁷ 10⁸

Vt (V)

0 1 2 3 4

5 Erase state, T= 25^。C Program state, T= 25^。C Erase state, T=125^。C Program state, T=125^。C

Fig. 2.8 Endurance characteristics of HfO2 nanocrystal memory devices. Negligible degradation is found even after 10⁶ P/E cycles.

PE cycles

10⁰ 10¹ 10² 10³ 10⁴ 10⁵ 10⁶

Vt (V)

0 1 2 3 4 5

Erase state (Vg= -5V, Vd= 10V, time=1ms) Program state (Vg= 9V, Vd= 9V, time=10us)

bit 2 prog Vg=5 Vs=5

(Bit1,Bit2)=(0,1), forward read for Bit1, Vd=0.1V, Vs=0V (Bit1, Bit2)=(0,1), reverse read for Bit1, Vd=0V, Vs=2.3V (Bit1,Bit2)=(1,0), forward read for Bit2, Vd=0V, Vs=0.1V (Bit1,Bit2)=(1,0), reverse read for Bit2, Vd=2.3V, Vs=0V

Fig. 2.9 Ids–Vgs Curves of the two-bit memory in a cell; forward read and reverse read for programmed bit1 and programmed bit2.

Table 2.3 Operation principles and bias conditions utilized during the operation of the HfO2 nanocrystal Flash memory cell.

Drain Voltage (V)

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

Vt (V)

0 1 2 3 4

Initial

T = 85

^o

C, stress time=2000sec T = 125

^o

C, stress time=2000 sec

Fig. 2.10 Lateral charge migration characteristics of the HfO2 nanocrystal Flash memory cells after 10k P/E cycling.

Time (sec)

10

⁰

10

¹

10

²

10

³

10

⁴

Vt (V)

0 1 2 3 4 5

Vg=-5V, T=25^oC Vg=-5V, T=125^oC Vg=0V, T=25^oC Vg=0V, T=125^oC

Fig. 2.11 Vertical charge migration characteristics of the HfO2 nanocrystal Flash memory cells after 10k P/E cycling.

Temperature (

^o

C)

227.0 203.2 181.5 161.8 143.7 127.0 111.6

Retention time (sec)

10

⁷

10

⁸

10

⁹

10

¹⁰

10

¹¹

1000/Temperature (1/K)

2.0 2.1 2.2 2.3 2.4 2.5 2.6 E _A = 2.1~3.3eV

Fig. 2.12 Activation energy characteristics of the HfO2 nanocrystal Flash memory cells taken from five samples.

Read disturb time (sec)

10

⁰

10

¹

10

²

10

³

V

t

shift (V)

-1.0 -0.5 0.0 0.5 1.0 1.5 2.0

Vg=3V, Vd=2.5V Vg=3V, Vd=3V Vg=3V, Vd=3.5V Vg=3V, Vd=4V Vg=3V, Vd=5V

Fig. 2.13 Read disturbance characteristics of the HfO2 nanocrystal memory devices.

No significant Vt shift occurred for Vd < 4, even after 1000 s at 25 °C.

Drain disturb time (sec)

10

⁰

10

¹

10

²

10

³

Program state V

t

shift (V)

-0.6 -0.4 -0.2 0.0 0.2

Vd=5V, T=25^oC Vd=9V, T=25^oC Vd=5V, T=125^oC Vd=9V, T=125^oC

Fig. 2.14 Drain disturbance characteristics of the HfO2 nanocrystal memory cells.

After 1000 s at 25 °C, only a 0.3V drain disturb margin was observed.

Gate disturb time (sec)

10

⁰

10

¹

10

²

10

³

V

t

(V)

1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8

V

_g

=10V, V

_d

=V

_s

=V

_sub

=0V, T=25

^o

C V

_g

=9V, V

_d

=V

_s

=V

_sub

=0V, T=25

^o

C

Initial V

_t

= 1.58V

Fig. 2.15 Gate disturbance characteristics of the HfO2 nanocrystal memory devices. A threshold voltage shift of only 0.22 V occurred after stressing at Vg = 9 V and Vs = Vd

= Vsub = 0 V for 1000 s.

V

_gbl

(V)

programming to different Vt levels.

Vt increase

A B

PE cycles

10

⁰

10

¹

10

²

10

³

10

⁴

10

⁵

10

⁶

10

⁷

10

⁸

10

⁹

V

t

(V)

1 2 3 4 5

6

Erase state (V_g= -5V, V_d=10V, t=1ms) Program state (V_g= 9V, V_d= 9V, t=10us)

Fig. 2.17 Endurance characteristics of the HfO2 nanocrystal memory after 10k P/E cycling.

Retention time (sec)

10

⁰

10

¹

10

²

10

³

10

⁴

10

⁵

10

⁶

10

⁷

10

⁸

Vt (V)

1 2 3 4

5

Erase state, T=25^oC Program state, T=25^oC Erase state, T=125^oC

Program state, T=125^oC

10 years

Fig. 2.18 Retention characteristics of the HfO2 nanocrystal memory after 10k P/E cycling at 25 and 125 °C. No significant charge loss occurred at 25 °C; and only a very low charge loss occurred at 125 °C.

Table 2.4 Memory characteristics of the device fabricated in this study and the comparison with reported data for various SONOS-type memory cells.

Time (sec)

10^-7 10^-6 10^-5 10^-4 10^-3 10^-2 10^-1 10⁰

Vt shift (V)

0 1 2 3 4 5 6

t=2nm, V_d=10V, V_g=10V t=4nm, V_d=10V, V_g=10V t=6.1nm, V_d=10V, V_g=10V

Fig. 2.19 Program characteristics of HfO2 nanocrystal memory devices with different tunnel oxide thickness for different programming conditions

Time (sec)

10

^-6

10

^-5

10

^-4

10

^-3

10

^-2

10

^-1

10

⁰

Vt shift (V)

-3 -2 -1

0 ^{t=2nm, V}

^g

^{= -5V, V}

^d

^=10V

t=4nm, V

_g

= -5V, V

_d

=10V t=6.1nm, V

_g

= -5V, V

_d

=10V

Fig. 2.20 Erase characteristics of HfO2 nanocrystal memory devices with different tunnel oxide thickness for different programming conditions

Time (sec)

10

⁰

10

¹

10

²

10

³

10

⁴

10

⁵

10

⁶

10

⁷

10

⁸

V t (V)

0 1 2 3 4 5

t=6nm, T=125

^o

C t=4nm, T=125

^o

C t=2nm, T=125

^o

C

Fig. 2.21 Retention characteristics of HfO2 nanocrystal memory devices at 125°C with different tunnel oxide thickness.

Tunnel oxide thickness (nm)

0 2 4 6 8

Activation energy (eV)

2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4

Fig. 2.22 The activation energy of the traps in the HfO2 nanocrystals for the fresh device with different tunnel thickness

PE cycles

10⁰ 10¹ 10² 10³ 10⁴ 10⁵ 10⁶

Vt (V)

0 1 2 3 4 5 6

Erase state, tunnel oxide=20A Program state, tunnel oxide=20A Erase state, tunnel oxide=61A Program state, tunnel oxide=61A

Fig. 2.23 Endurance characteristics of HfO2 nanocrystal memory devices with different tunnel oxide thickness.

Vt distribution

Vt(V)

0 1 2 3 4 5

count

0 2 4 6 8 10 12 14 16 18

20

V_g=9V, V_d=5V, t=10μs

V_g=9V, V_d=9V, t=10μs

V_g=10V, V_d=10V, t=10μs

V_g=11V, V_d=11V, t=10μs

Fig. 2.24 Four-level threshold voltage (Vth) distribution of multilevel programming.

Chapter 3

Annealing Temperature Effect on the

Performance of Nonvolatile HfO

₂

SONOS-type Flash Memory

3.1 Introduction

SONOS-type (poly-Si-oxide-nitride-oxide-silicon) Flash memories have recently attracted much attention for the application in the next-generation nonvolatile memories [3.1].Based on discrete storage nodes, the SONOS-type Flash memories have grand potency for achieving high program/erase speed, low programming voltage, low-power performance, large memory window, excellent retention, endurance, and disturbance characteristics [3.2-3.6]. Hafnium oxide (HfO2) is considered to be a promising candidate for the charge trapping layer for the SONOS-type Flash memory instead of Si3N4 film [3.7]. The high-κ dielectric film, HfO2, is expected to have better charge trapping characteristics than the conventional Si3N4 films for sufficient density of trap states and deep trap energy level to achieve longer retention time [3.8-3.9]. This feature makes HfO2 be more helpful in scaling the tunnel oxide for enhancing the performance and more suitable for the development of the SONOS-type memory with multi-bit operation [3.10-3.11].

However, using HfO2 film as the trapping layers has the issue of lateral migration of trapped electrons and then leads to degraded retention [3.12].

In this chapter, we investigated the performances of the HfO2 SONOS-type Flash memories by changing post-deposition annealing temperatures for the HfO2 trapping layer. Besides, we show the high-κ dielectric film such as HfO2 can trap electron and

hole for the trapping characteristics.

3.2 Experimental

The fabrication process of the HfO2 SONOS-like Flash memory is shown in Figure 3.1. A 2nm direct tunneling oxide was thermally grown on a (100)-oriented p-type Si substrate. A 5nm amorphous HfO2 layer was subsequently deposited by electron beam evaporation method with pure Hafnium dioxide (HfO2) (99.9% pure) targets. Next, the samples were subject to rapid thermal annealing (RTA) through N2

gas at 600 °C and 900 °C for 1 min. A blocking oxide of about 8nm was then deposited by PECVD followed by poly-Si deposition and gate patterning to complete the gate stack formation of the HfO2 SONOS-type Flash memory devices.

3.3 Results and Disscussion 3.3.1 Devices Operation

Figure 3.2 and figure 3.3 show the programming and erasing characteristics, respectively, with different pulse widths for the HfO2 SONOS-type Flash memories with different post-HfO2-deposition annealing temperatures. All devices described in this paper had dimensions of L/W = 1/2 μm. We used channel hot-electron injection for the programming with the bias condition at Vg-Vt=7V and Vd=6V and band-to-band hot-hole injection for erasing with the bias condition at Vg-Vt=-6V and Vd=8V [3.13]. Based on the discrete charge storage of HfO2 tapping layer, the feasibility of two-bit operation can be achieved with proper bias scheme. We can employ forward and reverse reads to detect the information stored in the programmed bit1 and bit2, respectively. This means that we can program one bit and read the information using a reverse read scheme. We have added the table 1 to summarize the

bias conditions for two-bit operation. For the temperature effect, it was clearly observed that the programming speed and the memory window increase when the annealing temperature increases. In addition, with the annealing temperature increases, the erasing speed increases but slight overerasure can be observed [3.14]. We speculate this is due to the crystallization-induced trap generation. As well known, the HfO2 trapping layers will crystallize after high temperature annealing. The defects along the grain boundaries are thought being able to act as the extra trapping sites and, therefore, larger memory window can be obtained [3.15]. From the results of X-ray Diffraction (XRD) analysis, we did see that the degree of crystallization becomes more significant upon increasing temperature (Fig. 3.4). Since the Vt are 2.7V, 2.2V, and 1.8V for the as-deposited, 600°C-annealed and 900°C-annealed devices, respectively, we then conclude that the generated crystallization-induced traps inside the HfO2 trapping layer are hole-trap-like, which fact can explain the result shown in Fig. 3.3 that the more severe overerasure upon increasing annealing temperature has been observed. Owing to the nature of discrete charge storage sites in the high-κ gate dielectrics, we can easily achieve 2 bits storage in one single memory device by just reversing source and drain [3.16].

Figure 3.5 illustrates the retention characteristics for all HfO2 SONOS-type Flash memories. The retention time of the memory with as-deposited HfO2 trapping layer can be up to 10⁸ seconds for 10% charge loss. However, it was significantly degraded as the annealing was employed and the situation became worse as the temperature increased. We have calculated the activation energy of the traps in the HfO2

nanocrystals for the fresh device. Activation energy tracing is used widely to characterize the Arrhenius relation extracted from the temperature dependence of charge loss in a nonvolatile memory as a function of time. For a given charge–loss threshold criterion (in our case, 20%), the failure rates obtained at higher temperatures

(125–200 °C), and five numbers for every temperature, can then be extrapolated to the nominal operating condition. The extracted activation energies are 2.45, 1.78, 0.96 eV for the as-deposited, 600°C-annealed and 900°C-annealed samples, respectively [3.17]. Therefore, we thought that the post-deposition annealing will induce more traps with shallower energy level in the trapping layer, which give rise to larger memory window and poor charge retention.

The endurance performances after 10⁶ P/E cycles are shown in figure 3.6. Again, the rate of memory window narrowing increases upon increasing annealing temperature. As we know, the narrowing is mainly coming from charge gain.

Because of the use of ultra-thin tunnel oxide, there is only very minute amount of trapped charges generated during operation in the tunnel oxide [3.18]. Hence, we attribute this to the residual charges along the grain boundaries because these highly localized induced traps are more difficult to remove unless their positions are coincided to overlap with the hot-hole injection. Figure 3.7 shows the vertical charge migration characteristics with applying Vg-Vt=-12V at room temperature 25°C.

Consistent with the former result, the vertical charge migration is exacerbated by increasing annealing temperature. With the annealing temperature increases, the more vertical charge loss was found. It can be explained by more leakage path in the grain boundary of crystallized HfO2 in the high annealing temperature.

3.3.2 Disturbances

Figure 3.8 shows the read disturb induced erase-state threshold voltage instability in a localized HfO2 SONOS-type Flash memory cell for three samples. To allow for two-bit operation, the applied bitline voltage in reverse-read scheme must be sufficiently large (>1.5V) for being able to “read-through” the trapped charge in the

neighboring bit. Relatively large read bitline voltage may cause unwanted electron injection and then result in a significant threshold voltage shift of the neighboring bit.

For our measurement, the gate and drain biases were applied and the source was ground. The results clearly show that almost no read disturbance appear for the low voltage reading operation of Vg -Vt= 3V and Vd = 2.5V in our HfO2 Flash memory.

Figure 3.9 shows the programming drain disturbance of our HfO2 SONOS-type Flash memories. The same drain voltages (Vd = 8V) were applied in the programming drain disturbance measurements at room temperature (T = 25°C). Upon the increasing annealing temperature, the more drain disturbances were observed. The storage charge leakage path along the grain boundaries induce more drain disturbances for the annealed devices. After 1000 seconds at 25°C, we have sufficiently drain disturb margin (< 0.3V) for the three annealed samples.

Figure 3.10 shows the gate disturb characteristics in the erasing state. Gate disturbance may occur during programming for the cells sharing a common wordline while one of the celles is being programmed. We measured the gate disturbance with the condition at Vg-Vt=7V and Vd=Vs=Vsub=0V for the three annealed samples. With the annealing temperature increases, the more gate disturbances were observed. A large amount trap generates in the high temperature annealing that induces more gate disturbances for the annealed devices. Only 0.5V threshold voltage shift has been observed for the 900ºC annealed devices after 1000 seconds stressing. Such good gate disturb characteristic with such thin tunnel oxide can be explained by using serial capacitor voltage divider model with small voltage drop at the tunnel oxide. In summary, we have good read, drain and gate disturbances for the as-deposited, 600°C-annealed and 900°C-annealed samples.

3.3.3 Charge pumping characteristics

The charge pumping (CP) measurement was used to investigate the characteristics of our HfO2 Flash memory. We used a trapezoidal gate pulse having a fixed pulse amplitude with a varying Vgbl. The substrate current (the so-called “charge pumping current,” Icp) as a function of Vgbl was measured. The gate pulse have a frequency of 1 MHz and a 50% duty cycle; the rising and falling times were both 2 ns.

Fig. 2.11 shows plots of the program state charge pumping current Icp versus Vgbl for our HfO2 nanocrystal memory cell. Fowler–Nordheim tunneling was used to program the cell with Vt levels from 2.20 to 3.55 V. The program state Icp curve shifted increasingly toward the right upon increasing the value of Vt as a result of an increase in the amount of injected charge in the HfO2 trapping layer. So, we conclude that HfO2 can behave as an charge trapping centers for our SONOS-type Flash memories.

3.4 Summary

In this chapter, we have investigated the effect of post-deposition annealing temperature on the performance of the resultant HfO2 SONOS-type Flash memories.

Higher temperature treatment can have large memory windows due to the crystallization-induced trap generation whereas lead to poorer retention and endurance performances. Moreover, we found that the HfO2 trapping layer can trap both electrons and holes. No significant read, drain and gate disturbances were observed for three samples. HfO2 SONOS-type Flash memory is considered to be a promising candidate for the Flash memory devices application.

Fig. 3.1 Schematic cross section and process flow of the HfO2 SONOS-type Flash memory device.

Table 3.1 Operation principles and bias conditions utilized during the operation of the HfO2 Flash memory cell.

Programming time (sec)

10

^-7

10

^-6

10

^-5

10

^-4

10

^-3

10

^-2

10

^-1

10

⁰

V

t

shift (V)

0 1 2 3 4 5 6

As-deposited, V_g-V_t=7V, V_d=6V 600^oC, V_g-V_t=7V, V_d=6V

900^oC, V_g-V_t=7V, V_d=6V

Fig. 3.2 Programming characteristics of the HfO2 SONOS-type Flash memories. It was clearly observed that the programming speed and the memory window increase when the annealing temperature increases.

Erasing time (sec)

10

^-6

10

^-5

10

^-4

10

^-3

10

^-2

10

^-1

10

⁰

V

t

shift (V)

-4 -3 -2 -1

0

As-deposited, V_g-V_t=-6V, V_d=8V

600^oC, V_g-V_t=-6V, V_d=8V 900^oC, V_g-V_t=-6V, V_d=8V

Initial V_t

Fig. 3.3 Erasing characteristics of the HfO2 SONOS-type Flash memories. With the annealing temperature increases, the erasing speed increase and shows little overerasure.

Angle (2θ)

30 40 50

900^oC 600^oC

As-deposited m(111)

m(102) m(002)

Fig. 3.4 X-ray Diffraction (XRD) analysis of the HfO2 trapping layer with different temperature.

Retention time (sec)

10

⁰

10

¹

10

²

10

³

10

⁴

10

⁵

10

⁶

10

⁷

10

⁸

10

⁹

V

t

shift (V)

1.5 2.0 2.5 3.0 3.5 4.0 4.5

As-deposited, T=25

^o

C 600

^o

C, T=25

^o

C

900

^o

C, T=25

^o

C

10 years

Fig. 3.5 Retention characteristics of the HfO2 SONOS-type Flash memories at room temperature T=25°C. The 900°C-annealed device shows the worst retention performance.

P/E cycles

10

⁰

10

¹

10

²

10

³

10

⁴

10

⁵

10

⁶

V

t

shift(V)

0 1 2 3 4 5

As-deposited, erase state (V_g-V_t= -6V, V_d=8V, t=10ms) As-deposited, program state (V_g-V_t=7V, V_d=6V, t=100μs) 600^oC, erase state (V_g-V_t=-6V, V_d=8V, t=10ms)

600^oC, program state (V_g-V_t=7V, V_d=6V, t=100μs) 900^oC, erase state (V_g-V_t=-6V, V_d=8V, t=10ms) 900^oC, program state (V_g-V_t=7V, V_d=6V, t=100μs)

Fig. 3.6 Endurance characteristics of the HfO2 SONOS-type Flash memories. The 900° C-annealed device shows larger memory window but worse endurance performance in the same condition.

Time (sec)

10

⁰

10

¹

10

²

10

³

10

⁴

V

t

shift (V)

1.0 1.5 2.0 2.5 3.0 3.5 4.0

As-deposited, V

_g

-V

_t

= -12V 600

^o

C, V

_g

-V

_t

= -12V

900

^o

C, V

_g

-V

_t

= -12V

Fig. 3.7 Vertical migration characteristics of HfO2 SONOS-type Flash memories.

Consistent with the former result, the vertical charge migration is exacerbated by increasing annealing temperature.

Read disturb time (sec)

10

⁰

10

¹

10

²

10

³

V

t

shi ft (V)

-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0

As-deposited, V_g-V_t=3V, V_d=2.5V 600^oC, V_g-V_t=3V, V_d=2.5V

900^oC, V_g-V_t=3V, V_d=2.5V

Fig. 3.8 Read disturbance characteristics of HfO2 SONOS-type Flash memories. No significant Vt shift for all samples even after 1000 seconds at 25°C.

Drain disturb time (sec)

10

⁰

10

¹

10

²

10

³

Program state V

t

shift (V)

-0.4 -0.2 0.0

0.2 As-deposited, V

_d

=8V 600

^o

C, V

_d

=8V

900

^o

C, V

_d

=8V

Fig. 3.9 Drain disturbance characteristics of HfO2 SONOS-type Flash memories. After 1000 seconds at 25°C, only 0.4V drain disturb margin is observed for the 900ºC annealed devices.

Gate disturb time (sec)

10

⁰

10

¹

10

²

10

³

V

t

shi ft (V)

-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2

As-deposited, V_g-V_t=7V, V_d=V_s=V_sub=0V 600^oC, V_g-V_t=7V, V_d=V_s=V_sub=0V

900^oC, V_g-V_t=7V, V_d=V_s=V_sub=0V

Fig. 3.10 Gate disturbance characteristics of HfO2 SONOS-type Flash memories.

Only 0.5V threshold voltage shift has been observed for the 900ºC annealed devices after Vg-Vt=7V and Vs=Vd=Vsub=0V, 1000 seconds stressing.

Vgl (V)

0 1 2 3 4 5 6

Icp (A)

10^-9

10^-8

Erase state=2.20V Vt=2.57V

Vt=2.97V Vt=3.55V

Oxide/HfO

₂

/oxide device

Fig. 3.11 Plots of Icp vs Vgbl for the HfO2 memory cell after F–N programming to different Vt levels.

Chapter 4

Low Temperature Polycrystalline Silicon Thin-Film Flash Memory with High-k Materials

4.1 Introduction

Polycrystalline silicon thin-film transistors (Poly-Si-TFT) have been widely used to integrate driver circuits for the application of AMLCD’s [4.1]. With progressive manufacturing technologies, the complexity of circuit integration will continue to increase. Currently, the feasibility of integrating an entire system on top of the panel (SOP) is being actively pursued [4.2]. Since a system shall include the functionality of memory, efforts shall be paid in order to successfully integrate the memories, such as SRAM, EEPROM, and Flash memory, directly on the panel [4.3-4.6]. SONOS (poly-Si-oxide-nitride-oxide-silicon)-type nonvolatile memory based on discrete storage nodes possesses great potential for achieving large memory windows, high program/erase speed, low programming voltage, low-power performance, excellent retention and good disturb characteristics [4.7].

In this chapter, we used three kinds of high-k dielectrics, including HfO2, Hf-silicate and Zr-silicate for the trapping layer of the poly-Si TFT memory. By employing low thermal cycle (600°C, 24hrs) for post high-κ deposition annealing and S/D activation, the proposed nonvolatile memory fabrication is fully compatible with the current mass-production TFT processing. This makes the realization of producing the embedded nonvolatile memories on the panel becomes feasible.

4.2 Experimental

The schematic diagram of the memory structure is illustrated in Fig. 4.1 First, 500-nm-thick thermal oxide was grown on the Si wafers by furnace system to substitute for the glass substrate and all the experimental devices in this study were fabricated on thermally-oxidized Si wafers. Then, a 100-nm-thick amorphous-silicon layer was deposited on thermally oxidized Si wafer by dissociation of SiH4 gas in a low-pressure chemical vapor deposition (LPCVD) at 550°C. Subsequently, solid phase crystallization (SPC) was performed at 600°C for 24 hours in N2 ambient for the phase transformation. Individual active regions were then patterned and defined.

After a standard RCA cleaning, two kinds of tunneling oxide thickness were deposited, one is 90-nm-thick TEOS oxide, the other is 200-nm-thick TEOS oxide. The followed by the depositions of three different kinds of high-k dielectrics, including HfO2, Hf-silicate and Zr-silicate thin films by co-sputtering method. A blocking oxide of about 33nm was then deposited by PECVD at 350°C. A 200-nm-thick poly-Si was deposited to serve as the gate electrode by LPCVD. Then, gate electrode was patterned and the regions of source, drain, and gate were doped by a self-aligned phosphorous ion implantation at the dosage and energy of 5×10¹⁵ ions/cm^-2 and 40keV, respectively. After S/D formation, which was activated at 600°C for 24-hr, passivation,

After a standard RCA cleaning, two kinds of tunneling oxide thickness were deposited, one is 90-nm-thick TEOS oxide, the other is 200-nm-thick TEOS oxide. The followed by the depositions of three different kinds of high-k dielectrics, including HfO2, Hf-silicate and Zr-silicate thin films by co-sputtering method. A blocking oxide of about 33nm was then deposited by PECVD at 350°C. A 200-nm-thick poly-Si was deposited to serve as the gate electrode by LPCVD. Then, gate electrode was patterned and the regions of source, drain, and gate were doped by a self-aligned phosphorous ion implantation at the dosage and energy of 5×10¹⁵ ions/cm^-2 and 40keV, respectively. After S/D formation, which was activated at 600°C for 24-hr, passivation,

在文檔中 新穎高介電常數材料與奈米微晶粒非揮發性記憶體之研究 (頁 48-0)