Thesis Organization

We will propose a novel, simple, reproducible, and reliable technique for the design of high-density HfO2 nanocrystal Flash memories through the spinodal decomposition of hafnium silicate in chapter 2. Then, in the chapter 3, we have investigated the effect of post-deposition annealing temperature on the performance of the resultant HfO2 SONOS-type Flash memories. In the chapter 4, we have studied three kinds of high-k dielectrics, including HfO2, Hf-silicate and Zr-silicate for the trapping layer of the low temperature poly-Si-TFT memory devices with two different thickness tunnel oxides. In chapter 5, 50nm nano scaled tri-gate HfO2 nanocrystals Flash memories have been fabricated on SOI. In the chapter 6, we have investigated the La2O3 trapping layers for the SONOS-type Flash memories. Conclusions follow in chapter 7.

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Fig. 1.1 (a)Schematic of a basic ETOX Flash memory device. (b) Electron flow (red arrows) during programming by CHE injection. Electron flow (green arrows) or hole flow (orange arrows) during erasing by FN tunneling or BTBTHH injection to the source. [1.2]

Fig. 1.2 Current-voltage characteristic of a memory device in the erased and programmed state, showing the VT shift and the memory window.

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Fig. 1.3 (a) Charges in the dielectric stored in isolated storage nodes. (b) A schematic of a continuous FG structure with all the charges drained by an isolated defect in the dielectric.

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Fig. 1.4 (a) Basic SONOS memory device structure. Red arrows show paths of electron transport during memory operation. The electrons hop between trap. (b) Energy diagram illustrating the physical process of a typical SONOS program operation sites (blue dots) within the Si3N4 layer.

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Fig. 1.5 (a) Vertical migration of the stored charge in the Si3N4 trapping layer in SONOS memory device structure. (b) Lateral migration of the stored charge in the HfO2 trapping layer in SONOS memory device structure.

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Fig. 1.6 (a) An illustration of a nanocrystal Memory. (b) The nanocrystal can store the charge locally due to the well isolation of nanocrystals from each other and effectively prevents formation of good conductive paths between the adjacent nodes

Chapter 2

Characteristics of HfO

Nanocrystal Nonvolatile Flash Memory

2.1 Introduction

SONOS-type (poly-Si-oxide-nitride-oxide-silicon) structure memories, which include nitride and nanocrystal memories, have recently attracted much attention for their application in the next-generation nonvolatile memories [2.1–2.10]. They exhibit many advantages, e. g., easy to fabricate, high program/erase speed, low programming voltage and power consumption, better potential for scalability below the 70-nm node, according to the International Technology Roadmap for Semiconductors (ITRS) [2.11]. Unfortunately, many concerns still remain for this type of memories. For conventional SONOS memory, erase saturation and vertical stored charge migration [2.7-2.8] are two major drawbacks. While, for nanocrystal memories, the most challenging tasks are how to maintain acceptable charge capability of the discrete storage nodes and fabricate nanocrystals with constant size, high density, and uniform distributions [2.9]. In recent years, various ONO processing technology [2.10] and alternative trapping layer material [2.12] have been investigated to improve the cell data retention. For example, the use of an Al2O3 trapping layer and HfAlO3 to replace Si3N4 have been considered since their material bandgaps and high trap densities provide superior program/erase speed and data retention [2.12-2.13]. Moreover, various kinds of nanocrystals, such as silicon (Si), germanium (Ge), and metal nanocrystals, may be used to provide charge storage for nonvolatile memories [2.1-2.6].

In this chapter, we propose a novel technique which is fully compatible with the

current CMOS technologies, in forming very localized HfO2 nanocrystals for application in high-density two-bit nonvolatile Flash memory. This approach utilizes spinodal decomposition of hafnium silicate after RTA treatment at a sufficiently high temperature [2.14-2.15]. Using this technique, we can readily isolate the HfO2

nanocrystals from each other within a SiO2-rich matrix. With a large band gap offset between HfO2 and SiO2, memory cell using HfO2 nanocrystal may exhibit superior characteristics, such as a larger memory window, high program/erase speeds, long retention time, excellent endurance [2.16-2.17], and strong immunity against disturbance. In addition, by comparing to those published ones using Si, Ge, and metal nanocrystals [2.1-2.6], our HfO2 nanocrystal memory possesses many advantages, such as larger memory window and better data retention. Moreover, high temperature process for the S/D activation is no longer detrimental because this step can help further stabilize the HfO2 nanocrystal; while it will oxidize the other nanocrystals and lead to a decrease in memory window. The process is very simple, reproducible, and reliable with less metal contamination concern.

2.2 Experimental

An example of the fabrication process of the HfO2 nanocrystal memory devices is demonstrated by a LOCOS isolation process on a p-type, 5–10 Ω cm, (100) 150-mm silicon substrate (Fig. 2.1). First, a 2nm tunnel oxide was thermally grown at 1000 °C in a vertical furnace system. Next, a 12nm amorphous HfSiOx silicate layer was deposited by co-sputtering with pure silicon (99.9999% pure) and pure hafnium (99.9% pure) targets in an oxygen gas ambient. The co-sputtering process was performed with 7.6 ¯ 10^–3 Torr at room temperature and with precursors of O2 (3 sccm) and Ar (24 sccm); in which both dc sputter powers were set at 150 W. The

samples were then subjected to RTA treatment in an O2 ambient at 900 °C for 1 min to convert the HfSiOx silicate film into the separated HfO2 and SiO2 phases. Their compositions were identified using both energy-dispersive spectroscopy (EDS) and X-ray photoelectron spectroscopy (XPS). A 8nm blocking oxide was then deposited through high-density-plasma chemical vapor deposition (HDPCVD), followed by a N2 densification process at 900 °C for 1 min. Subsequently, poly-Si deposition, gate patterning, source/drain (S/D) implanting, and the remaining standard CMOS procedures were completed to fabricate the HfO2 nanocrystal memory devices.

2.3 Results and Discussion

2.3.1 Material Analysis of HfO

Nanocrystals

Figure 2.2 shows planar-view high-resolution transmission microscopy (HRTEM) image of the HfO2 nanocrystals. The average nanocrystal size was 5–8 nm; the density was as high as 0.9–1.9 ¯ 10¹² cm^–2. Clearly, the nanocrystals were well separated in two dimensions within the SiO2; in which the average distance is >5 nm.

This isolation of the nanocrystals prevents the formation of effective conductive paths between adjacent nodes. The mechanism responsible for the formation of HfO2

nanocrystal is through the phase separation of hafnium silicate into a crystallized structure [2.14]. For the Hf-silicate layer, the compositions within metastable extensions of the spinodal are unstable and HfO2 nanocrystal will be formed and wrapped up by SiO2 after cooling down from RTA processing. In addition, it is clear from the diffraction patterns that the as-deposited film was amorphous and that the sample subjected to RTA was polycrystalline. The HfO2 nanocrystals have monoclinic crystalline structures. Table 2.1 lists the original average concentrations of the individual elements in the as-deposited amorphous HfSiOx silicate layer, as

determined through EDS analysis at a spatial resolution less than 2.0 nm. We observe that the as-deposited HfSiOx layer comprised ca. 40 mol% HfO2 and 60 mol% SiO2; the average elemental concentrations of Hf, Si, and O were 12.61, 18.99, and 68.40%, respectively. At this elemental composition, we can readily reproduce high-density HfO2 nanocrystal dots embodied within a SiO2-rich matrix after RTA in an O2

ambient.

Moreover, we also deposited 2nm and 6nm amorphous HfSiOx silicate layer by the same co-sputtering conditions. The samples were also subjected to RTA treatment in an O2 ambient at 900 °C for 1 min to convert the HfSiOx silicate film into the separated HfO2 and SiO2 phases. Figure 2.3 (a) and 2.3 (b) show the planar-view high-resolution transmission microscopy (HRTEM) image of the HfO2 nanocrystals for the different thickness samples. With the thickness increases, the better HfO2

nanocrystals form, the HfO2 nanocrystal size increases, but the nanocrystal destiny decreases. Table 2.2 shows the comparison table of the different thickness samples of HfSiOx silicate layers after 900°C-RTA-treated.

We have also performed X-ray photoelectron spectroscopy (XPS) measurements using an Al Kα X-ray source (1486.6 eV photons) to determine the bonding environments of the Hf and Si atoms. Fig. 2.4(a) shows the Hf 4f photoemission peaks of the as-deposited Hf-silicate film before and after its PDA at 900 °C under O2. In the as-deposited film we observe well-defined 4f5/2 and 4f7/2 feature peaks that correspond to Hf–O–Si bonding. We confirmed that HfO2 nanocrystals formed after RTA through the observed shifts of these peaks to lower binding energies (4f5/2: ca.

18.9 eV; 4f7/2: ca. 17.4 eV) [2.18-2.19]. Fig. 2.4(b) shows Si 2p XPS spectra of the as-deposited Hf-silicate film before and after RTA. Again, the Si–O bonds in SiO2

network (104 eV) are prominent; their peak intensity increased after PDA. These results provide definite evidence for phase separation occurring in the PDA-treated

Hf-silicate film.

2.3.2 Characteristics of Fresh Devices and 2-bit operation

Figure 2.5 shows the Ids-Vgs curves of the HfO2 nanocrystal memory devices with programming time of 10μs for different programming conditions. Channel hot-electron injection and band-to-band hot-hole injection were employed for programming and erasing, respectively. All cells described in this chapter have dimensions of L/W = 1/2 μm. A relatively large memory window of about 3V can be achieved at the Vg=Vd=10V program operation. Program characteristics as a function of pulse width for different operation conditions are shown in Fig. 2.6(a). Both source and substrate terminals were biased at 0V. The “Vt shift” is defined as the threshold voltage change of a device between the written and the erased states. With Vd=Vg=9V, relatively high speed (10μs) programming performance can be achieved with a memory window of about 2.2V. Meanwhile, Fig. 2.6(b) displays the erase characteristics as a function of various operation voltages. Again, excellent erase speed of around 0.1 ms can be obtained. More important, there is only a very small amount of over-erase observed. The reason is owing to the fact that the vertical electric field decreases with decreasing amount of trapped electrons in the nanocrystals during erasing and the hole injection into the nanocrystals will reduce significantly due to the higher hole tunneling barrier presented in HfO2/SiO2 stack after all programmed charges are removed [2.20].

The retention characteristics of the HfO2 nanocrystal memory devices at both room temperature (T=25°C) and higher temperature (T=125°C) are illustrated in Fig.

2.7. The retention time can be up to 10⁸ seconds for 10% charge loss at room temperature. Only slight charge loss has been seen even at the temperature up to

125°C. We ascribe these results to the combining effects of the tight embrace of HfO2

nanocrystals by SiO2-rich matrix and the sufficiently deep trap energy level [2.20].

Therefore, albeit with a tunnel oxide down to 2nm in thickness, no significant lateral and vertical charge migrations occurred. As a result, superior retention characteristic of the charge storage can be procured. The endurance characteristics after 10⁶ P/E cycles are also shown in Fig. 2.8. The programming and erasing conditions are Vg=Vd=9V for 10μs and Vg=-5V, Vd=10V for 1ms, respectively. No detectable memory window narrowing has been displayed. Moreover, the individual threshold voltage shifts in program and erase states only become visible after 10⁵ cycles. This trend indicates that the amount of operation-induced trapped electrons is very tiny.

Certainly, this is intimately related to the use of ultra-thin tunnel oxide and very minute amount of residual charges in the HfO2 nanocrystals after cycling. Fig. 2.9 demonstrates the feasibility of performing two-bit operation with our HfO2

nanocrystal memories through a reverse read scheme in a single cell. From the Ids–Vgs

curves, it is clear that we could employ forward and reverse reads to detect the information stored in the programmed bit1 and bit2, respectively. The read operation was achieved using a reverse read scheme. Table 2.3 summarizes the bias conditions for two-bit operation.

2.3.3 Migration of storage charges

One of the major advantages that HfO2 nanocrystal Flash memory has over floating gate Flash EEPROM is its better data retention, which is attributed to its excellent capability of locally trapping charges with no significant lateral or vertical migration. We can measure the degrees of migration from the cells after the cycling.

One method for characterizing the lateral extent of the trapped electrons is to monitor

the variation of the threshold voltage (Vt) for a programmed memory cell in the presence of a changing drain current (Vd) [2.19]. Fig. 2.10 shows a plot of the measured Vt versus Vd as a function of the measuring temperature in a programmed cell after 10k P/E cycling. Here, Vt is defined as the applied gate voltage at which the drain current is 1 μA. Since channel hot-electron injection is used for the cell programming, the trapped electrons in the HfO2 nanocrystal trapping layer are more likely to be located near the n⁺ drain junction. These trapped electrons will raise the potential barrier near the drain side and increase the value of Vt. The degree of the Vt

shift is believed to be proportional to the trapped electron density if the drain terminal is maintained at a relatively low potential (e.g., Vd = 0.1 V). When a sufficiently high drain bias (e.g., Vd = 1.5 V) is applied, however, the drain depletion region will be extended toward the channel and, consequently, block the influence from the trapped electrons for the measured Id–Vg characteristics [2.21]. Therefore, this proposed technique can detect the lateral profile of the trapped electrons. To enhance the storage charge movement in the HfO2 nanocrystal trapping layer, the programmed samples were subjected to high-temperature baking at 80 and 125 °C for 2000 s, respectively. Remarkably, the Vt–Vd curves for the cycled device and the baked devices exhibit very little difference, suggesting that lateral migration of the storage charges in the HfO2 nanocrystal trapping layer is rather insignificant. It was attributed to the effective isolation of each nanocrystal within the SiO2 matrix. Next, we investigated the influence of the vertical field on charge retention, i.e., vertical migration. Fig. 2.11 shows the Vt variation over time for various stress conditions for the 10k P/E cycled cells. Visible charge loss was observed when the applied gate voltage and temperature were raised up to -5V and 125°C. We thought even though the trap energy level in the nanocrystal is quite deep, the generated defects and interface traps of the 2nm tunnel oxide after 10k P/E cycled stress will help stored

charges escape via trap-assisted tunneling. Therefore, vertical charge migration is more observable than lateral charge migration in our memory cell. We also calculated the activation energy for the traps of the HfO2 nanocrystals in the new cells (Fig. 2.12).

Activation energy tracing is used widely to characterize the Arrhenius relation extracted from the temperature dependence of charge loss from nonvolatile memory as a function of time. For a given charge loss threshold criterion (in our case, 20% is used), the failure rates obtained at high temperature (125–200 °C) can then be extrapolated to the nominal operating conditions. The model is based on a classical temperature-activated Arrhenius law, expressed in the form tR = t0 × eE^a/kT, where t0

is the retention time corresponding to an infinite temperature, Ea is the activation energy, T is the temperature, and k is the Boltzmann constant [2.22]. The activation energy, determined from the slopes of five samples, lies in the range 2.1–3.3 eV, Obviously, it is higher than those values previously reported for conventional SONOS memories [2.23-2.25].

2.3.4 Disturbance

Figure 2.13 demonstrates the read disturbance induced erase-state threshold voltage instability in a localized HfO2 nanocrystal trapping storage Flash memory cell under several operation conditions. For two-bit operation, the applied bitline voltage in a reverse-read scheme must be sufficiently large (>1.5 V) to be able to “read through” the trapped charge in the neighboring bit. The read-disturb effect is the result of two factors: the word-line and the bit-line. The word-line voltage during read may enhance room temperature (RT) drift in the neighboring bit [2.26]. On the other hand, a relatively large read bit-line voltage may cause unwanted channel hot-electron injection and, subsequently, result in a significant threshold voltage shift of the

neighboring bit. In our measurements, the gate and drain biases were applied and the source was grounded. The results demonstrate clearly that almost no read disturbance occurred in our HfO2 nanocrystal Flash memory under low-voltage reading (Vg = 3 V;

Vd = 2.5 V). For a larger memory window, we found that only a small read disturbance (ca. 0.3 V) can be observed after operation at Vd = 4 V after 1000 s at 25

°C.

Figure 2.14 shows the programming drain disturbance of our HfO2 nanocrystal Flash memory. Two different drain voltages (Vd = 5 and 9 V) were applied in the programming drain disturbance measurements at two different temperatures (T = 25 and 125 °C). We observed that a sufficient programming drain disturb margin exists (ΔVt < 0.4 V), even after programming at a value of Vd of 9V under high temperature (T = 125 °C) and after stressing for 1000 s. Fig. 2.15 shows the gate disturbance characteristics in the erasing state. Gate disturbance may occur during programming for the cells sharing a common word-line while one of the cells is being programmed. We observed a threshold voltage shift of only 0.16 V, i.e., negligible disturbance, under the following conditions: Vg = 9 V; Vs = Vd = Vsub = 0 V; stressed for 1000 s. It in interested to know why this memory can exhibit such excellent gate disturb characteristics with such a thin tunnel oxide; a non-negligible current will be present in the tunnel oxide when a voltage of 9 V is applied to the gate electrode. Using a serial capacitor voltage divider model, we estimated that the voltage drop at the tunnel oxide would be 0.98 V if the trapping layer is assumed to be a HfO2 film, rather than nanocrystal. Even though a 0.98V drop will cause a significant leakage current through an individual 2nm oxide layer, the data retention in the memory cell is related not only to the direct tunneling leakage current induced by such a voltage but also to the total tunneling situation in the whole gate stack; i.e., the effect that the potential barrier presented by the high-k material has on the tunneling current must be taken

into account. In other words, it is incorrect to state that a large direct tunneling current will definitely exist in the interfacial layer and, in turn, that it will induce significant disturbance during programming.

2.3.5 Charge pumping characteristics

The charge pumping (CP) measurement was used to investigate the characteristics of our HfO2 nanocrystal Flash memory. We used a trapezoidal gate pulse having a fixed pulse amplitude with a varying Vgbl. The substrate current (the so-called “charge pumping current,” Icp) as a function of Vgbl was measured. The gate pulse have a frequency of 1 MHz and a 50% duty cycle; the rising and falling times were both 2 ns. Fig. 2.16 shows plots of the program state charge pumping current Icp

versus Vgbl for our HfO2 nanocrystal memory cell. Fowler–Nordheim tunneling was used to program the cell with Vt levels from 2.06 to 3.51 V. The open symbols represent the measured data. The program state Icp curve shifted increasingly toward the right upon increasing the value of Vt as a result of an increase in the amount of injected charge in the HfO2 nanocrystal trapping layer. Interestingly, a hump appeared in the left-hand edge of the curve in compliance with this shift. We decompose the resultant Icp curve mathematically into two individual curves, A and B, in a fresh memory cell. We speculate that these two Icp curves arise from interlacing of the SiO2

matrix and HfO2 nanocrystals within the trapping layer. In other words, the memory is composed of two kinds of devices that have different gate dielectric configurations.

The extracted threshold voltage in curve A is larger than that in curve B, even for a fresh memory; because the value of EOT of the gate stack in the region containing SiO2 matrix is larger than that in the part containing the HfO2 nanocrystals. We believe that curve A is related to the SiO2 matrix and curve B corresponds to the HfO2

nanocrystals. With programming, it is clear that the Icp curve arising from the region containing the SiO2 matrix undergoes almost no shift and the resultant distortion appearing in the measured Icp curve is caused mainly by the charging of the HfO2

nanocrystal. This result implies that the programming charge was stored almost

nanocrystal. This result implies that the programming charge was stored almost