Further Recommendations - Conclusions and Further Recommendations

Chapter 7 Conclusions and Further Recommendations

7.2 Further Recommendations

There are some interesting topics for further study. First, for the nanocrystal, we can use other high-k materials such ZrO2 nanocrystal. Moreover, we can change the SiO2 base to the Al2O3 base. Second, we can change other high-k dielectric trapping layer such as Pr2O3 and CeO2. Third, high-k PMOS Flash memory can realize. Final, we can use High-k dielectric tunnel oxide to obtain high speed operation.

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Chapter 2

[2.1] Ryuji Ohba, Naoharu Sugiyama, Ken Uchida, Junji Koga, and Akira Toriumi,

“Nonvolatile Si quantum memory with self-aligned doubly-stacked dots,” IEEE Trans.

Electron Devices, vol. 49, pp. 1392-1398, Aug. 2002.

[2.2] R. Muralidhar, R.F. Steimle, M. Sadd, R. Rao, C.T. Swift, E.J. Prinz, J. Yater, L.

Grieve, K. Harber, B. Hradsky, S. Straub, B. Acred, W. Paulson, W. Chen, L. Parker, S.G.H. Anderson, M. Rossow, T. Merchant, M. Paransky, T. Huynh, D. Hadad, Ko-Min Chang, and B.E. White Jr., “A 6V Embedded 90nm Silicon Nanocrystal Nonvolatile Memory,” in IEDM Tech. Dig., 2003, pp. 601-605.

[2.3] T. Baron, B. Pellissier, L. Perniola, F. Mazen, J. M. Hartmann and G. Polland,

“Chemical vapor deposition of Ge nanocrystals on SiO2,” Appl. Phys. Lett., vol. 83, pp. 1444-1446, 2003.

[2.4] Q. Wan, C. L. Lin, W. L. Liu, and T. H. Wang, “Structural and electrical characteristics of Ge nanoclusters embedded in Al2O3 gate dielectric,” Appl. Phys.

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[2.5] Chungho Lee, Anirudh Gorur-Seetharam, and Edwin C. Kan, “Operational and

reliability comparison of discrete-storage nonvolatile memories: Advantages of single- and double-layer metal nanocrystals,” in IEDM Tech. Dig., 2003, pp. 557-561.

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[2.7] Peiqi Xuan, Min She, Bruce Harteneck, Alex Liddle, Jeffrey Bokor, and Tsu-Jae King, “FinFET SONOS Flash memory for embedded applications,” in IEDM Tech.

Dig., 2003, pp. 609-613.

[2.8] T. Sugizaki, M. Kobayashi, M. Ishidao, H. Minakata, M. Yamaguchi, Y. Tamura, Y. Sugiyama, T. Nakanishi, and H. Tanaka, “Novel multi-bit SONOS type flash memory using a high-k charge trapping layer,” in Proc. VLSI Symp. Technology Dig.

Technical Papers, 2003, pp. 27-28.

[2.9] M. L. Ostraat, J. W. De Blauwe, M. L. Green, L. D. Bell, M. L. Brongersma, J.

Casperson, R. C. Flagan, and H. A. Atwater, “Synthesis and characterization of aerosol silicon nanocrystal nonvolatile floating-gate memory devices,” Appl. Phys.

Lett., vol. 79, pp. 433-435, 2001.

[2.10] T. S. Chen, K. H. Wu, H. Chung, and C. H. Kao, “Performance improvement of SONOS memory by bandgap engineer of charge-trapping layer,” IEEE Electron Device Lett., vol. 25, no. 4, pp. 205-207, Apr. 2002.

[2.11] “Test and test equipment” in The International Technology Roadmap for Semiconductors (ITRS), 2001, pp. 27-28.

[2.12] T. Sugizaki, M. Kobayashi, H. Minakata, M. Yamaguchi, Y. Tamura, Y.

Sugiyama, H. Tanaka, T. Nakanishi, and Y. Nara, “New 2-bit/Tr MONOS type flash memory using Al2O3 as charge trapping layer,” in Proc. IEEE Non-Volatile Semiconductor Memory Workshop, Feb. 2003, pp. 60-61.

[2.13] Y. N. Tan, W. K. Chim, W. K. Choi, M. S. Joo, T. H. Ng, and B. J. Cho,

“High-K HfAlO charge trapping layer in SONOS-type nonvolatile memory device for high speed operation,” in IEDM Tech. Dig., 2004, pp. 889-892.

[2.14] Susanne Stemmer, Zhiqiang Chen, Carlos G. Levi, Patrick S. Lysaght, Brendan Foran, John A. Gisby, and Jeff R. Taylor, “Application of metastable phase diagrams to silicate thin films for alternative gate dielectrics,” Jpn. J. Appl. Phys., vol. 42, pp.

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[2.15] Shin-ichi Saito, Yuichi Matsui, Kazuyoshi Torii, Yasuhiro Shimamoto, Masahiko Hiratani, and Shin’ichiro Kimura, “Inversion electron mobility affected by phase separation in high-permittivity gate dielectrics,” Jpn. J. Appl. Phys., vol. 42, pp.

L1425-L1428, 2003.

[2.16] Y. H. Lin, C. H. Chien, C. T. Lin, C. Y. Chang, and T. F. Lei, “High Performance Nonvolatile HfO2 Nanocrystal Memory,” IEEE Electron Device Lett., vol. 26, no. 3, pp. 154-156, Mar. 2005.

[2.17] Yu-Hsien Lin, Chao-Hsin Chien, Ching-Tzung Lin, Ching-Wei Chen, Chun-Yen Chang, and Tan-Fu Lei, “High Performance Multi-bit Nonvolatile HfO2

Nanocrystal Memory Using Spinodal Phase Separation of Hafnium Silicate,” IEDM Technical Digest, pp. 1080-1802, Dec. 2004.

[2.18] G. D. Wilk, R. M. Wallace, and J. M. Anthony, “Hafnium and zirconium silicates for advanced gate dielectrics,” J. Appl. Phys., vol. 87, no 1, pp. 484-492, Jan.

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[2.20] W.J. Zhu, Tso-Ping Ma, Takashi Tamagawa, J. Kim, and Y. Di, “Current Transport in Metal/Hafnium Oxide /Silicon Structure”, IEEE Electron Device Lett., vol. 23, no. 2, pp. 97-99, Feb. 2002.

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[2.22] Barbara De Salvo, Gerard Ghibaudo, Georges Pananakakis, Gilles Reimbold, Francois Mondond, Bernard Guillaumot, and Philippe Candelier, “Experimental and theoretical investigation of nonvolatile memory data-retention,” IEEE Trans. Electron Devices, vol. 46, no. 7, pp. 1518-1524, Jul., 1999.

[2.23] Boaz Eitan, Paolo Pavan, Ilan Bloom, Efraim Aloni, Aviv Frommer, and David Finzi, “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Lett., vol. 21, no. 11, pp. 543-545, Nov. 2000.

[2.24] H. Kameyama, Y. Okuyama, S. Kamohara, K. Kubota, H. Kume, K. Okuyama, Y. Manabe, A. Nozoe, H. Uchida, M. Hidaka, and K. Ogura, “A New Data Retention Mechanism after Endurance Stress on Flash Memory,” in Reliability Physics Symposium Proceedings, 2000, pp. 194-199.

[2.25] Wook H. Lee, Dong-Kyu Lee, Young-Min Park, Keon-Soo Kim, Kun-Ok Ahn, and Kang-Deog Suh, “A New Data Retention Mechanism after Endurance Stress on Flash Memory,” in Reliability Physics Symposium Proceedings, 2001, pp. 57-60.

[2.26] W. J. Tsai, C. C. Yeh, N. K. Zous, C. C. Liu, S. K. Cho, T. Wang, S. C. Pan, and C. Y. Lu, “Positive oxide charge-enhanced read disturb in a localized trapping storage flash memory cell,” IEEE Trans. Electron Devices, vol. 51, no. 3, pp. 434-439, Mar.

2004.

[2.27] Y. H. Shih, H. T. Lue, K. Y. Hsieh, R. Liu, and C. Y. Lu, “A novel 2-bit/cell nitride storage flash memory with greater than 1M P/E-cycle endurance,” in IEDM Tech. Dig., 2004, pp. 881-884.

Chapter 3

[3.1] Marvin H. White, Dennis A. Adams, and Jiankang Bu, “On the Go with SONOS”, IEEE Circuits and Devices Magazine, vol. 16, pp. 22-31, Jul. 2000.

[3.2] T. S. Chen, K. H. Wu, H. Chung, and C. H. Kao, “Performance improvement of SONOS memory by bandgap engineer of charge-trapping layer”, IEEE Electron Device Lett., vol. 25, no. 4, pp. 205-207, Apr. 2002.

[3.3] T. Sugizaki, M. Kobayashi, H. Minakata, M. Yamaguchi, Y. Tamura, Y.

[3.4] T. Baron, B. Pellissier, L. Perniola, F. Mazen, J. M. Hartmann and G.

Polland,“ Chemical vapor deposition of Ge nanocrystals on SiO2,” Appl. Phys. Lett., vol. 83, pp. 1444 – 1446, 2003.

[3.5] Ryuji Ohba, Naoharu Sugiyama, Ken Uchida, Junji Koga, and Akira Toriumi,

“Nonvolatile Si quantum memory with self-aligned doubly-stacked dots,” IEEE Trans.

Electron Devices, vol. 49, pp. 1392-1398, Aug. 2002.

[3.6] R. Muralidhar, R.F. Steimle, M. Sadd, R. Rao, C.T. Swift, E.J. Prinz, J. Yater, L.

[3.7] Y. N. Tan, W. K. Chim, W. K. Choi, M. S. Joo, T. H. Ng, and B. J. Cho,

“ High-κ HfAlO charge trapping layer in SONOS-type nonvolatile memory device for high speed operation,” in IEDM Tech. Dig., 2004, pp. 889-892.

[3.8] W.J. Zhu, Tso-Ping Ma, Takashi Tamagawa, J. Kim, and Y. Di, “Current

Transport in Metal/Hafnium Oxide /Silicon Structure”, IEEE Electron Device Lett., vol. 23, no. 2, pp. 97-99, Feb. 2002.

[3.9] G. D. Wilk, R. M Wallace, J. M. Anthony, “High-κ gate dielectrics: Current status and materials properties considerations”, Applied Physics Review, vol. 89, no.

10, pp. 5243-5275, Nay 2001.

[3.10] Yu-Hsien Lin, Chao-Hsin Chien, Ching-Tzung Lin, Chun-Yen Chang, and Tan-Fu Lei, “High Performance Nonvolatile HfO2 Nanocrystal Memory”, IEEE Electron Device Lett., vol. 26, no. 3, pp. 154-156, Mar. 2005.

[3.11] D. Montanari, J. Van Houdt, D. Wellekens, G. Vanhorebeek, L. Haspeslagh, L.

Deferm, G. Groeseneken, H. E. Maes, “Multi-level charge storage in source-side injection flash EEPROM”, in IEEE Nonvolatile Memory Technology Conference, pp.80-83, Jun. 1996.

[3.12] T. Sugizaki, M. Kobayashi, M. Ishidao, H. Minakata, M. Yamaguchi, Y.

Tamura, Y. Sugiyama, T. Nakanishi, and H. Tanaka, “Novel multi-bit SONOS type flash memory using a high-κ charge trapping layer,” in Proc. VLSI Symp. Technology Dig. Technical Papers, 2003, pp. 27 - 28.

[3.13] W. J. Tsai, C. C. Yeh, N. K. Zous, C. C. Liu, S. K. Cho, T. Wang, S. C. Pan and C. Y. Lu, “Positive oxide charge-enhanced read disturb in a localized trapping storage flash memory cell”, IEEE Trans. Electron Devices, vol. 51, no. 3, pp. 434-439, Mar.

2004.

[3.14] Chih-Chieh Yeh, Tahui Wang, Wen-Jer Tsai, Tao-Cheng Lu, Yi-Ying Liao, Hung-Yueh Chen, Nian-Kai Zous, Wenchi Ting, Ku, J., Chih-Yuan Lu, “A novel erase scheme to suppress overerasure in a scaled 2-bit nitride storage flash memory cell”

Electron Device Letters, IEEE Electron Device Lett., vol. 25, pp. 643-645, Sep. 2004.

[3.15] T. Yamaguchi, H. Satake, N. Fukushima, “Degradation of current drivability by the increase of Zr concentrations in Zr-silicate MISFET”, in IEDM Tech. Dig., pp.

663-6666, 2001.

[3.16] Yao-Wen Chang; Tao-Cheng Lu; Sam Pan; Chih-Yuan Lu, “Modeling for the 2nd-bit effect of a nitride-based trapping storage flash EEPROM cell under two-bit operation”, IEEE Electron Device Lett., vol. 25, pp. 95-97, Feb. 2004.

[3.17] Barbara De Salvo, Gerard Ghibaudo, Georges Pananakakis, Gilles Reimbold, Francois Mondond, Bernard Guillaumot, and Philippe Candelier, “Experimental and theoretical investigation of nonvolatile memory data-retention”, IEEE Trans. Electron Devices, vol. 46, no. 7, pp. 1518-1524, Jul., 1999.

[3.18] E. F. Runnion, S. M. Gladstone, R. S. Scott, Jr., D. J. Dumin, L. Lie, and J. C.

Mitros, “Thickness dependence of stress-induced leakage currents in silicon oxide”, IEEE Trans. Electron Devices, vol. 44, pp.993-1001, Jun. 1997.

Chapter 4

[4.1] H. Oshima and S. Morozumi, “Future trends for TFT integrated circuits on glass substrates”, IEDM Technical Digest, pp. 157, 1989.

[4.2] T. Serikawa, S. Shirai, A. Okamoto, and S. Suyama, “Low-temperature fabrication of high-mobility poly-Si TFT’s for large-area LCD’s”, IEEE Trans.

Electron Devices, vol. 36, pp. 1929-1933, Sep. 1989.

[4.3] Jung-Hoon Oh, Hoon-Ju Chung, Nae-In Lee, and Chul-Hi Han, “A High-Endurence Low-Temperature Polysilicon Thin-Film Transistor EEPROM Cell”, IEEE Electron Device Lett., vol. 21, no. 6, pp. 304-306, June. 2000.

[4.4] Mino Cao, Tiemin Zhao, Krishna C. Saraswat, James D. Plummer, ”A Simple EEPROM Cell Using Twin Polysilicon Thin Film Transistors”, IEEE Electron Device Lett., vol. 15, no. 8, pp. 304-306, Aug. 1994.

[4.5] Nae-In Lee, Jin-Woo Lee, Hyoung-Sub Kim, and Chul-Hi Han,

“High-Performance EEPROM’s Using N- and P-Channel Polysilicon Thin-Film Transistors with Electron Cyclotron Resonance N2O-Plasma Oxide”, IEEE Electron Device Lett., vol. 20, no. 1, pp. 15-17, Jan. 1999.

[4.6] Andrew J. Walker, Sucheta Nallamothu, En-Hsing Chen, Maitreyee Mahajani, S.

Brad Herner, Mark Clack, James M. Cleeves, S. Vance Dunton, Victoria L. Eckert, James Gu, Susan Hu, Johan Knall, Michael Konevecki, Christopher Petti, Steven Radigan, Usha Raghuram, Joetta Vienna, Michael A. Vyvoda, “3D TFT-SONOS Memory Cell for Ultra-High Density File Storage Applications”, in Proc. VLSI Symp.

Technology Dig. Technical Papers, pp. 29-30, 2003.

[4.7] Y. N. Tan, W. K. Chim, W. K. Choi, M. S. Joo, T. H. Ng, and B. J. Cho,

“High-K HfAlO charge trapping layer in SONOS-type nonvolatile memory device for high speed operation,” in IEDM Tech. Dig., 2004, pp. 889-892.

[4.8] W.J. Zhu, Tso-Ping Ma, Takashi Tamagawa, J. Kim, and Y. Di, “Current Transport in Metal/Hafnium Oxide /Silicon Structure”, IEEE Electron Device Lett., vol. 23, no. 2, pp. 97-99, Feb. 2002.

[4.9] Yu-Hsien Lin, Chao-Hsin Chien, Ching-Tzung Lin, Ching-Wei Chen, Chun-Yen Changand Tan-Fu Lei, “High Performance Multi-bit Nonvolatile HfO2 Nanocrystal Memory Using Spinodal Phase Separation of Hafnium Silicate”, IEDM Technical Digest, pp. 1080-1802, 2004.

[4.10] Barbara De Salvo, Gerard Ghibaudo, Georges Pananakakis, Gilles Reimbold, Francois Mondond, Bernard Guillaumot, and Philippe Candelier, “Experimental and theoretical investigation of nonvolatile memory data-retention,” IEEE Trans. Electron Devices, vol. 46, no. 7, pp. 1518-1524, Jul., 1999.

[4.11] Boaz Eitan, Paolo Pavan, Ilan Bloom, Efraim Aloni, Aviv Frommer, and David Finzi, “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Lett., vol. 21, no. 11, pp. 543-545, Nov. 2000.

[4.12] H. Kameyama, Y. Okuyama, S. Kamohara, K. Kubota, H. Kume, K. Okuyama, Y. Manabe, A. Nozoe, H. Uchida, M. Hidaka, and K. Ogura, “A New Data Retention Mechanism after Endurance Stress on Flash Memory,” in Reliability Physics Symposium Proceedings, 2000, pp. 194-199.

[4.13] Wook H. Lee, Dong-Kyu Lee, Young-Min Park, Keon-Soo Kim, Kun-Ok Ahn, and Kang-Deog Suh, “A New Data Retention Mechanism after Endurance Stress on Flash Memory,” in Reliability Physics Symposium Proceedings, 2001, pp. 57-60.

[4.14] G. A. Armstrong, S. Uppal, S. D. Brotherton and J.R. Ayres, “Differentiation of Effects due to Grain and Grain Boundary Traps in Laser Annealed Poly-Si Thin Film Transistors”, Jpn. J Appl Phys., vol. 37, pp. 1721-1726, Apr. 1998.

[4.15] Michael Hack, Alan G. Lewis and I-Wei Wu, “ Physical Models for Degradation Effects in Polysilicon Thin-Film Transistors”, IEEE Trans. Electron Devices, vol. 40, pp. 890-897, May, 1993.

[4.16] I. W. Wu, W. B. Jackson, T. Y. Huang, A. G. Lewis, and A. Chiang, “Passivation kinetics of two types of defects in polysilicon TFT by plasma hydrogenation,” IEEE Electron Devices lett., vol. 12, pp. 181-183, May 1991.

[4.17] G. K. Giust and T. W. Sigmon, “High-performance thin-film transistors fabricated using excimer laser processing and grain engineering,” IEEE Trans.

Electron Devices, vol. 45, pp. 925-932, Apr. 1998.

[4.18] C. F. Yeh, T. J. Chen, C. Liu, J. T. Gudmundsson and M. A. Lieberman,

“Hydrogenation of polysilicon thin-film transistor in a planar inductive H2/Ar discharge,” IEEE Electron Device Lett., vol. 20, pp. 223-225, 1999.

[4.19] H. C. Cheng, F. S. Wang, and C. Y. Huang, “Effects of NH3 plasma passivation on N-channel polycrystalline silicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 44, pp. 64-68, 1997.

[4.20] J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M.

Rider, “Conductivity behavior in polycrystalline semiconductor thin film transistors,”

J. Appl. Phys., vol. 53, pp. 1193-1202, Feb. 1982.

[4.21] R. E. Proano, R. S. Misage, and D. G. Ast, “Development and electrical properties of undoped polycrystalline silicon thin-film transistors,” IEEE Trans.

Electron Devices, vol. 36, pp. 1915-1922, Sep. 1989.

[4.22] C. A. Dimitriadis, P. A. Coxon, L. Dozsa, L. Papadimitriou, and N. Economou,

“Performance of thin-film transistors on polysilicon films grown by low-pressure chemical vapor deposition at various pressures,” IEEE Trans. Electron Devices, vol.

39, pp. 598-606, Mar. 1992.

[4.23] G. A. Armstrong, S. Uppal, S. D. Brotherton and J.R. Ayres, “Differentiation of Effects due to Grain and Grain Boundary Traps in Laser Annealed Poly-Si Thin Film Transistors”, Jpn. J Appl Phys., vol. 37, pp. 1721-1726, Apr. 1998.

[4.24] Michael Hack, Alan G. Lewis and I-Wei Wu, “ Physical Models for Degradation Effects in Polysilicon Thin-Film Transistors”, IEEE Trans. Electron Devices, vol. 40, pp. 890-897, May, 1993.

[4.25] T. F. Chen, C. F. Yeh and J. C. Lou, “Effects of grain boundaries on performance and hot-carrier reliability of excimer-laser annealed polycrystalline silicon thin film transistors,” J. Appl. Phys., vol. 95, pp.5788-5794, May 2004.

[4.26] Yu-Hsien Lin, Chao-Hsin Chien, Ching-Tzung Lin, Chun-Yen Chang, and Tan-Fu Lei, “Novel Two-Bit HfO2 Nanocrystal Nonvolatile Flash Memory”, IEEE Trans. Electron Devices, vol. 49, pp. 782 – 789, Apr. 2006

Chapter 5

[5.1] “Test and test equipment” in The International Technology Roadmap for

Semiconductors (ITRS), 2001, pp. 27-28.

[5.2] Ryuji Ohba, Naoharu Sugiyama, Ken Uchida, Junji Koga, and Akira Toriumi,

“Nonvolatile Si quantum memory with self-aligned doubly-stacked dots,” IEEE Trans.

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[5.3] R. Muralidhar, R.F. Steimle, M. Sadd, R. Rao, C.T. Swift, E.J. Prinz, J. Yater, L.

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在文檔中新穎高介電常數材料與奈米微晶粒非揮發性記憶體之研究 (頁 168-191)