Channel dangling bonds

With investigating the long-term stability, we found that poly-Si-TFT’s reliability characteristics, such as retention, drain and gate disturbance, are intimately related to the density of traps along the grain boundaries of the poly-Si films [4.16], [4.17].

Even though the charge retention capability could be significantly improved by reducing trap density with employing NH3 plasma treatment [4.18], [4.19], the hydrogenated poly-Si-TFTs still depicted significant and rather unique threshold voltage deviation resulting from drain and gate disturbance. These specific drain and gate disturbance are believed to arise from the breaking of the weak Si-H bonds induced by the acting stresses and the filling of the un-passivated traps by the produced electrons. For comparison of our experiments, NH3 plasma sintering was performed to complete the fabrication of the poly-Si-TFT memories, but some of comparison samples were not subjected to plasma treatment.

Figure 4.15 shows the retention behaviors of the poly-Si-TFT Flash memories with and without NH3 plasma treatment. We could clearly see the memory device with NH3 plasma treatment depicted a better room temperature retention performance than that without NH3 plasma treatment. This result implies that the hydrogenation by NH3 plasma treatment is closely related to the charge storage capability of the poy-Si-TFT Flash memories. The retention characteristic of a 10k P/E cycled hydrogenated memory device is also shown for comparison. The charge loss no doubt became worse and started only after few tenths of second due to the induced defects after cycling. This behavior feature was obviously different from that in the case without NH3 treatment.

In order to clarify the mechanism responsible for this phenomenon, trap state densities (QT) of the samples were extracted. Fig. 4.16 exhibits the plots of the ln[ID/(VGS-VFB)] versus 1/(VGS-VFB)² curves at low VDS and high VGS. The QT values for the poly-Si-TFTs were estimated by Levison and Proano method [4.20], [4.21]

from the slopes of these curves. The hydrogenated poly-Si-TFT exhibits a QT value of 1.51×10¹² cm^-2, whereas the non-hydrogenated poly-Si-TFT has the value of 1.74×10¹² cm^-2. To further study the hydrogenated passivation effect near the interface, the effective interface trap states densities (NT) near the SiO2/poly-Si interface were also calculated. From the subthreshold swing (S.S.), by neglecting the depletion capacitance, NT can be expressed as[4.22]:

NT = [(S.S./ln10)(q/kT)-1)](Cox/q),

where the Cox is the capacitance of the gate oxide. The NT values of the non-hydrogenated and hydrogenated poly-Si-TFTs are 1.82×10¹² cm^-2 and 1.63×10¹² cm^-2, respectively. After 10k P/E cycling, the extracted QT value is 2.42×10¹² cm^-2 and the NT value is 2.68×10¹² cm^-2. In Fig. 1, the evolution of QT value as a function of time for the sample without NH3 treatment is also plotted. We found the tendency traced well with the charge loss behavior. In contrast, the QT value remains unchanged for the P/E cycled hydrogenated memory device (not shown). These results explain why two different charge loss trends were observed between the non-hydrogenated and the cycled hydrogenated one. In other words, we believe that the surprisingly steep charge loss in the case without NH3 treatment is caused by the defects at the grain boundaries; while the smooth and early retention degradation of the 10k P/E cycled memory device arises from the combining effects of the generated traps in the bulk of the tunnel oxide and those traps produced near the interface during cycling.

Disturbance is a very important reliability concern for the Flash memories. It

often takes place during programming a specific cell in the NOR Flash memory, which operation leads to the unwanted electrical stress acting on those neighboring cells connected to the same bitline, i.e, drain disturbance, and to the same wordline, i.e., gate disturbance. Fig. 4.17 shows the drain disturb characteristics of the poly-Si-TFT Flash memories in the programmed state. Two different drain voltages were applied, i.e., Vd = 10V and 12V, with the other terminals grounded. For the hydrogenated samples, we observed that a drain disturb (ΔVt~0.7 V) existed for the cycled memory device under a drain disturb of 12V for 1000 seconds. However, for the non-hydrogenated device the degradation was quite severe. This result is believed due to the presence of the localized traps along the grain boundaries in the channel, which can significantly affect the Vt shift through drain bias stressing [4.23-4.24].

Here, we can confirm our former speculation−the generated traps after cycling locate mostly near the Si/SiO2 interface rather than at the grain boundaries deep inside the channel [4.25]−since the cycled hydrogenated device depicts higher QT value but less significant disturbance. Fig. 4.18 shows the gate disturb characteristics of both fresh hydrogenated and non-hydrogenated memory devices in the erased state with two different tunnel oxide thicknesses (t = 9nm and 20nm). The applied gate voltage was 12V with other terminals grounded. Even though the non-hydrogenated devices again exhibited poorer gate disturb results, the Vt shift decreased rather than increased as the stressing time increased, which is in strong contrast to the situation in the conventional SONOS-type memories [4.26]. Since no cycling had been done for the fresh devices, the decrease in Vt seems unlikely to be caused by the electron detrapping. Thus, we thought this phenomenon is ascribed to the filling of the traps at the grain boundaries by the induced electrons by the applied gate voltage. Moreover, the larger Vt shift in the thinner oxide case is due to the more induced electrons by the higher electric field. These results mean that the defects in the channel not only

significantly influence the data retention but also the drain and gate disturbance of the poly-Si-TFT Flash memories.

4.4 Summary

In this chapter, we have studied three kinds of high-k dielectrics, including HfO2, Hf-silicate and Zr-silicate for the trapping layer of the poly-Si TFT memory devices with two different thickness tunnel oxides. By sticking with sufficiently low thermal-budget processing, we have successfully demonstrated the feasibility of fabricating nonvolatile poly-Si TFT memories with excellent characteristics in terms of large memory windows, good speed program/erase, long retention time and 2-bit operation. Moreover, the poly-Si grain boundary is the concerned issues about the disturbance characteristics. We demonstrated that the reliability characteristics of a poly-Si-TFT memory device in terms of retention, drain and gate disturbance are closely related to the defects along the grain boundaries in the channel. The NH3

plasma treatment is one of the useful methods to improve the SiO2/poly-Si interface and the channel quality because it can effectively eliminate the trap densities in both regions. These poly-Si TFT memories make the realization of producing the embedded nonvolatile memories for system on the panel.

Fig. 4.1 Schematic cross section of the high-κ dielectric poly-Si-TFT nonvolatile memories.

Bit2 Bit1

S D

+

n ⁺ n ⁺

Tunnel oxide

Blocking oxide

Poly

High-k

SiO

₂

Si wafer

Poly

G

Fig. 4.2 Cross-sectional HRTEM images of the gate stacks for the poly-Si-TFT memories with HfO2, Hf silicate and Zr silicate trapping layers. The inset show the diffraction patterns of them.

V _g (V)

0 2 4 6 8 10

I d (A)

10

^-13

10

^-12

10

^-11

10

^-10

10

^-9

10

^-8

10

^-7

10

^-6

10

^-5

10

^-4

(Bit1, Bit2)=(E, E)=(1, 1) (Bit1, Bit2)=(P, E)=(0, 1)

Forward read for (0, 1), V_d=1V (Bit1, Bit2)=(E, P)=(1, 0)

Reverse read for (1, 0), V_s=1V

Fig. 4.3 Demonstration of 2 bits/cell operation. E: erased; P: programmed; Bit1: drain side; Bit2: source side.

Table 4.1 Operation principles and bias conditions utilized during the operation of the poly-Si TFT Flash memory cell.

Time (sec)

10

^-7

10

^-6

10

^-5

10

^-4

10

^-3

10

^-2

10

^-1

10

⁰

V t shift (V)

-6 -4 -2 0 2 4 6

8 HfO

₂

, V

_g

=10V, V

_d

=10V

Hf silicate, V

_g

=10V, V

_d

=10V Zr silicate, V

_g

=10V, V

_d

=10V

HfO

₂

, V

_g

=-8V, V

_d

=8V

Hf silicate, V

_g

=-8V, V

_d

=8V Zr silicate, V

_g

=-8V, V

_d

=8V

Fig. 4.4 Programming and erasing speed characteristics of poly-Si TFT memories with HfO2, Hf silicate and Zr silicate trapping layers for different programming conditions. The programming time can be as short as 1ms if the window margin is set to 3V with Vg=Vd=12V. The erasing time is about 10 ms.

Time (s)

10

⁰

10

¹

10

²

10

³

10

⁴

10

⁵

10

⁶

10

⁷

10

⁸

Normalized V t shift

0.0 0.2 0.4 0.6 0.8 1.0

HfO

₂

Hf silicate Zr silicate

Fig. 4.5 Retention characteristics of the fabricated poly-Si-TFT memories at T=25°C.

The retention time can be up to 10⁶ s for 20% charge loss at room temperature.

P/E cycles

10

⁰

10

¹

10

²

10

³

10

⁴

10

⁵

V

t

(V)

2 4 6 8 10

HfO

₂

Hf silicate Zr silicate

Fig. 4.6 Endurance characteristics of the poly-Si-TFT memories. Despite the occurrence of significant memory window narrowing, a memory window of about 2V is sustained even after 10⁵ P/E cycles.

Program

Erase

Time (sec)

10

^-7

10

^-6

10

^-5

10

^-4

10

^-3

10

^-2

10

^-1

10

⁰

V t shift (V)

-4 -2 0 2

4 P: t=9nm, V

_g

=10V, V

_d

=10V P: t=20nm, V

_g

=10V, V

_d

=10V

E: t=9nm, V

_g

=-10V, V

_d

=10V E: t=20nm, V

_g

=-10V, V

_d

=10V

Fig. 4.7 Programming and erasing speed characteristics of poly-Si TFT memories with HfO2, Hf silicate and Zr silicate trapping layers for different programming conditions. The programming time can be as short as 1ms if the window margin is set to 3V with Vg=Vd=12V. The erasing time is about 10 ms.

Time (s)

10 ⁰ 10 ¹ 10 ² 10 ³ 10 ⁴ 10 ⁵ 10 ⁶ 10 ⁷ 10 ⁸ Normalized V t shift

0.0 0.2 0.4 0.6 0.8 1.0

t=20nm, T=25

^o

C t=20nm, T=85

^o

C t=9nm, T=25

^o

C t=9nm, T=85

^o

C

Fig. 4.8 Retention characteristics of the fabricated poly-Si-TFT memories with two different tunnel oxide thickness samples at T=25°C.

Time (s)

10

^-1

10

⁰

10

¹

10

²

10

³

10

⁴

10

⁵

10

⁶

10

⁷

10

⁸

Normalized V t shift

0.0 0.2 0.4 0.6 0.8 1.0

t=20nm, T=25

^o

C t=20nm, T=85

^o

C t=9nm, T=25

^o

C t=9nm, T=85

^o

C

Fig. 4.9 Retention characteristics of the fabricated poly-Si-TFT memories with two different tunnel oxide thickness samples at T=85°C.

P/E cycles

10

⁰

10

¹

10

²

10

³

10

⁴

10

⁵

V

t

(V)

2 4 6 8 10

t=9nm t=20nm Hf silicate

Fig. 4.10 Endurance characteristics of the poly-Si-TFT memories with two different tunnel oxide thickness samples.

Fig. 4.11 The schematic illustration of disturb condition. Cell A is the programming cell. Cell B and Cell C are the drain disturbance and gate disturbance, respectively.

Drain disturb time (sec)

10

⁰

10

¹

10

²

10

³

V t shift (V)

-1.0 -0.5 0.0 0.5 1.0

fresh, t=20nm, V

_d

=10V fresh, t=20nm, V

_d

=12V fresh, t=9nm, V

_d

=10V fresh, t=9nm, V

_d

=12V

10k P/E cycled, t=20nm, V

_d

=10V 10k P/E cycled, t=20nm, V

_d

=12V

Fig. 4.12 Drain disturbance characteristics of the Hf silicate TFT memory devicess with two different tunnel oxide thickness samples. After 1000 s at 25 °C, small 0.7V drain disturb margin was observed.

Gate disturb time (sec)

10

⁰

10

¹

10

²

10

³

V t shift (V)

-1.0 -0.5 0.0 0.5

1.0 fresh, t=20nm, V

_g

=10V

fresh, t=20nm, V

_g

=12V

10k P/E cycled, t=20nm, V

_g

=10V 10k P/E cycled, t=20nm, V

_g

=12V

fresh, t=9nm, V

_g

=10V fresh, t=9nm, V

_g

=12V

Fig. 4.13 Gate disturbance characteristics of the Hf silicate TFT memory devices with two different tunnel oxide thickness samples.

Read disturb time (sec)

10

⁰

10

¹

10

²

10

³

V t shift(V)

-1.0 -0.5 0.0 0.5 1.0

10k P/E cycled, t=20nm, V

_g

=3V, V

_d

=1V 10k P/E cycled, t=20nm, V

_g

=3V, V

_d

=2V 10k P/E cycled, t=9nm, V

_g

=3V, V

_d

=1V 10k P/E cycled, t=9nm, V

_g

=3V, V

_d

=2V

Fig. 4.14 Read disturbance characteristics of the Hf silicate TFT memory devices with two different tunnel oxide thickness samples. No significant Vt shift occurred for Vd <

1, even after 1000 s at 25 °C.

Time (s)

10

^-1

10

⁰

10

¹

10

²

10

³

10

⁴

10

⁵

10

⁶

10

⁷

10

⁸

Normalized V

t

shift

0.0 0.2 0.4 0.6 0.8 1.0

Normalized Q

t Fresh device, NH₃

Fresh device, w/o NH₃

10k P/E cycled device, NH₃

Normalized Q_t, fresh device, w/o NH₃ Tunnel oxide=20nm

Fig. 4.15. Retention characteristics of the non-hydrogenated, fresh and 10k P/E cycled hydrogenated poly-Si-TFT memories at T=25°C.

1/(V

_GS

-V

_FB

)

²

(V

^-2

)

0.005 0.010 0.015 0.020

ln[I

DS

/(V

GS

-V

FB

)](Ohm

-1

)

-24 -22 -20 -18 -16 -14 -12

NH

₃

sintering, fresh device w/o NH

₃

sintering, fresh device

NH

₃

sintering, 10k P/E cycled device

Fig. 4.16. In[ID/(VGS-VFB)] verus 1/(VGS-VFB)² curves at VDS=0.1V, and high VGS for the three kinds of poly-Si-TFT memories.

Q_t=1.51×10¹²

Qt=1.74×10¹² Q_t=2.42×10¹²

Drain disturb time (sec)

10

⁰

10

¹

10

²

10

³

V t shift (V)

0.0 0.5 1.0 1.5 2.0

2.5 _NH

3

, V

_d

=10V NH

₃

, V

_d

=12V w/o NH

₃

, V

_d

=10V w/o NH

₃

, V

_d

=12V

NH

₃

, 10k P/E cycled, V

_d

=10V NH

₃

, 10k P/E cycled, V

_d

=12V

Tunnel oxide=20nm

Fig. 4.17. Drain disturb characteristics of the non-hydrogenated, fresh and 10k P/E cycled hydrogenated poly-Si-TFT memories.

Gate disturb time (sec)

10

⁰

10

¹

10

²

10

³

V t shift (V)

-1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2

NH

₃

, tunnel oxide=20nm, V

_g

=12V NH

₃

, tunnel oxide=9nm, V

_g

=12V w/o NH

₃

, tunnel oxide=9nm, V

_g

=12V w/o NH

₃

, tunnel oxide=20nm, V

_g

=12V

Fig. 4.18. Gate disturb characteristics of the non-hydrogenated, fresh and 10k P/E cycled hydrogenated poly-Si-TFT memories.

Chapter 5

Nano Scaled Tri-Gate HfO

₂

Nanocrystal Flash Memory on SOI

5.1 Introduction

According to the International Technology Roadmap for Semiconductors (ITRS), there are critical limitations for aggressively scaling the conventional nonvolatile floating gate memories below sub-70nm node [5.1]. Therefore, the SONOS-type (poly-Si-oxide-nitride-oxide-silicon) structure memories including nitride memories and nanocrystal memories have recently attracted much attention for the application in the next-generation nonvolatile memories [5.2-5.11] because of their great potential for achieving high program/erase speed, low programming voltage and low power performance. However, many concerning issues are still presented for both types of memories. For conventional SONOS, erase saturation and vertical stored charge migration [5.8-5.9] are the major drawbacks; while for nanocrystal memories good enough charge keeping capability of the discrete storage nodes and the formation of nanocrystals with constant size, high density and uniform distribution are the extremely challenging issues [5.10]. In recent years, many papers have ever shown Al2O3 trapping layer as the potential candidate for replacing Si3N4 [5.11] and also demonstrated different kinds of nanocrystals to provide charge storage for the non-volatile memories, such as silicon (Si) nanocrystals, germanium (Ge) nanocrystals and metal nanocrystals [5.2-5.7].

In this chapter, we use the very local HfO2 nanocrystals for the application of the nonvolatile Flash memories on the SOI. We have successfully achieved the 50nm

nanocrystal memories with good characteristics in terms of considerably large memory window, high speed program/erase, long retention time, and good endurance.

5.2 Experimental

The ultrashort HfO2 nanocrystal Flash memory was fabricated by the following process steps for the structure on figure 5.1. After active region was patterned, a 2nm tunnel oxide was thermally grown at 1000 °C in a vertical furnace system. Next, a 10nm amorphous HfSiOx silicate layer was deposited by co-sputtering with pure silicon (99.9999% pure) and pure hafnium (99.9% pure) targets in an oxygen gas ambient. The co-sputtering process was performed with 7.6 ¯ 10^–3 Torr at room temperature and with precursors of O2 (3 sccm) and Ar (24 sccm); in which both dc sputter powers were set at 150 W. A 8nm blocking oxide was then deposited through high-density-plasma chemical vapor deposition (HDPCVD). Next, a 100-nm in-situ n⁺ phosphorus deoped a-Si gate layer was deposited by LPCVD. After gate patterning, the remaining oxide on source/drain regions was removed by diluted HF and then a 150-nm TEOS oxide sidewall spacer was formed by deposition and etching. A self-aligned implantation was used to perform the n⁺ source/drain extension with As⁺ to dose 1 × 10¹⁵ cm^-2 and energy 20 keV, tilt 20^o. Then, a self-aligned implantation was used to perform the n⁺ source/drain with As⁺ to dose 5 × 10¹⁵ cm^-2 and energy 15 keV, tilt 7^o. Dopants were activated by RTA at 950°C for 15s and the HfSiOx silicate film into the separated HfO2 and SiO2 phases. After contact and metallization have completed the processes.

5.3 Results and Discussion

5.3.1 Material Analysis of HfO

2

Nanocrystal memory

Figure 5.2(a) and Fig. 5.2(b) shows cross-section-view high-resolution transmission microscopy (HRTEM) image of the HfO2 nanocrystals device. Clearly, the gate length is about 55nm and the nanocrystals were well separated in two dimensions within the SiO2; in which the average distance is >5 nm. This isolation of the nanocrystals prevents the formation of effective conductive paths between adjacent nodes. The mechanism responsible for the formation of HfO2 nanocrystal is through the phase separation of hafnium silicate into a crystallized structure [5.12].

For the Hf-silicate layer, the compositions within metastable extensions of the spinodal are unstable and HfO2 nanocrystal will be formed and wrapped up by SiO2

after cooling down from RTA processing. In addition, it is clear from the diffraction patterns that the as-deposited film was amorphous and that the sample subjected to RTA was polycrystalline. The HfO2 nanocrystals have monoclinic crystalline structures.

5.3.2 Characteristics of Fresh Devices and 2-bit operation

Figure 5.3 shows the Ids-Vgs curves of the HfO2 nanocrystal memory devices with programming time of 10μs for different programming conditions. Channel hot-electron injection and band-to-band hot-hole injection were employed for programming and erasing, respectively. All cells described in this chapter have dimensions of L/W = 50/50 nm. A relatively large memory window of about 2.2V can be achieved at the Vg=11V, Vd=4V, T=1ms program operation. Program characteristics as a function of pulse width for different operation conditions are shown in Fig. 5.4(a). Both source and substrate terminals were biased at 0V. The “Vt

shift” is defined as the threshold voltage change of a device between the written and the erased states. With Vd=4V, Vg=11V, relatively high speed (1ms) programming

performance can be achieved with a memory window of about 2.2V. Meanwhile, Fig.

5.5(b) displays the erase characteristics as a function of various operation voltages.

Again, excellent erase speed of around 0.1 ms can be obtained.

The retention characteristics of the HfO2 nanocrystal memory for the fresh devices at different temperature (T=25°C, 85°C, and 125°C) are illustrated in Fig. 5.5.

The retention time can be up to 10⁸ seconds for 17%, 30% and 71% charge loss at temperature 25^oC, 85°C and 125^oC. Much charge loss has been seen for the both samples. We ascribe these results that the the HfO2 nanocrystals have good formation at the RTA at the temperature 950°C for 15sec. The endurance characteristics after 10⁶ P/E cycles are also shown in Fig. 5.6. The programming and erasing conditions are Vg= 10V for 1ms and Vg=-10V for 1ms, respectively. Small memory window narrowing has been displayed. This trend indicates that the amount of operation-induced trapped electrons is very tiny. Certainly, this is intimately related to the use of ultra-thin tunnel oxide and very minute amount of residual charges in the HfO2 nanocrystals after cycling. Fig. 5.7 demonstrates the feasibility of performing two-bit operation with our HfO2 nanocrystal memories through a reverse read scheme in a single cell. From the Ids–Vgs curves, it is clear that we could employ forward and reverse reads to detect the information stored in the programmed bit1 and bit2, respectively. The read operation was achieved using a reverse read scheme.

5.3.3 Different length and width characteristics

In the fabricated ultranarrow-channel memory, a larger threshold voltage shift has been observed than in the wide-channel memory for different length and width (Fig. 5.8(a)(b) and Fig. 5.9(a)(b)). From numerical calculations, it turns out that this is caused by bottleneck regions that dominate the conductance of the whole channel in

the ultranarrow-channel. In the wide channel, the current can flow through the wide and low-potential region. In the ultranarrow channel, on the contrary, the current path is completely blocked at the bottleneck region where one dot covers almost the entire channel bottleneck effect. Moreover, the average potential in the ultranarrow channel is higher than in the wide channel because of the effects of dots on the side surfaces.

These effects are the origins of larger Vt shift in the ultranarrow devices.

5.3.4 Disturbance

Figure 5.10 demonstrates the read disturbance induced erase-state threshold voltage instability in a localized HfO2 nanocrystal trapping storage Flash memory cell under several operation conditions. For two-bit operation, the applied bitline voltage in a reverse-read scheme must be sufficiently large (>1.5 V) to be able to “read through” the trapped charge in the neighboring bit. The read-disturb effect is the result of two factors: the word-line and the bit-line. The word-line voltage during read may enhance room temperature (RT) drift in the neighboring bit [5.13]. On the other hand, a relatively large read bit-line voltage may cause unwanted channel hot-electron injection and, subsequently, result in a significant threshold voltage shift of the neighboring bit. In our measurements, the gate and drain biases were applied and the source was grounded. The results demonstrate clearly that almost no read disturbance occurred in our HfO2 nanocrystal Flash memory under low-voltage reading (Vg = 1.5 V; Vd = 1V~2.5 V). For a larger memory window, we found that no read disturbance can be observed after operation after 1000 s at 25 °C.

5.3.5 Few Electron Effect

Firstly, we studied the drain current versus gate voltage characteristic, IdVg of the

memory devices at room temperature. IdVg characteristics of the HfO2 nanocrystal memories clearly show the occurrence of few electron effects. In particular, in Fig.

5.11, the continuous curve corresponds to the IdVg measurement, performed on a written device, when the gate bias is slowly swept down from 3 to -2 V. On this characteristic, abrupt peaks on the current are observed, corresponding to the subsequent discharging of few electrons from a HfO2 nanocrystal. The dashed lines correspond to the same measurements performed with a fast voltage sweep on the same device after various writing conditions. In this case, no discharging event occurs during the measurement. Moreover, we can note that the continuous curve abruptly jumps from one dashed line to the other. Note that simultaneous injection/emission of electrons from different HfO2-dots is improbable due to the fact that dots are largely spread in size in our devices. As reported in [5.14], the threshold voltage shift, Vth △ induced by one electron trapped in the a HfO2-dot can be estimated as

(1) where Cfg is the dot to gate capacitance, Ccg the channel to gate capacitance and the Cfc channel to dot capacitance. The following expressions for the capacitances are taken: Cfg=εOXAdot/t2; Ccg=εOX(A-Adot)/(t1+t2); Cfc=εOXAdot/t1 where Adot is the HfO2-dot area, A is the total active area of the device (given by the top and the lateral sides of the SOI channel covered by the gate), t1 and t2 are the tunnel and control oxide thickness, respectively, and εOX is the oxide dielectric constant. After developments, (1) yields

(2) It should be stated that, in this capacitive approach, the threshold voltage shift is independent from the area of the HfO2 dot, but only depends on the total gate area A

and on the number of charges trapped in the HfO2-dot. Based on (2), the threshold voltage shift induced by only one electron trapped in one HfO2-dot, named hereafter

and on the number of charges trapped in the HfO2-dot. Based on (2), the threshold voltage shift induced by only one electron trapped in one HfO2-dot, named hereafter

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