Few Electron Effect

Firstly, we studied the drain current versus gate voltage characteristic, IdVg of the

memory devices at room temperature. IdVg characteristics of the HfO2 nanocrystal memories clearly show the occurrence of few electron effects. In particular, in Fig.

5.11, the continuous curve corresponds to the IdVg measurement, performed on a written device, when the gate bias is slowly swept down from 3 to -2 V. On this characteristic, abrupt peaks on the current are observed, corresponding to the subsequent discharging of few electrons from a HfO2 nanocrystal. The dashed lines correspond to the same measurements performed with a fast voltage sweep on the same device after various writing conditions. In this case, no discharging event occurs during the measurement. Moreover, we can note that the continuous curve abruptly jumps from one dashed line to the other. Note that simultaneous injection/emission of electrons from different HfO2-dots is improbable due to the fact that dots are largely spread in size in our devices. As reported in [5.14], the threshold voltage shift, Vth △ induced by one electron trapped in the a HfO2-dot can be estimated as

(1) where Cfg is the dot to gate capacitance, Ccg the channel to gate capacitance and the Cfc channel to dot capacitance. The following expressions for the capacitances are taken: Cfg=εOXAdot/t2; Ccg=εOX(A-Adot)/(t1+t2); Cfc=εOXAdot/t1 where Adot is the HfO2-dot area, A is the total active area of the device (given by the top and the lateral sides of the SOI channel covered by the gate), t1 and t2 are the tunnel and control oxide thickness, respectively, and εOX is the oxide dielectric constant. After developments, (1) yields

(2) It should be stated that, in this capacitive approach, the threshold voltage shift is independent from the area of the HfO2 dot, but only depends on the total gate area A

and on the number of charges trapped in the HfO2-dot. Based on (2), the threshold voltage shift induced by only one electron trapped in one HfO2-dot, named hereafter δVth, in a device with W=L=50nm, is about 15 mV. Note that this value is of the same order of magnitude of the average experimental threshold voltage shift, which can be extracted from Fig. 5.11. Fig. 5.12(a)(b) is the IdVg of the memory devices at low temperature (40°K). The IdVg characteristics of the HfO2 nanocrystal memories clearly also show the occurrence of few electron effects. On this characteristic, abrupt peaks on the current are observed, corresponding to the subsequent discharging of few electrons from a HfO2 nanocrystal. For the slowly swept, abrupt peaks are observed more clearly because more electron discharging, but they still have the same order of magnitude of almost 15mV.

5.4 Summary

In this chapter, we have proposed a novel simple, reproducible, reliable technique for preparation of 50nm high density HfO2 nanocrystals using spinodal decomposition of hafnium silicate on SOI and achieved nanocrystal memories with characteristics in terms of large memory windows, high speed program/erase, retention time, and good endurance. Few Electron Phenomena at 40°K has been observed clearly.

Discontinuities appear, that is corresponding to discharging of few electron from HfO2

nanocrystals.

Fig. 5.1 HfO2 nanocrystal Flash memory cell structure.

(a)

(b)

Fig. 5.2 (a) Planar-view HRTEM image of the 50nm HfO2 nanocrystals devices. (b) Planar-view HRTEM image of the HfO2 nanocrystals trapping layer.

V _g (V)

Fig. 5.3 Ids-Vgs curves of programmed memories with different programming conditions. The programming time is 10μs. A memory window of larger than 3V can be achieved with Vg= Vd=10V programming operation.

Time (sec)

10

^-7

10

^-6

10

^-5

10

^-4

10

^-3

10

^-2

10

^-1

10

⁰

V t shift (V)

0 1 2 3 4

V

_g

=8V, V

_d

=3V V

_g

=8V, V

_d

=4V V

_g

=10V, V

_d

=4V V

_g

=11V, V

_d

=4V

Fig. 5.4 (a) Program characteristics of HfO2 nanocrystal memory devices with different programming conditions. (b). Erase characteristics of HfO2 nanocrystal memory devices with different erasing voltages.

Time (sec)

10

^-7

10

^-6

10

^-5

10

^-4

10

^-3

10

^-2

10

^-1

10

⁰

V t shift (V)

-6 -5 -4 -3 -2 -1 0

V

_g

=-3V, V

_d

=3V V

_g

=-3V, V

_d

=4V V

_g

=-4V, V

_d

=3V

Fig. 5.4 (a) Program characteristics of HfO2 nanocrystal memory devices with different programming conditions. (b). Erase characteristics of HfO2 nanocrystal memory devices with different erasing voltages.

Fig. 5.5 Retention characteristics of HfO2 nanocrystal memory devices at T=25°C.

Fig. 5.6 Endurance characteristics of HfO2 nanocrystal memory devices. Negligible degradation is found even after 10⁵ P/E cycles.

V

_g

(V)

Fig. 5.7 Ids–Vgs Curves of the two-bit memory in a cell; forward read and reverse read for programmed bit1 and programmed bit2.

Channel length (nm)

60 80 100 120 140 160

V t shift (V)

0.0 0.5 1.0 1.5 2.0 2.5

(a)

(b)

Fig. 5.8 (a) Room-temperature hysteresis characteristics of the fabricated devices with various channel lengths. (b) The carrier mobiles with various channel lengths.

Channel width (nm)

20 40 60 80 100 120 140 160

V t shift (V)

0.0 0.5 1.0 1.5 2.0 2.5 3.0

(a)

(b)

Fig. 5.9 (a) Room-temperature hysteresis characteristics of the fabricated devices with various channel widths. (b) The carrier mobiles with various channel widths.

Read disturb time (sec)

10

⁰

10

¹

10

²

10

³

V t shift (V)

-0.4 -0.2 0.0 0.2

0.4 ^V

^g

^{=1.5V, V}

^d

^=1V

V

_g

=1.5V, V

_d

=1.5V V

_g

=1.5V, V

_d

=2V V

_g

=1.5V, V

_d

=2.5V

Fig. 5.10 Read disturbance characteristics of the HfO2 nanocrystal memory devices.

Fig. 5.11 Drain current versus gate voltage characteristic.

(a)

(b)

Fig. 5.12 Drain current versus gate voltage characteristic at low temperature (40°K) for different swept times. (a) delay=0 sec. (b) delay=0.1sec.

Chapter 6

2-Bit Lanthanum Oxide Trapping Layer Nonvolatile Flash Memory

6.1 Introduction

Silicon–oxide–nitride–oxide–silicon (SONOS) charge trapping-based nonvolatile memories have received a considerable amount of interest recently [6.1–6.3].

Obtaining nonvolatile, low-power, fast memories with short dimensions remains a key challenge in the electronics industry. According to the International Technology Roadmap for Semiconductors (ITRS) [6.4], the key issue for floating-gate nonvolatile semiconductor memories is the scaling of the tunneling oxide; the stress-induced leakage current (SILC), which can discharge the whole floating-gate memory with even one single defect, becomes a severe problem at very thin tunneling oxide thicknesses. This scaling issue remains a formidable challenge, especially for emerging system-on-chip (SOC) integrated circuit designs in which the programming voltage must be scaled for the nonvolatile memories to be compatible with low-voltage logic circuits. High-k dielectric materials, such as hafnium oxide (HfO2) and lanthanum oxide (La2O3), are promising candidates to replace Si3N4 films as the charge trapping layer of SONOS-type Flash memories [6.5]. Such high-κ dielectric films are expected to exhibit better charge trapping characteristics than are displayed by conventional Si3N4 films; their sufficient densities of trap states and deep trap energy levels should result in longer retention times [6.6-6.7]. This feature suggests that HfO2 will be more practical for further scaling of the tunnel oxide to enhance the performance and more suitable for the development of SONOS-type memories that

perform multi-bit operations [6.8-6.9]. Moreover, a greater voltage drop at the tunnel oxide can be obtained when using the high-k material as the trapping layer. Therefore, low-power, high-speed operation at short dimensions is achievable for high-k SONOS-type memories.

In this chapter, we prepared high-k SONOS-type memories incorporating lanthanum oxide (La2O3) as the trapping layer. These memories exhibit good characteristics: considerably large memory windows, high speed programming/erasing, good retention times, high endurance, and low disturbance.

6.2 Experimental

Figure 6.1 displays the structure and process flow for the preparation of the La2O3 high-k memories. The fabrication of the La2O3 memory devices involved the LOCOS isolation process on p-type, 5–10 Ω cm, (100) 150-mm silicon substrates.

First, a 2-nm-thick tunnel oxide was grown thermally at 1000 °C in vertical furnace system. Next, a 4-nm-thick lanthanum oxide layer was deposited using the E-gun method with La2O3 targets. Subsequently, the samples were subjected to RTA treatment under an O2 ambient at 900 °C for 1 min. A blocking oxide (ca. 7 nm) was deposited using high-density-plasma chemical vapor deposition (HDPCVD) followed by a N2 densification process at 900 °C for 1 min. Poly-Si deposition, gate lithography, gate etching, source/drain (S/D) implanting, substrate and contact patterning, followed by the rest of the subsequent standard CMOS procedure, were then performed to complete the fabricating of the La2O3-containing high-k SONOS-type memory devices.

6.3 Results and Disscussion

6.3.1 Devices Operation

Figure 6.2 shows the cross-sectional high-resolution transmission microscopy (HRTEM) images of the gate stacks of the La2O3 Flash memory. For SONOS-type structure, the thicknesses of the tunnel oxide, La2O3 trapping layer, and blocking oxide layer are 2nm, 4nm, and 7nm, respectively. For the operation of our La2O3

SONOS-type memory, we employed channel hot-electron injection and band-to-band hot-hole injection for the programming and erasing, respectively. All devices described in this paper had dimensions of L/W = 2/1 μm. Figure 6.3 demonstrates the feasibility of performing two-bit operation with our La2O3 SONOS-type memory through a forward read and reverse read scheme in a single cell [6.10]. From the Ids–Vgs curves, it is clear that we could employ forward and reverse reads to detect the information stored in the programmed bit1 and bit2, respectively. The read operation was achieved using a reverse read scheme. Table 6.1 summarizes the bias conditions for two-bit operation.

Program characteristics as a function of pulse width for different operation conditions are shown in fig. 6.4. Both source and substrate terminals were biased at 0V. The “Vt shift” is defined as the threshold voltage change of a device between the programmed and the erased states. With Vd=Vg=9V, relatively high speed (t=100μs) programming performance can be achieved with a memory window of about 2.2V.

Meanwhile, Fig. 6.5 displays the erase characteristics as a function of various operation voltages. Again, excellent erase speed of a memory window around 10 ms can be obtained. More important, there is only a very small amount of over-erase observed. The reason is owing to the fact that we use the band-to-band hot-hole injection, the vertical electric field will decrease with decreasing amount of trapped electrons in the trapping layer during erasing and the hole injection into the trapping

layer will reduce significantly.

Figure 6.6 illustrates the retention characteristics observed at temperatures of 25, 85, and 125 °C. At room temperature, the charge loss of the memory incorporating the La2O3 trapping layer was below 19% after 10⁸ s; this behavior is probably related intimately to the trap energy level in high-κ dielectrics [6.11]. The retention behavior deteriorated, however, as the temperature increased: we obtained 38 and 63% charge losses at 85 and 125 °C, respectively, after 10⁸ s. We calculated the activation energy of the traps in the La2O3 layer of a fresh device. Activation energy tracing is used widely to characterize the Arrhenius relation extracted from the temperature dependence of charge loss in a nonvolatile memory as a function of time. For a given charge-loss threshold criterion (in our case, 20%), the failure rates obtained at higher temperatures (125–200 °C), with five measurements at each temperature, were then extrapolated to the nominal operating conditions. We obtained an extracted activation energy of 1.25 eV for the La2O3 trapping layer. Obviously, this value is higher than those reported previously for conventional SONOS memories [6.12–6.14].

Figure 6.7 displays the endurance characteristics after 10⁵ P/E cycles (programming conditions: Vg = Vd = 10 V for 100 μs; erasing conditions: Vg = –3V, Vd

= 10 V for 1 ms). A slight memory window narrowing occurred and individual threshold voltage shifts become visible in the program and erase states after 10² cycles.

This finding suggests the formation of operation-induced trapped electrons. Certainly, this feature is related intimately to the use of the ultra-thin tunnel oxide and the minute amount of residual charge remaining in the La2O3 layer after cycling.

6.3.2 Disturbances

Figure 6.8 shows the programming drain disturbance of our La2O3 SONOS-type

memory. Three different drain voltages (Vd = 5, 7 and 9 V) were applied in the programming drain disturbance measurements at room temperatures. We observed that a sufficient programming drain disturb margin exists (ΔVt < 1 V), even after programming at a value of Vd of 9V under room temperature and after stressing for 1000 s. Figure 6.9 shows the gate disturbance characteristics in the erasing state. Gate disturbance may occur during programming for the cells sharing a common word-line while one of the cells is being programmed. We observed a threshold voltage shift of only 0.9V under the following conditions: Vg = 10 V; Vs = Vd = Vsub = 0 V; stressed for 1000 s. Because of the small voltage drop at the tunnel oxide by using a serial capacitor voltage divider model, this memory can exhibit such good gate disturb characteristics with such a thin tunnel oxide.

Figure 6.10 demonstrates the read disturbance induced erase-state threshold voltage instability in a localized La2O3 trapping storage Flash memory cell under several operation conditions. For two-bit operation, the applied bitline voltage in a reverse-read scheme must be sufficiently large (>2 V) to be able to “read through” the trapped charge in the neighboring bit. The read-disturb effect is the result of two factors: the word-line and the bit-line. The word-line voltage during read may enhance room temperature (RT) drift in the neighboring bit [6.15]. On the other hand, a relatively large read bit-line voltage may cause unwanted channel hot-electron injection and, subsequently, result in a significant threshold voltage shift of the neighboring bit. In our measurements, the gate and drain biases were applied and the source was grounded. The results demonstrate clearly that almost no read disturbance occurred in our La2O3 Flash memory under low-voltage reading (Vg = 3 V; Vd = 2.5 V). For a larger memory window, we found that only a small read disturbance (ca. 0.3 V) can be observed after operation at Vd = 4 V after 1000 s at 25 °C.

6.4 Summary

In this chapter, we have investigated the memory effect on the performance of the La2O3 SONOS-type memories. It has good characteristics in terms of large memory windows, high speed program/erase, good retention time, excellent endurance, and 2-bit operation. Hence, La2O3 are the candidates used for the trapping layers for the SONOS-type memories.

Fig. 6.1 Schematic representation of the La2O3 SONOS-type Flash memory cell structure and localized charge storage.

Fig. 6.2 Planar-view HRTEM image of the La2O3 SONOS-type memory.

V _g (V)

Fig. 6.3 Ids–Vgs Curves of the two-bit memory in a cell; forward read and reverse read for programmed bit1 and programmed bit2.

Table 6.1 Operation principles and bias conditions utilized during the operation of the La2O3 SONOS-type memory cell.

Time (sec)

10

^-7

10

^-6

10

^-5

10

^-4

10

^-3

10

^-2

10

^-1

10

⁰

Vt shift (V)

0 1 2 3 4 5 6

V

_g

=7V, V

_d

=7V V

_g

=8V, V

_d

=8V V

_g

=9V, V

_d

=9V V

_g

=10V, V

_d

=10V

Fig. 6.4 Program speed of the La2O3 SONOS-type memory

Time (sec)

10

^-6

10

^-5

10

^-4

10

^-3

10

^-2

10

^-1

10

⁰

Vt shift (V)

-3 -2 -1

0 ^V

^g

^{= -3V, V}

^d

^=9V

V

_g

= -4V, V

_d

=9V V

_g

= -5V, V

_d

=9V

Initial Vt

Fig. 6.5 Erase speed of the La2O3 SONOS-type memory.

Time (sec)

10

⁰

10

¹

10

²

10

³

10

⁴

10

⁵

10

⁶

10

⁷

10

⁸

Normalized Vt (V)

0 20 40 60 80 100

T=25

^o

C T=85

^o

C T=125

^o

C

Fig. 6.6 Retention of. the La2O3 SONOS-type memory for three temperature (T=25^oC, 85^oC,and 125^oC). 22% charge loss occurred at 25 °C; and 40% charge loss occurred at 125 °C up to 10⁸ sec..

P/E cycles

10

⁰

10

¹

10

²

10

³

10

⁴

10

⁵

Vt (V)

2 3 4 5 6 7 8

Erase state, V_g= -3V, V_d=10V, t=1ms Program state, V_g= 10V, V_d= 10V, t=0.1ms

Fig. 6.7 Endurance characteristics of the La2O3 SONOS-type memory after 10k P/E cycling.

Drain disturb time (sec)

10

⁰

10

¹

10

²

10

³

Program state Vt shift (V) ^-2.0

-1.5 -1.0 -0.5 0.0 0.5 1.0

V

_d

=5V V

_d

=7V V

_d

=9V

Fig. 6.8 Drain disturbance characteristics of the La2O3 SONOS-type memory. After 1000 s at 25 °C, only a 1V drain disturb margin was observed.

Gate disturb time (sec)

10

⁰

10

¹

10

²

10

³

Program st ate Vt shift ( V )

-1.0 -0.5 0.0 0.5 1.0 1.5 2.0

Program state, V

_g

=8V Program state, V

_g

=9V Program state, V

_g

=10V

Fig. 6.9 Gate disturbance characteristics of the La2O3 SONOS-type memory. A threshold voltage shift of only 1 V occurred after stressing at Vg = 10 V and Vs = Vd = Vsub = 0 V for 1000 s.

Read disturb time (sec)

10

⁰

10

¹

10

²

10

³

Vt shift (V)

-1.0 -0.5 0.0 0.5 1.0 1.5 2.0

V

_g

=4.5V, V

_d

=2V V

_g

=4.5, V

_d

=3V V

_g

=4.5V, V

_d

=4V

Fig. 6.10 Read disturbance characteristics of the La2O3 SONOS-type memory devices.

No significant Vt shift occurred for Vd < 4, even after 1000 s at 25 °C.

Chapter 7

Conclusions and Further Recommendations

7.1 Conclusions

In this thesis, for the chapter 2, we propose a novel, simple, reproducible, and reliable technique for the design of high-density HfO2 nanocrystals through the spinodal decomposition of hafnium silicate. Our nanocrystal memory exhibits superior characteristics in terms of negligible lateral or vertical migration of stored charge and good disturbance characteristics. The cells after 10k P/E cycling also show a long retention time and excellent endurance. With these superior performance, we believe that HfO2 nanocrystal Flash memory is quite suitable for the two-bit operation and that it has great potential for replacing the ONO stack in conventional SONOS-type Flash memory.

Then, in the chapter 3, we have investigated the effect of post-deposition annealing temperature on the performance of the resultant HfO2 SONOS-type Flash memories. Higher temperature treatment can have large memory windows due to the crystallization-induced trap generation whereas lead to poorer retention and endurance performances. Moreover, we found that the HfO2 trapping layer can trap both electrons and holes. No significant read, drain and gate disturbances were observed for three samples. HfO2 SONOS-type Flash memory is considered to be a promising candidate for the Flash memory devices application.

In this chapter 4, we have studied three kinds of high-k dielectrics, including HfO2, Hf-silicate and Zr-silicate for the trapping layer of the poly-Si TFT memory devices with two different thickness tunnel oxides. By sticking with sufficiently low

thermal-budget processing, we have successfully demonstrated the feasibility of fabricating nonvolatile poly-Si TFT memories with excellent characteristics in terms of large memory windows, good speed program/erase, long retention time and 2-bit operation. Moreover, the poly-Si grain boundary is the concerned issues about the disturbance characteristics. We demonstrated that the reliability characteristics of a poly-Si-TFT memory device in terms of retention, drain and gate disturbance are closely related to the defects along the grain boundaries in the channel. The NH3

plasma treatment is one of the useful methods to improve the SiO2/poly-Si interface and the channel quality because it can effectively eliminate the trap densities in both regions. These poly-Si TFT memories make the realization of producing the embedded nonvolatile memories for system on the panel.

In this chapter 5, we have proposed a novel simple, reproducible, reliable technique for preparation of 50nm nano-scaled tri-gate HfO2 nanocrystals using spinodal decomposition of hafnium silicate on SOI and achieved nanocrystal memories with characteristics in terms of large memory windows, high speed program/erase, retention time, and good endurance. Few Electron Phenomena at 40°K has been observed clearly. Discontinuities appear, that is corresponding to discharging of few electron from HfO2 nanocrystals.

In chapter 6, we have investigated the memory effect on the performance of the La2O3 SONOS-type memories. It has good characteristics in terms of large memory windows, high speed program/erase, good retention time, excellent endurance, and 2-bit operation. Hence, La2O3 are the candidates used for the trapping layers for the SONOS-type memories.

7.2 Further Recommendations

There are some interesting topics for further study. First, for the nanocrystal, we can use other high-k materials such ZrO2 nanocrystal. Moreover, we can change the SiO2 base to the Al2O3 base. Second, we can change other high-k dielectric trapping layer such as Pr2O3 and CeO2. Third, high-k PMOS Flash memory can realize. Final, we can use High-k dielectric tunnel oxide to obtain high speed operation.

References

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[1.10] Marvin H. White, Dennis A. Adams, and Jiankang Bu, “On the Go with SONOS”, IEEE Circuits and Devices Magazine, vol. 16, pp. 22-31, Jul. 2000.

[1.11] “Test and test equipment” in The International Technology Roadmap for Semiconductors (ITRS), 2001, pp. 27-28.

[1.12] Y. N. Tan, W. K. Chim, W. K. Choi, M. S. Joo, T. H. Ng, and B. J. Cho,

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[1.13] W.J. Zhu, Tso-Ping Ma, Takashi Tamagawa, J. Kim, and Y. Di, “Current Transport in Metal/Hafnium Oxide /Silicon Structure”, IEEE Electron Device Lett., vol. 23, no. 2, pp. 97-99, Feb. 2002.

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[1.15] Yu-Hsien Lin, Chao-Hsin Chien, Ching-Tzung Lin, Chun-Yen Chang, and

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