Disturbances…

Figure 3.8 shows the read disturb induced erase-state threshold voltage instability in a localized HfO2 SONOS-type Flash memory cell for three samples. To allow for two-bit operation, the applied bitline voltage in reverse-read scheme must be sufficiently large (>1.5V) for being able to “read-through” the trapped charge in the

neighboring bit. Relatively large read bitline voltage may cause unwanted electron injection and then result in a significant threshold voltage shift of the neighboring bit.

For our measurement, the gate and drain biases were applied and the source was ground. The results clearly show that almost no read disturbance appear for the low voltage reading operation of Vg -Vt= 3V and Vd = 2.5V in our HfO2 Flash memory.

Figure 3.9 shows the programming drain disturbance of our HfO2 SONOS-type Flash memories. The same drain voltages (Vd = 8V) were applied in the programming drain disturbance measurements at room temperature (T = 25°C). Upon the increasing annealing temperature, the more drain disturbances were observed. The storage charge leakage path along the grain boundaries induce more drain disturbances for the annealed devices. After 1000 seconds at 25°C, we have sufficiently drain disturb margin (< 0.3V) for the three annealed samples.

Figure 3.10 shows the gate disturb characteristics in the erasing state. Gate disturbance may occur during programming for the cells sharing a common wordline while one of the celles is being programmed. We measured the gate disturbance with the condition at Vg-Vt=7V and Vd=Vs=Vsub=0V for the three annealed samples. With the annealing temperature increases, the more gate disturbances were observed. A large amount trap generates in the high temperature annealing that induces more gate disturbances for the annealed devices. Only 0.5V threshold voltage shift has been observed for the 900ºC annealed devices after 1000 seconds stressing. Such good gate disturb characteristic with such thin tunnel oxide can be explained by using serial capacitor voltage divider model with small voltage drop at the tunnel oxide. In summary, we have good read, drain and gate disturbances for the as-deposited, 600°C-annealed and 900°C-annealed samples.

3.3.3 Charge pumping characteristics

The charge pumping (CP) measurement was used to investigate the characteristics of our HfO2 Flash memory. We used a trapezoidal gate pulse having a fixed pulse amplitude with a varying Vgbl. The substrate current (the so-called “charge pumping current,” Icp) as a function of Vgbl was measured. The gate pulse have a frequency of 1 MHz and a 50% duty cycle; the rising and falling times were both 2 ns.

Fig. 2.11 shows plots of the program state charge pumping current Icp versus Vgbl for our HfO2 nanocrystal memory cell. Fowler–Nordheim tunneling was used to program the cell with Vt levels from 2.20 to 3.55 V. The program state Icp curve shifted increasingly toward the right upon increasing the value of Vt as a result of an increase in the amount of injected charge in the HfO2 trapping layer. So, we conclude that HfO2 can behave as an charge trapping centers for our SONOS-type Flash memories.

3.4 Summary

In this chapter, we have investigated the effect of post-deposition annealing temperature on the performance of the resultant HfO2 SONOS-type Flash memories.

Higher temperature treatment can have large memory windows due to the crystallization-induced trap generation whereas lead to poorer retention and endurance performances. Moreover, we found that the HfO2 trapping layer can trap both electrons and holes. No significant read, drain and gate disturbances were observed for three samples. HfO2 SONOS-type Flash memory is considered to be a promising candidate for the Flash memory devices application.

Fig. 3.1 Schematic cross section and process flow of the HfO2 SONOS-type Flash memory device.

Table 3.1 Operation principles and bias conditions utilized during the operation of the HfO2 Flash memory cell.

Programming time (sec)

10

^-7

10

^-6

10

^-5

10

^-4

10

^-3

10

^-2

10

^-1

10

⁰

V

t

shift (V)

0 1 2 3 4 5 6

As-deposited, V_g-V_t=7V, V_d=6V 600^oC, V_g-V_t=7V, V_d=6V

900^oC, V_g-V_t=7V, V_d=6V

Fig. 3.2 Programming characteristics of the HfO2 SONOS-type Flash memories. It was clearly observed that the programming speed and the memory window increase when the annealing temperature increases.

Erasing time (sec)

10

^-6

10

^-5

10

^-4

10

^-3

10

^-2

10

^-1

10

⁰

V

t

shift (V)

-4 -3 -2 -1

0

As-deposited, V_g-V_t=-6V, V_d=8V

600^oC, V_g-V_t=-6V, V_d=8V 900^oC, V_g-V_t=-6V, V_d=8V

Initial V_t

Fig. 3.3 Erasing characteristics of the HfO2 SONOS-type Flash memories. With the annealing temperature increases, the erasing speed increase and shows little overerasure.

Angle (2θ)

30 40 50

900^oC 600^oC

As-deposited m(111)

m(102) m(002)

Fig. 3.4 X-ray Diffraction (XRD) analysis of the HfO2 trapping layer with different temperature.

Retention time (sec)

10

⁰

10

¹

10

²

10

³

10

⁴

10

⁵

10

⁶

10

⁷

10

⁸

10

⁹

V

t

shift (V)

1.5 2.0 2.5 3.0 3.5 4.0 4.5

As-deposited, T=25

^o

C 600

^o

C, T=25

^o

C

900

^o

C, T=25

^o

C

10 years

Fig. 3.5 Retention characteristics of the HfO2 SONOS-type Flash memories at room temperature T=25°C. The 900°C-annealed device shows the worst retention performance.

P/E cycles

10

⁰

10

¹

10

²

10

³

10

⁴

10

⁵

10

⁶

V

t

shift(V)

0 1 2 3 4 5

As-deposited, erase state (V_g-V_t= -6V, V_d=8V, t=10ms) As-deposited, program state (V_g-V_t=7V, V_d=6V, t=100μs) 600^oC, erase state (V_g-V_t=-6V, V_d=8V, t=10ms)

600^oC, program state (V_g-V_t=7V, V_d=6V, t=100μs) 900^oC, erase state (V_g-V_t=-6V, V_d=8V, t=10ms) 900^oC, program state (V_g-V_t=7V, V_d=6V, t=100μs)

Fig. 3.6 Endurance characteristics of the HfO2 SONOS-type Flash memories. The 900° C-annealed device shows larger memory window but worse endurance performance in the same condition.

Time (sec)

10

⁰

10

¹

10

²

10

³

10

⁴

V

t

shift (V)

1.0 1.5 2.0 2.5 3.0 3.5 4.0

As-deposited, V

_g

-V

_t

= -12V 600

^o

C, V

_g

-V

_t

= -12V

900

^o

C, V

_g

-V

_t

= -12V

Fig. 3.7 Vertical migration characteristics of HfO2 SONOS-type Flash memories.

Consistent with the former result, the vertical charge migration is exacerbated by increasing annealing temperature.

Read disturb time (sec)

10

⁰

10

¹

10

²

10

³

V

t

shi ft (V)

-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0

As-deposited, V_g-V_t=3V, V_d=2.5V 600^oC, V_g-V_t=3V, V_d=2.5V

900^oC, V_g-V_t=3V, V_d=2.5V

Fig. 3.8 Read disturbance characteristics of HfO2 SONOS-type Flash memories. No significant Vt shift for all samples even after 1000 seconds at 25°C.

Drain disturb time (sec)

10

⁰

10

¹

10

²

10

³

Program state V

t

shift (V)

-0.4 -0.2 0.0

0.2 As-deposited, V

_d

=8V 600

^o

C, V

_d

=8V

900

^o

C, V

_d

=8V

Fig. 3.9 Drain disturbance characteristics of HfO2 SONOS-type Flash memories. After 1000 seconds at 25°C, only 0.4V drain disturb margin is observed for the 900ºC annealed devices.

Gate disturb time (sec)

10

⁰

10

¹

10

²

10

³

V

t

shi ft (V)

-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2

As-deposited, V_g-V_t=7V, V_d=V_s=V_sub=0V 600^oC, V_g-V_t=7V, V_d=V_s=V_sub=0V

900^oC, V_g-V_t=7V, V_d=V_s=V_sub=0V

Fig. 3.10 Gate disturbance characteristics of HfO2 SONOS-type Flash memories.

Only 0.5V threshold voltage shift has been observed for the 900ºC annealed devices after Vg-Vt=7V and Vs=Vd=Vsub=0V, 1000 seconds stressing.

Vgl (V)

0 1 2 3 4 5 6

Icp (A)

10^-9

10^-8

Erase state=2.20V Vt=2.57V

Vt=2.97V Vt=3.55V

Oxide/HfO

₂

/oxide device

Fig. 3.11 Plots of Icp vs Vgbl for the HfO2 memory cell after F–N programming to different Vt levels.

Chapter 4

Low Temperature Polycrystalline Silicon Thin-Film Flash Memory with High-k Materials

4.1 Introduction

Polycrystalline silicon thin-film transistors (Poly-Si-TFT) have been widely used to integrate driver circuits for the application of AMLCD’s [4.1]. With progressive manufacturing technologies, the complexity of circuit integration will continue to increase. Currently, the feasibility of integrating an entire system on top of the panel (SOP) is being actively pursued [4.2]. Since a system shall include the functionality of memory, efforts shall be paid in order to successfully integrate the memories, such as SRAM, EEPROM, and Flash memory, directly on the panel [4.3-4.6]. SONOS (poly-Si-oxide-nitride-oxide-silicon)-type nonvolatile memory based on discrete storage nodes possesses great potential for achieving large memory windows, high program/erase speed, low programming voltage, low-power performance, excellent retention and good disturb characteristics [4.7].

In this chapter, we used three kinds of high-k dielectrics, including HfO2, Hf-silicate and Zr-silicate for the trapping layer of the poly-Si TFT memory. By employing low thermal cycle (600°C, 24hrs) for post high-κ deposition annealing and S/D activation, the proposed nonvolatile memory fabrication is fully compatible with the current mass-production TFT processing. This makes the realization of producing the embedded nonvolatile memories on the panel becomes feasible.

4.2 Experimental

The schematic diagram of the memory structure is illustrated in Fig. 4.1 First, 500-nm-thick thermal oxide was grown on the Si wafers by furnace system to substitute for the glass substrate and all the experimental devices in this study were fabricated on thermally-oxidized Si wafers. Then, a 100-nm-thick amorphous-silicon layer was deposited on thermally oxidized Si wafer by dissociation of SiH4 gas in a low-pressure chemical vapor deposition (LPCVD) at 550°C. Subsequently, solid phase crystallization (SPC) was performed at 600°C for 24 hours in N2 ambient for the phase transformation. Individual active regions were then patterned and defined.

After a standard RCA cleaning, two kinds of tunneling oxide thickness were deposited, one is 90-nm-thick TEOS oxide, the other is 200-nm-thick TEOS oxide. The followed by the depositions of three different kinds of high-k dielectrics, including HfO2, Hf-silicate and Zr-silicate thin films by co-sputtering method. A blocking oxide of about 33nm was then deposited by PECVD at 350°C. A 200-nm-thick poly-Si was deposited to serve as the gate electrode by LPCVD. Then, gate electrode was patterned and the regions of source, drain, and gate were doped by a self-aligned phosphorous ion implantation at the dosage and energy of 5×10¹⁵ ions/cm^-2 and 40keV, respectively. After S/D formation, which was activated at 600°C for 24-hr, passivation, metallization and NH3 plasma sintering were performed to complete the fabrication of the poly-Si TFT memories.

4.3 Results and Discussion 4.3.1 Material Analysis

Figure 4.2 shows the cross-sectional HRTEM images of the gate stacks of the poly-Si-TFT memories. For SONOS-type structure, the thicknesses of the tunnel

oxide and blocking oxide layer are 9nm, 33nm, respectively. The trapping layer thicknesses are 9.8nm, 20.1nm and 13.9nm for the memories with HfO2, Hf silicate, and Zr silicate, respectively. In addition, from the diffraction patterns, it is found that HfO2 and Hf silicate samples depict less degree of crystallization than Zr silicate after 600°C, 24hrs dopant activation. For the operation of our poly-Si-TFT memories, we employed channel hot-electron injection and band-to-band hot-hole injection for the programming and erasing, respectively. All devices described in this paper had dimensions of L/W = 1/1.5 μm. Fig. 4.3 demonstrates the feasibility of performing two-bit operation with our poly-Si-TFT memories through a reverse read scheme in a single cell [4.8]. From the Ids–Vgs curves, it is clear to see that we can conduct forward and reverse reads to detect the information stored in the programmed Bit1 and Bit2, respectively. We programmed the Bit1 and Bit2 with the bias condition of Vd = Vg = 12V with the programming time of 1ms, and erased the Bit1 and Bit2 with the bias condition of Vd = 10V and Vg = -10V with the erasing time of 10ms. The read operation was achieved using a reverse read scheme with Vd = 1V, Vg = 3.5V. Table 4.1 summarizes the bias conditions for two-bit operation.

4.3.2 Characteristics of three kinds of high-k TFT memories

We compared the characteristics of the three different kinds of high-k TFT memories with different trapping layers for the TFT memories. Program/erase characteristics of the poly-Si TFT memories with HfO2, Hf-silicate and Zr-silicate trapping layers are shown in figure 4.4 We can see that the program time can be as short as 1ms for a window of 3V with the operation condition of Vg=Vd=12V, and the erase time is about 10ms with Vg=-10V and Vd=10V for the HfO2 and Zr-silicate cases. While for the split with Hf-silicate, slightly poor performance arises from the

thicker trapping layer. Fig. 4.5 illustrate the retention times for the fresh memories at room temperatur. The memory with Zr-slicate trapping layer depicts the worst retention. However, its retention time can be up to 10⁶ s for 20% charge loss at room temperature and 10⁴ s for 30% charge loss at 85°C. Such a good retention is believed to be ascribed to the sufficiently deep trap energy level in the high-k dielectrics [4.8].

Besides, the quality of the tunnel oxide can play a strong role in charge retention.

Thus, further improvement of the tunnel oxide can be conducted for obtaining better charge keeping capability. Meanwhile, the endurance characteristics after 10⁵ P/E cycles for the memories with HfO2 , Hf silicate and Zr-silicate trapping layers are shown in Fig. 4.6 The programming and erasing conditions are Vg=Vd=12V for 1ms and Vg=-10V, Vd=10V for 10ms for both samples, respectively. Despite the occurrence of significant memory window narrowing, a memory window of about 2V is sustained even after 10⁵ P/E cycles. The origin of the narrowing over cycling, mainly coming from the increase of Vt in erased state, might be due to two factors:

The first is the mismatch between the localized spatial distributions for injected electrons and holes by using channel hot-electron programming and band-to-band hot-hole erasing. The uncompensated electrons will then cause the Vt to increase gradually over P/E cycling. The other is the stress-induced electron traps generated in the tunnel oxide during cycling. Therefore, in pursuing superior performance in charge storage capability of these new TFT memories, nano-dots formation [4.9], if feasible, and higher quality tunnel oxide are highly recommended.

4.3.3 Comparison of different tunnel oxide thickness

Now, we compared characteristics of the different tunnel oxide thickness samples for hafnium silicate TFT memories. Figure 4.7 shows the programming and erasing

characteristics, respectively, with different pulse widths for the Hf silicate TFT Flash memories for comparing two different tunnel oxide thickness samples. We used channel hot-electron injection for the programming with the bias condition at Vg = 10V and Vd = 10V and band-to-band hot-hole injection for erasing with the bias condition at Vg = 10V and Vd = -10V. For the tunnel oxide thickness effect, it was clearly observed that the programming speed and the memory window increase when the tunnel oxide thickness decreases for the short pulse width. But for long pulse width, the hot carrier saturate and the programming state and erasing state almost have the same memory windows. Figure 4.8 illustrates the retention characteristics for comparing two different tunnel oxide thickness samples for the fresh memory at different temperature. The retention time of the TFT memory with Hf silicate trapping layer can be up to 10⁸ seconds for 10% charge loss at room temperature. But the retention got worse as the temperature increased, 29% charge loss and 68% charge loss for the thick and thin tunnel oxide samples have obtained up to 10⁸ seconds. We have calculated the activation energy of the traps in the Hf silicate for the fresh device.

Activation energy tracing is used widely to characterize the Arrhenius relation extracted from the temperature dependence of charge loss in a nonvolatile memory as a function of time. For a given charge–loss threshold criterion (in our case, 20%), the failure rates can obtained then can be extrapolated to the nominal operating condition.

The extracted activation energies are 1.04, 1.33 eV for the 9nm and 20nm samples, respectively [4.10]. Obviously, it is in the higher ranges at those values previously reported for conventional SONOS memories [4.11–4.13]. Therefore, we thought that the thick tunnel oxide sample can be conducted for obtaining better charge keeping capability. Fig. 4.9 illustrates the retention characteristics for comparing two different tunnel oxide thickness samples for the fresh memories both at room temperature (T = 25 °C) and above (T = 125 °C). The same results have been observed formed, the

retention got worse as the temperature increased, and 56% charge loss and 70%

charge loss for the thick and thin tunnel oxide samples have obtained up to 10⁸ seconds. Thick tunnel oxide sample have better charge keeping capability in the 10k P/E cycled devices.

The endurance performances after 10⁵ P/E cycles for comparing two different tunnel oxide thickness samples are shown in figure 4.10. Again, the rate of memory window narrowing increases upon increasing P/E cycling and the thick samples have more memory window narrowing than the thin tunnel oxide samples. As we know, the narrowing is mainly coming from charge gain. Because of the use of thick tunnel oxide, there is only very large minute amount of trapped charges generated during operation in the tunnel oxide.

4.3.4 Disturbance characteristics

Disturbance characteristics are very important reliability characteristics of Flash memory, we showed the characteristics for taking the examples of the hafnium silicate samples. Figure 4.11 is the schematic circuitry of the NOR Flash memory array architectures, some failure phenomenon “disturbance” often takes place under operation when the electrical stress applied to those neighboring cells during programming a specific cell in the array for NOR Flash applications. During programming cell A, drain disturbance occurs in the cell B and same for those cells connected with the same bitline because the drain stress is applied to the same bitline (BL). On the other hand, gate disturbance occurs in the cell C and same for those cells connected with the same wordline because the gate stress is applied to the same wordline (WL). For the cell reading, the unwanted electron injection would happen while the wordline voltage and bitline voltage are under read operation. This

phenomenon would result in a significant threshold voltage shift of our selected reading cell. This is call read disturbance.

For almost all the popular Flash memory array architectures, erase is performed in blocks, and big chunk of devices are erased in one operation, so all the cells on the same bitline should be erased at the same time. In other words, drain disturb is a problem only during programming, when page or byte operations are employed.

Moreover, since the bias condition for the disturbed bits is ground gate, with high voltage on the drain, the worst case is the unwanted erase of programmed bits. Figure 4.12 shows the programming drain disturbance of our Hf silicate TFT Flash memories.

Two different drain voltages (Vd = 10V and 12 V, Vg=Vs=Vsub=0V) were applied at two different tunnel oxide thickness (t = 9nm and 20nm) samples in the fresh and cycled devices. We observed that a sufficient programming drain disturb margin exists (ΔVt < 0.7 V) in our operation windows (ΔVt < 3 V), even after programming at a value of Vd of 12V under 10k cycled devices after stressing for 1000 seconds. In particular, the Vt shift increased with the drain disturb time increased. This phenomenon is believed due to the presence of the localized traps along the grain boundaries in the channel, which can significantly affect the Vt shift through drain bias stressing [4.14-4.15]. The charge loss happened in the poly grain boundaries due to the band bending during drain bias stressing, the Vt should be increase that the channel electron charge can overcome the grain boundary sites to turn on the channel.

The high voltage drain bias stressing (Vg=12V) have more Vt shift can demonstrate the grain boundaries issues.

For the gate disturbance, the word line for the memory cells in a row is common, when we want to program one of the cells with channel hot electron (such as Vg=10V, Vd=10V), the gate terminals in the other memory devices will also sustain this high voltage. Therefore, programming may lead to the so-called gate disturbance for the

operation. Figure 4.13 shows the gate disturb characteristics in the erasing state. We measured the gate disturbance with the condition at Vg =10V and Vd=Vs=Vsub=0V for two different tunnel oxide thickness (t = 9nm and 20nm) samples in the fresh and cycled devices.. Only 0.7V threshold voltage shift has been observed for the 10k cycled devices after 1000 seconds stressing. But opposite to the drain disturbance, the Vt shift decreased with the gate disturb time increased. The same phenomenon for the localized traps along the grain boundaries in the channel affect much for the Vt shift through drain bias stressing [4.14-4.15]. The charge gain happened in the poly grain boundaries of the channel during gate bias stressing, the Vt will be decreasing that the channel will turn on easily because electron charge fill the grain boundary sites. The thinner tunnel oxide sample (t=9nm) has more Vt shift during drain bias stressing (Vg=12V) also can demonstrate the grain boundaries issues. Therefore, to eliminate the traps along the grain boundaries in the channel is another key for achieving better performance.

Figure 4.14 shows the read disturb induced erase-state threshold voltage instability in a Hf silicate TFT Flash memory cell for 10k P/E cycled samples. To allow for two-bit operation, the applied bitline voltage in reverse-read scheme must be sufficiently large (>1V) for being able to “read-through” the trapped charge in the neighboring bit. Relatively large read bitline voltage may cause unwanted electron injection and then result in a significant threshold voltage shift of the neighboring bit.

For the TFT memory, such low drain voltage (Vd=1V) can be used for the 2-bit operation because that the depletion region induced in the un-doped poly-Si body is considerably wide, which is able to mask the effect of the stored charge. For our measurement, the gate and drain biases were applied and the source was ground. The

For the TFT memory, such low drain voltage (Vd=1V) can be used for the 2-bit operation because that the depletion region induced in the un-doped poly-Si body is considerably wide, which is able to mask the effect of the stored charge. For our measurement, the gate and drain biases were applied and the source was ground. The

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