As discussed in the previous section, the challenge inherent is associated with the rapid scaling of the gate dielectric thickness, Td for high-performance and low-power logic technologies. The first difficulty is a susceptibility to boron penetration, which is the uncontrolled diffusion of boron from the heavily doped p+ poly gate of the pMOSFETs through the thin gate dielectric and into the MOSFET channel. The result is an uncontrollable but positive shift in the pMOSFET Vt. Lightly doping the gate oxide with nitrogen to form oxy-nitride generally controls this problem [18] and is the standard approach for current
leading-edge IC technologies. The other major difficulty is excessive gate leakage current, as the oxy-nitride becomes very thin with scaling. The predominant conduction mode for very thin dielectrics is direct tunneling, where the gate leakage current increases exponentially with decreasing dielectric thickness. In Figure 1.1 [2], the 2003 ITRS projections for EOT and Jg, limit are plotted for low-standby-power (LSTP) logic. Also plotted are simulations of the expected gate leakage current density assuming the gate dielectric is oxy-nitride. As indicated in the figure, by 2006 oxy-nitride is incapable of satisfying the limit (Jg, limit) on gate leakage current density. Carrying out a similar analysis for low-operating-power (LOP) and high-performance logic, oxy-nitride is incapable of satisfying the limit on gate leakage current density by 2006 for LOP logic also, and by 2007 for high-performance logic [2].
In 2006 or 2007, when oxy-nitride gate dielectric becomes incapable of meeting the maximum gate leakage limit, the preferred approach to reducing gate leakage in order to satisfy the limit is to replace the oxy-nitride with a “high-κ” dielectric. Such a dielectric has a significantly higher relative dielectric constant k than the kox = 3.9 value of silicon dioxide (the k for lightly nitrogen doped oxy-nitride is also close to 3.9). For a dielectric of thickness Td, the equivalent oxide thickness, EOT, is:
EOT = Td / (k / kox) = Td / (k / 3.9). (1.1)
To first order, a transistor with such a gate dielectric has a gate capacitance per unit area,
Cg, area = kε0 / Td = koxε0 / EOT, (1.2)
where ε0 is the dielectric constant of vacuum. koxε0/EOT is also the value of the gate capacitance per unit area for an otherwise identical transistor with a silicon dioxide gate dielectric of thickness EOT. Hence, to first order, the major electrical characteristics such as
Ion should be the same for both transistors (except the gate leakage current, which should be significantly reduced for the transistor with high-κ gate dielectric). For silicon dioxide, with k
= 3.9, EOT = Td, while for high-κ gate dielectric, where k > 3.9, Td is significantly larger than EOT. Since direct tunneling is strongly dependent on Td, the gate leakage current density will generally be significantly smaller for the high-κ gate dielectric, if the energy barrier between the dielectric and silicon is large enough [19]. Extending current approaches using lightly nitrogen-doped oxy-nitride with k ~ 3.9, heavily nitrogen doped oxy-nitride has been shown to have k > 5, and as a result, gate leakage current reduced by more than an order of magnitude relative to silicon dioxide [20]. In simulating the gate leakage of oxy-nitride dielectric, as in Figure 1.1, such extended, heavily nitrogen doped oxy-nitride is assumed. Per the analysis above, high-κ gate dielectric is projected to be needed for low-power logic in 2006 and for high-performance logic in 2007. Very active research and development is being carried out on high-κ materials for the gate dielectric, and the current leading candidates are hafnium oxide, hafnium silicate, and hafnium oxy-nitride [21].
Another major front-end issue is polysilicon depletion in the gate electrode. When gate voltage is applied to turn on a MOSFET, a depletion region of thickness Wd forms adjacent to the polysilicon-oxide interface (see Figure 1.2). This depletion region increases the effective electrical thickness of the gate dielectric in inversion, EOTelec:
EOTelec = EOT + ∆poly = EOT + (kox / kSi)Wd ~ EOT + Wd / 3, (1.3)
where kSi = 11.9 is the relative dielectric constant of silicon and ∆poly encapsulates the impact of polysilicon depletion. According to Wilk et al. [19], ∆poly can be as much as 0.4 nm. As a result of the polysilicon depletion, EOT is replaced by EOTelec in (1.2) for the gate capacitance per unit area, reducing the capacitance. Consequently, for any given gate voltage, the inversion layer charge and Ion are reduced. The impact of polysilicon depletion becomes more
severe with the smaller EOT in succeeding technology generations. Increased doping of the polysilicon reduces the depletion, since Wd is inversely proportional to the square root of the polysilicon doping. However, with the limited solubility of the dopants, particularly boron for the p+ polysilicon gate of the pMOSFET, this solution will eventually become inadequate, even if germanium-doped polysilicon, which has higher solid solubility for boron, is used [22].
The preferred solution is metal-gate electrodes, since with metal gates there is virtually no depletion, no boron penetration, and sheet resistance is very low. According to 2003 ITRS projections, metal-gate electrodes will need to be implemented for high-performance logic by 2007 [2]. However, CMOS optimization requires a work function ~ 5.0 eV (near the silicon valence band edge) for pMOSFETs and ~ 4.1 eV (near the silicon conduction band edge) for nMOSFETs [23] to set the desired symmetric threshold voltages of 0.2 to 0.5 V for NMOS and −0.2 to −0.5 V for PMOS. One approach involves utilizing different metals with different work functions, one for the pMOSFET [24], [25], and one for the nMOSFET [26], [27]
device. This would present difficult process integration problems and would tend to increase the chip processing complexity and cost. An alternative approach that aims to reduce the process complexity and cost is to utilize one material system for both metal electrodes, and use doping or alloy composition to vary the work function as necessary [25], [28].