The gate oxide has been aggressively scaled in recent generations. Figure 2.3 shows extrapolated gate oxide scaling targets based on published data from recent Intel technologies [30]. The technology node refers to the smallest poly-Si gate length which can be defined by photolithography and roughly corresponds to the minimum channel length for a given process technology. A more complete list of projected transistor parameters is given in Table 2.1. The predictions are based on extrapolations of published state-of-the-art 180 nm technologies assuming channel length, supply voltage, and gate oxide thickness scaling factors of 0.7, 0.8, and 0.8, respectively [31]-[33]. These projections, representative of the current targets for high-performance logic technology, aggressively outpace those compiled in the 2000 update of the International Technology Roadmap for Semiconductors (ITRS). However, these data have been included and revised in the 2004 update of the ITRS, as shown in Table 2.2.
The two data sets in Figure 2.3 refer to the equivalent electrical and physical thickness of the gate oxide. The equivalent oxide thickness (EOT) refers to how thin a pure SiO2 layer would need to be in order to meet the gate capacitance requirements of a given technology. In a modern MOSFET device, the gate oxide behaves electrically as if it were 0.8−1.0 nm thicker than its physical thickness, because depletion in the poly-Si gate and quantization in the inversion layer each extend the centroids of charge modulated by the gate voltage by 0.4−0.5 nm [34].
2.2.1 Gate Leakage and Static Power Dissipation
A significant consequence of aggressively scaling the gate oxide is the resulting direct tunneling of carriers through the potential barrier presented by the insulator layer. As illustrated in Figure 2.2(b), when the thickness of the potential barrier becomes less than approximately 3.0 nm, substantial tunneling currents can flow through the gate oxide, leading to large static power dissipation. In addition, the gate and channel regions are no longer isolated from each other when tunneling occurs. Recent studies have shown that gate leakage can significantly impact circuit performance as a consequence, especially for analog and dynamic logic circuits.
Figure 2.4 shows extrapolated trends in power dissipation for high-performance CMOS logic based on published data from recent Intel technologies [30], [35]. Both active and static power components are shown. Traditionally, the main source of power dissipation in CMOS circuits has been active switching, which depends on the rate at which node capacitances are charged and discharged,
. (2.4)
f NCV
Pactive = 2
N is the number of switching transistors, C is the total switched capacitance, V is the supply voltage, and f is the frequency of operation. The observed increase in active power with each generation reflects the trend towards higher levels of integration and higher frequency of operation, which more than offsets the reduction in device capacitance and supply voltage.
Much more alarming is the rapid increase in static (i.e. standby) power dissipation beyond the 180 nm technology node. Static power is primarily due to subthreshold (Ioff) and gate (Igate) leakage currents. The extrapolation of the Igate component is based on quantum mechanical modeling of gate tunneling currents through ultrathin SiO2 layers by Lo et al. [34], [36]. As shown in Figure 2.4, standby power has been increasing much more rapidly than active power
in recent generations, and if current trends continue, standby power will actually surpass active power beyond the 65 nm generation. Clearly, the exponential increase in the gate leakage, which arises from direct tunneling of carriers through the gate oxide, presents a serious limit to future CMOS scaling.
2.2.2 Scaling Limit of SiO2
In addition to limitations arising from static power dissipation, there has recently been great interest in determining if a more fundamental limit to scaling SiO2 exists. One of the most convincing experiments which demonstrated that such a fundamental limit indeed exists is the work of Muller et al. from Bell Labs [37], [38]. Using a scanning transmission electron microscope (STEM) probe with 0.2 nm resolution, they studied the chemical composition and electronic structure of oxide layers as thin as 0.7−1.2 nm through detailed electron-energy- loss spectroscopy (EELS) measurements. By moving the probe site-by-site through the ultrathin SiO2 layers, they mapped the local unoccupied density of electronic states, which provides insight into the local energy gap of the material, as a function of the probe position.
In their work, the local energy gap was given by the separation between the highest occupied and lowest unoccupied states. They found that three to four monolayers of SiO2 were needed to ensure that at least one monolayer maintained a fully bulk-like bonding environment, giving rise to the wide, insulating bandgap of SiO2. Since the first and last monolayers form interfaces with Si and poly-Si respectively, they have bonding arrangements intermediate to those of bulk Si and bulk SiO2 and hence have energy gaps smaller than that of bulk SiO2. Based on these insights, Muller et al. concluded that the fundamental scaling limit of SiO2 is likely to be in the range of 0.7 to 1.2 nm. Another important insight from their study was that for a 1.0 nm oxide, a 0.1 nm increase in the root-mean-square (RMS) interface roughness can
lead to a factor of 10 increase in the gate leakage current, showing that the growth of such thin layers must be precisely controlled on atomic scales.
There has been remarkable agreement between experiment and theory regarding the scaling limit of SiO2. Theoretical studies by Tang et al. employing a Si/SiO2 interface model based on the β-cristobalite form of SiO2 showed that the band offset at the interface degraded substantially when the SiO2 layer was scaled to less than three monolayers [39]. The large reduction in the band offset was attributed to a reduction in the SiO2 bandgap and also suggested 0.7 nm as the scaling limit of SiO2. A more recent study by Kaneta et al. using a Si/SiO2 interface model based on β-quartz SiO2 directly computed the local energy gap as a function of position through the interface [40]. While the transition from bulk Si to bulk SiO2 in their model was structurally abrupt, it was found that the full bandgap of SiO2 was not obtained until the second monolayer of SiO2 was reached. Again, these calculations suggest that approximately 0.7 nm of SiO2 is the minimum required for substantial band offsets to develop at the interface, indicating the formation of a large bandgap.
Thus, both experiment and theory suggest that the bulk properties of SiO2, including the wide, insulating bandgap needed to isolate the gate and channel regions, cannot be obtained for films less than 0.7 nm thick. Since technology roadmaps predict the need for sub-0.6 nm gate oxides in future generations, it is unlikely that SiO2 will scale beyond the 70 nm generation, both from static power dissipation and fundamental materials science points of view.