5.5 HfO 2 MIS Capacitor with Copper Gate Electrode
5.5.4 Constant Current Stress and Charge-to-Breakdown
Figure 5.15 shows the typical I-V curves of HfO2 and SiO2 MIS capacitors. Obviously, the breakdown voltage for the SiO2 capacitor is nearly three times larger than that of the HfO2
capacitor. Figure 5.16 shows the gate voltage variation as a function of time for the SiO2 and HfO2 capacitors with different gate electrodes, when subjected to CCS. The stressing current used was −1 mA/cm2. The reason why we used such low current density for stressing is owing to the fact that the QBD is extremely hard to be monitored under the condition of −100 mA/cm2 for the Cu/SiO2/Si capacitors when Cu was incorporated. In the case of SiO2
capacitors, a larger voltage shift observed in the Cu-gate capacitor, compared to the Al-gate counterpart, implies the incorporation of Cu ions into SiO2 dielectric during BTS test does result in higher electron trapping rate. By contrast, different metal gates (i.e., Al and Cu) only lead to indiscernible change in gate voltage shift during CCS for the HfO2-based capacitors.
These results suggest that the SiO2 dielectric is more vulnerable than HfO2 to Cu diffusion. As a result, the SiO2 capacitors will breakdown more easily when Cu is employed as the gate electrode. Noticeably, the gate voltage variation curve for the HfO2 capacitor as a function of stressing time is very rough in nature, as shown in Figure 5.17(a). This behaves totally different from the smooth curve for the SiO2 capacitor, as shown in Figure 5.17(b). The charging-discharging effect is implied to take place anytime for the HfO2 capacitors, even when the initial stage of the CCS. Figure 5.18 shows the Weibull distributions of the charge-to-breakdown (QBD) for all four capacitor configurations. Consistent with the results in Figure 5.16, the value of 63% QBD for the Cu-gate SiO2 capacitors is more than one order of magnitude lower than that for the Al-gate SiO2 capacitors. This severe reliability degradation is the main reason why Cu is excluded from the conventional FEOL processes of silicon-based ULSI manufacturing. However, our finding strongly indicates that this is no longer an issue for the HfO2 dielectric. From the cumulative QBD plots of HfO2 capacitors with the Cu and Al gate electrodes, no significant difference is observed between the two groups, indicating that Cu diffusion has only negligible effects on the reliability of
HfO2-based capacitors. No degradation was observed even though 4-nm-thick HfO2 was used in Cu/HfO2/Si capacitor, as shown in Figure 5.18 [129]. Moreover, the mechanism is mainly soft breakdown in such HfO2 film. It is notable here that flatband voltage shifts were taken place for some of the samples using n-type Si. The reason is unknown so far.
5.6 Conclusions
Hafnium oxide film was evaluated as possible candidate material to replace SiO2 for gate dielectric in complementary metal-oxide-semiconductor technology. Both sputtering and MOCVD methods can be used as the tool of thin-film HfO2 deposition. In view of the film uniformity and interfacial layer growth, however, sputtering maybe not sufficient to be a production tool in the future.
AVD-deposited HfO2 capacitors using Cu and Al as the gate electrode have been fabricated and investigated for the first time. The counterparts with thermally grown SiO2
dielectric were also constructed for comparison. Our results clearly show that HfO2 dielectric depicts superior resistance against Cu diffusion after BTS test, compared to SiO2. Moreover, the presence of Cu metal in direct contact with HfO2 has negligible impact on the reliability of the HfO2 capacitor. The fact that HfO2 can behave as a good barrier against Cu diffusion is attributed to its considerably high density. This finding is important as it suggests the feasibility of a Cu integration process from the p-channel gate electrode to BEOL interconnect, which will allow the use of the gate electrode as the first-level metal simultaneously, resulting in a simplified process.
Time (sec)
150 300 450 600 750 900
Thickness (nm)
0 2 4 6 8 10 12 14 16
18 as-deposited
O2: 800
oC, 30 sec Linear Regression N2: 800
oC, 30 sec
Fig. 5.1 Thickness of HfO2 film as a function of deposition time before and after O2
and N2 ambient annealing.
4.5 nm
Poly-Si
Si
(a)
4.5 nm
Poly-Si
Si
(b)
Fig. 5.2 TEM picture of HfO2 film deposited by PVD (a) with the power of 100 W for 300 sec, (b) with higher resolution. The PDA condition is 800°C in O2 ambient for 30 sec.
Si
(a)
3.4 nm HfO
2SiO
2Si
(b)
Fig. 5.3 (a) TEM picture of Pt/HfO2/Si deposited by PVD. (b) TEM picture of Pt/HfO2/Si deposited by PVD with higher resolution.
Wavelength (nm)
200 400 600 800
Reflectance
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
4.5 nm 6.3 nm 12.5 nm 13.6 nm 14.1 nm
thickness ↑
Fig. 5.4 Reflectance spectra of thin HfO2 films on Si.
Binding Energy (eV)
6 8 10 12 14 16 18 20 22 24
KCounts
0 20 40 60 80 100 120 140
Hf 4f
(a)
Binding Energy (eV)
10 12 14 16 18 20 22 24 26 28 30
Intens ity (a .u.)
Hf 4f
as-deposited: 100 W, 600 sec PDA: O2 30 sec
900oC 800oC 700oC 600oC as-deposited
(b)
Fig. 5.5 (a) XPS spectrum shows a typical HfO2 chemical bonding. (b) XPS spectra show HfO2 chemical bonding after elevated temperature annealing.
Fig. 5.6 AFM image of HfO2 on p-Si, the RMS roughness is about 0.14 nm.
Voltage (V)
-3 -2 -1 0 1 2 3
Capacitance (pF)
0 100 200 300 400 500 600
1 MHz 100 kHz 10 kHz
100 W, 300 secRTA: O2, 30 sec Gate Electrode: Pt Area: 4.5E-4 cm2 EOT@100 KHz: 30 A
Fig. 5.7 C-V curves of a thin-film HfO2 capacitor with Pt electrode on n-Si substrate.
Al Pt HfO
2n-type Si substrate
Fig. 5.8 Schematic representation of an HfO2 capacitor with Pt electrode on n-Si substrate.
Voltage (V)
Fig. 5.9 100 kHz curves of both positive and negative C-V sweeps. The hysteresis is less than 110 mV.
Cu / SiO
2 Al/HfO2/Si capacitors before and after BTS at 150°C for 1000 sec. The applied field was +1 MV/cm.Gate Bias (V)
Fig. 5.12 (a) Typical I-V curves of Cu/HfO2/Si capacitors before and after BTS at 150°C for 1000 sec. (b) Typical gate current and substrate current variation curves of Cu/HfO2/Si capacitors during BTS. The applied field was +1 MV/cm.
Cu / HfO2 / Si
Fig. 5.13 Typical C-V curves of Cu/HfO2/Si capacitors at frequencies varies from 1 kHz to 1 MHz.
Temperature (
oC)
100 125 150 175 200
Flatband Voltage Shift (V)
after BTS test at +1 MV/cm for 1000 sec. The temperatures were varied from 100 to 200°C.Gate Bias (V)
Gate Voltage Shift, ∆ V
G(V) 0.0
Fig. 5.16 Gate voltage variation of SiO2 and HfO2 capacitors with Cu and Al gate electrodes subjected to CCS as a function of time.
Cu / HfO2 / Si
Stress Time (sec)
0 500 1000 1500 2000
Voltage (V)
2 3 4 5
(a)
Cu / SiO2 / Si
Stress Time (sec)
0 100 200 300 400
Voltage (V)
0 2 4 6 8 10 12 14 16
(b)
Fig. 5.17 Gate voltage variation of (a) HfO2 and (b) SiO2 capacitors with Cu gate electrodes subjected to CCS as a function of time.
Charge to Breakdown, Q
BD(C/cm
2) 10
-210
-110
010
110
210
310
610
710
8Weibull Ln(-Ln(1-F))
-4 -3 -2 -1 0 1 2
Cu/SiO2 (10nm) Al/SiO2 (10nm) Cu/HfO2 (10nm) Al/HfO2 (10nm) Cu/HfO2 (4nm)
Fig. 5.18 Cumulative QBD plots of Cu/HfO2/Si, Al/HfO2/Si, Cu/SiO2/Si, and Al/SiO2/Si capacitors.
Chapter 6
Investigation of HfO
2Dielectrics for Inter-Poly Dielectrics and Metal-Insulator-Metal Capacitors
6.1 Introduction
It is well known that the capacitance of a parallel-plate capacitor is normally a function of the area of the electrode, the dielectric constant of the dielectric, and the thickness of the dielectric. Both top electrode and bottom electrode of the capacitor under consideration are assumed to be metallic conductors with high conductance. However, if one of the electrodes is n+/p+ polysilicon, a depletion region extending into the polysilicon is formed at the polysilicon/dielectric interface, thereby rendering the capacitance of such a structure somewhat lower than that if both electrodes had been metallic. In recent years, the inter-poly dielectrics (IPDs) and metal-insulator-metal (MIM) capacitors in next-generation nonvolatile memories (NVMs) and silicon radio-frequency (RF) applications have attracted great attention. The scaling down of IPDs is important with a large gate coupling coefficient, small cell size, and low programming voltage [130]. For MIM capacitors, the advantages are high conductive electrodes and low parasitic capacitance compared to IPDs [131].
In recent years, the dramatic increase in wired and wireless communications has demanded the need for high quality passives for analog and mixed signal applications. MIM capacitors using one of the standard back-end metal layers as bottom electrode have emerged as key passive components for microprocessors, high frequency circuits, and mixed-signal
integrated circuits applications [132], [133]. Compared with double poly linear capacitors, they offer the advantages of reduced series resistance and lower parasitic capacitance [134]. A high capacitance density is important for a MIM capacitor to increase the circuit density and reduce the cell area and cost. Therefore, adoption of high-k material like Al O or HfO is a very efficient way to increase the capacitance density [135].
2 3 2
Silicon oxide and silicon nitride are dielectrics that are commonly used in conventional capacitors, but their capacitance densities are limited due to low dielectric constants. It is expected to be one solution to enhance the capacitance density by using higher dielectric constant materials. Among various high-k dielectric candidates, HfO2 has been investigated as a promising material in gate dielectric of MOSFETs due to its high dielectric constant, excellent thermal stability, and high band gap. [136]. In addition, excellent MOS capacitors with HfO2 have also been demonstrated [137]. Therefore, it seems that HfO2 is a promising candidate for the above applications. In this work, MIM capacitors with HfO dielectrics have been fabricated and investigated. Experimental results show low leakage current of ~5×10 A/cm and high capacitance density of ~3.4 fF/µm at 100 kHz in the MIM capacitors. The temperature coefficient and frequency dispersion effect for these MIM capacitors were very small.
Different metal electrodes like tantalum, aluminum, and copper were also investigated and compared. Finally, the mechanism of electrical transport was extracted for the HfO MIM capacitors.
6.2 Experimental Procedure
Standard 6-in (150-mm) Si wafers, with a resistivity of 15-25 Ω-cm, were used in this study. An additional 500-nm thermal SiO2 was grown on the Si substrate to increase the substrate isolation. The IPDs and MIM capacitors with HfO2 films were subsequently formed
on the 500-nm SiO2. Before high-k dielectrics deposition, a layer of 200-nm-thick low-pressure-chemical-vapor-deposition (LPCVD) polysilicon was deposited and doped as the bottom electrode of the IPDs. HfO2 films (20-nm) were then prepared by metal-organic-chemical-vapor-deposition (MOCVD) at 345°C. After that, a layer of 200-nm-thick LPCVD polysilicon was deposited and doped as the top electrode. A photolithography step and dry etching were subsequently conducted to define the IPDs.
Finally, rapid thermal annealing (RTA) was performed at 600°C in N2 ambient for 30 sec. For the case of MIM capacitors fabrication, a layer of 100-nm-thick HfN film was deposited on SiO2 as the bottom electrode. Following that, HfO2 film (20-nm) and TiN film were deposited and patterned in sequence. All these processes are performed at room temperature.
In the second part of this work, on the other hand, the procedure was described as follow.
After an additional 500-nm thermal SiO2 was grown on the Si substrate to increase the substrate isolation. The MIM capacitors with HfO2 films were subsequently formed on the 500-nm SiO2. Before high-k dielectrics deposition, a layer of Ta film was deposited by sputtering on SiO2 as the bottom electrode. HfO2 films (50-nm) were then prepared by sputtering in O2 ambient. After that, a layer of Ta film was deposited as the top electrode. The pattern of the MIM capacitors was defined using a metal mask. The counterparts of the MIM capacitors with Al and Cu metals as the top electrodes were also fabricated for comparison.
Finally, furnace annealing was conducted at 400°C in N2 ambient for 30 min.
The leakage current was measured using a Keithley Model 4200-SCS Semiconductor Characterization System, and the capacitance was measured using an Agilent 4284A precision LCR meter at frequencies varied from 1 kHz to 1 MHz. In order to investigate the thermal stability of the high-k dielectric film, thermal stresses were performed with measurement temperatures varied from 25°C to 125°C.