This thesis investigates promising candidates of alternative gate dielectrics containing nitrided oxide and hafnium oxide.
The thesis is organized as follows:
Chapter 2 reviews recent trends in gate oxide scaling to show that further scaling of SiO2
is limited by static power dissipation and other fundamental considerations. As an alternative to continuing to scale SiO2, the use of alternative high-k gate dielectrics is discussed. Several of the most important material properties for such high-k dielectrics are also reviewed.
Chapter 3 investigates the hot carrier injection reliability of nMOSFET’s with ultrathin plasma nitrided gate oxide. The devices with plasma nitrided oxide suffer more trans- conductance reduction and threshold voltage shift. The degradation is direct proportional to the plasma nitridation time. We report, for the first time, an enhanced degradation under negative substrate bias in nMOSFETs with ultrathin plasma nitrided gate dielectric. The enhanced degradation is attributed to the introduction of paramagnetic electron trap precursors during plasma nitridation.
Chapter 4 investigates the hot carrier injection reliability and negative bias temperature instability of pMOSFET’s with ultrathin plasma nitrided gate oxide. For channel hot-carrier stressing, the most efficient stressing condition is located corresponding to the region of maximum gate current. The negative threshold voltage shift indicates a positive charge build-up in the gate dielectric. For negative bias temperature stressing, appreciable enhancement of the threshold voltage shift can be observed through the raising of temperature.
The enhanced device degradation is attributed to the H-related species and the interface trap generated during NBT stressing. NBTI is an important issue for pMOSFETs from the reliability point of view.
Chapter 5 presents the hafnium oxide film as alternative material to replace SiO2 for gate dielectric in complementary metal-oxide-semiconductor technology. AVDTM-deposited HfO2
capacitors using Cu and Al as the gate electrode have been fabricated and investigated for the first time. Our results clearly show that HfO2 dielectric depicts superior resistance against Cu
diffusion after BTS test, compared to SiO2. Moreover, the presence of Cu metal in direct contact with HfO2 has negligible impact on the reliability of the HfO2 capacitor. The fact that HfO2 can behave as a good barrier against Cu diffusion is attributed to its considerably high density. This finding is important as it suggests the feasibility of a Cu integration process from the gate electrode to BEOL interconnect.
Chapter 6 investigates HfO2 MIM capacitors with different metal electrodes. The MIM capacitor with Al top electrode exhibits the lowest capacitance density, while that with Cu top electrode exhibits the highest capacitance value. Due to the Al2O3 layer formed between Al and HfO2, the capacitance density and the leakage current density were reduced. On the other hand, the successful fabrication of the Cu top electrode capacitor implies the possibility of integrating Cu with HfO2 dielectrics.
Chapter 7 describes the conclusions of the thesis and the suggestions for future work.
Fig. 1.1 LSTP logic scaling-up of gate leakage current density limit and of simulated gate leakage due to direct tunneling. [ITRS 2003]
Fig. 1.2 Polysilicon depletion effects
Chapter 2
Trends in Gate Oxide Scaling
2.1 MOSFET Scaling
Recall that a MOSFET ideally acts as a three-terminal switch, either connecting or isolating the drain (D) and source (S) terminals based on the voltage applied to the controlling gate (G) terminal, as illustrated in Figure 2.1(a). In practice, this switching action is achieved through the use of a gate capacitor, as illustrated in Figure 2.1(b). Depending on the polarity of the voltage applied to the gate terminal, either positive or negative charge is induced in the channel region along the bottom plate of the gate capacitor. The channel charge either connects or isolates the drain and source nodes depending on the type of carrier contained in those regions.
The operation of the MOSFET depends critically on several properties of the gate dielectric material, SiO2. The wide insulating bandgap (Eg) of SiO2 electrically isolates charges in the gate and channel regions, so that the controlling gate terminal does not interfere with the flow of current in the channel region, as illustrated in Figure 2.2(a). Also, the interface between SiO2 and the underlying Si substrate is electrically of very high quality, allowing electric field lines originating at the gate electrode to penetrate into the channel region to accumulate or invert the surface charge. Prior to the development of the Si/SiO2 system, attempts to realize a field-effect transistor (FET) were hampered by the abundance of electrically active defects at the dielectric/semiconductor interface.
The amount of charge (Q) induced in the channel region is given by the product of the gate oxide capacitance per unit area (Cox) and the voltage drop across the gate capacitor (V),
V C
Q= ox . (2.1)
Since Cox can be modeled as a parallel-plate capacitor, its value is given by
ox ox
ox t
C k ε0
= , (2.2)
where kox is the relative dielectric constant, ε0 is the permittivity of free space, and tox is the physical thickness of the dielectric material. Based on these relations, the drain-source current for a long-channel MOSFET operating in the saturation region can be expressed as
)2
where µ is the channel mobility, W and L are the width and length of the channel region, respectively, Vgs is the gate-source potential, and Vt is the threshold voltage. Equations 2.2 and 2.3 reveal that reducing the lateral (L) and vertical (tox) dimensions of the device increases the current flow between the drain and source. Intuitively, this is because reducing toxincreases Cox and hence the amount of channel charge, and reducing L decreases the distance the channel charge must travel to conduct a current. Reducing the gate oxide thickness (tox) along with the channel length (L) also helps to maintain the gate electrode’s control over short channel effects. Increased gate capacitance allows the gate potential to modulate more channel charge and is especially important as the supply voltage scales down. Much of the progress in Si microelectronics has been driven by the ability to continually shrink these and other critical dimensions of the MOSFET to increase performance and decrease die area, a process referred to as scaling [29].