• 沒有找到結果。

In the study of high-k gate dielectrics related to hafnium oxide, the superior resistance against Cu diffusion after BTS test is observed. The presence of Cu metal in direct contact with HfO2 has negligible impact on the reliability of the HfO2 capacitor. However, the transistor has not been processed yet. The next step of this study is the achievement of the MOSFET fabrication, followed with the device characterization and verification of the findings in previous work.

The MIM capacitors with HfO2 gate dielectric have been studied. The behavior of the capacitors related to different metal electrodes exhibits somehow slightly variations. Although such difference can be roughly imagined from the interface formed on the dielectric, the mechanism behind is still not understood. Further experiments and analyses are required to clarify the interaction between the metal electrode and the dielectric, especially for the Cu metal that connecting to the MIM capacitors in the BEOL.

References

[1] G.E. Moore, “Lithography and the future of Moore’s Law,” in Proc. Eighth Optical/Microlithography Conf., SPIE, Feb. 1995, vol. 2440, pp. 2–17.

[2] Semiconductor Industry Association (SIA), International Technology Roadmap for Semiconductors 2003 ed., Austin, TX: SEMATECH, 2003 [Online]. Available:

http://public.itrs.net

[3] P.M. Zeitzoff and J.E. Chung, “Weighing in on logic scaling trends,” IEEE Circuits Devices Mag., vol. 18, pp. 18–27, Mar. 2002.

[4] Y. Taur and T.H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.:

Cambridge Univ. Press, 1998.

[5] C. Hu, “Gate oxide scaling limits and projection,” in IEDM Tech. Dig., 1996, pp.

319–322.

[6] H.S. Momose, M. Ono, T. Yoshitomi, T. Ohguro, S. Nakamura, M. Saito, and H. Iwai,

“Tunneling gate oxide approach to ultra-high current drive in small-geometry MOSFETs,” in IEDM Tech. Dig., 1994, pp. 593–596.

[7] T. Matsuoka, S. Kakimoto, M. Nakano, H. Kotaki, S. Hayashida, K. Sugimoto, K.

Adachi, S. Morichita, K. Uda, Y. Sato, M. Yamanaka, T. Ougura, and J. Takagi, “Direct tunneling N2O gate oxynitrides for low-voltage operation of dual gate CMOSFETs,” in IEDM Tech. Dig., 1995, pp. 851–854.

[8] T. Kuroi, S. Shimizu, S. Ogino, A. Teramoto, M. Shirahata, Y. Okumura, M. Inuishi,

and H. Miyoshi, “Sub-quarter-micron dual gate CMOSFETs with ultra-thin gate oxide of 2 nm,” in VLSI Symp. Dig. Tech. Papers, 1996, pp. 210–211.

[9] B.E. Weir, P.J. Silverman, D. Monroe, K.S. Krisch, M.A. Alam, G.B. Alers, T.W. Sorsch, G.L. Timp, F. Baumann, C.T. Liu, Y. Ma, and D. Huang, “Ultra-thin gate dielectrics:

They breakdown, but do they fail?,” in IEDM Tech. Dig., 1997, pp. 73–76.

[10] G. Timp, A. Agarwal, F.H. Baumann, T. Boone, M. Buonanno, R. Cirelli, V. Donnelly, M. Foad, D. Grant, M. Green, H. Gossmann, S. Hillenius, J. Jackson, D. Jacobson, R.

Kleiman, A. Komblit, F. Klemens, J.T.-C. Lee, W. Mansfield, S. Moccio, A. Murrell, M.

O’Malley, J. Rosamilia, J. Sapjeta, P. Silverman, T. Sorsch, W.W. Tai, D. Tennant, H.

Vuong, and B. Weir, “Low leakage, ultra-thin gate oxides for extremely high performance sub-100 nm nMOSFETs,” in IEDM Tech. Dig., 1997, pp. 930–932.

[11] Q. Xiang, G. Yeap, D. Bang, M. Song, K. Ahmed, E. Ibok, and M. R. Lin,

“Performance and reliability of sub-100 nm MOSFETs with ultra thin direct tunneling gate oxides,” in VLSI Symp. Dig. Tech. Papers, 1998, pp. 160–161.

[12] T. Sorsch, W. Timp, F.H. Baumann, K.H.A. Bogart, T. Boone, V.M. Donnelly, M.

Green, K. Evans-Lutterodt, C.Y. Kim, S. Moccio, J. Rosamilia, J. Sapjeta, P.

Silvermann, B. Weir, and G. Timp, “Ultra-thin, 1.0-3.0 nm, gate oxides for high performance sub-100 nm technology,” in VLSI Symp. Dig. Tech. Papers, 1998, pp.

222–223.

[13] H.S. Momose, R. Fujimoto, S. Otaka, E. Morifuji, T. Yoshitomi, T. Ohguro, M. Saito, T.

Morimoto, Y. Katsumata, and H. Iwai, “RF noise in 1.5 nm gate oxide MOSFETs and the evaluation of the NMOS LNA circuit integrated on a chip,” in VLSI Symp. Dig.

Tech. Papers, 1998, pp. 96–97.

[14] H.S. Momose, E. Morifuji, T. Yoshitomi, T. Ohguro, M. Saito, T. Morimoto, Y.

Katsumata, and H. Iwai, “High frequency AC characteristics of 1.5 nm gate oxide MOSFETs,” in IEDM Tech. Dig., 1996, pp. 105–108.

[15] C.H.J. Wann and C. Hu, “High endurance ultra-thin tunnel oxide for dynamic memory application,” in IEDM Tech. Dig., 1995, pp. 867–870.

[16] S.H. Lo, D.A. Buchanan, Y. Taur, L.K. Han, and E. Wu, “Modeling and characterization of n+- and p+- polysilicon-gate ultra-thin oxides (21-26A),” in VLSI Symp. Dig. Tech. Papers, 1997, pp. 149–150.

[17] S.J. Wang, I.C. Chen, and H.L. Tigelaar, “Effects of poly depletion on the estimate of thin dielectric lifetime,” IEEE Electron Device Lett., vol. 12, pp. 617–619, Nov. 1991.

[18] B. Maiti, P.J. Tobin, V. Misra, R.I. Hegde, K.G. Reid, and C. Gelatos, “High Performance 20 Å NO oxynitride for gate deielectric in deep sub-quarter microcon CMOS technology,” in IEDM Tech. Dig., 1997, pp. 651– 654.

[19] G.D. Wilk, R.M. Wallace, and J.M. Anthony, “High-κ gate dielectrics: Current status and material properties considerations,” J. Appl. Phys., vol. 89, pp. 5243–5275, May 2001.

[20] X. Guo and T.P. Ma, “Tunneling leakage current in oxynitride: Dependence on oxygen/nitrogen content,” IEEE Elec. Dev. Lett., vol. 19, pp. 207–209, June 1998.

[21] K. Onishi, C.S. Kang, R. Choi, H.-J. Cho, S. Gopalan, R. Nieh, E. Dhamarajan, and C.

Lee, “Reliability characteristics, including NBTI, of polysilicon gate HfO2

MOSFET’s,” in IEDM Tech. Dig., 2001, pp. 659–662.

[22] S. Gannavaram and M.C. Öztürk, “Ultra-shallow P+-N junctions for 35–70 nm CMOS using selectively deposited very heavily boron-doped silicon-germanium films,” in Rapid Thermal and Other Short-Time Processing Technologies II, Eds. ECS PV 00-09, pp. 73–82, 2000.

[23] H. Zhong, S.-N. Hong, Y.-S. Suh, H. Lazar, G. Heuss, and V. Misra, “Properties of Ru-Ta alloys as gate electrodes for NMOS and PMOS silicon devices,” in IEDM Tech.

Dig., 2001, pp. 467–470.

[24] Y.H. Kim, C.H. Lee, T.S. Jeon, W.P. Bai, C.H. Choi, S.J. Lee, L. Xinjian, R. Clarks, D.

Roberts, and D.L. Kwong, “High quality CVD TaN gate electrode for sub-100 nm MOS devices,” in IEDM Tech. Dig., 2001, pp. 667–670.

[25] H. Zhong, G. Heuss, V. Misra, H. Luan, C.H. Lee, and D.L. Kwong, “Characterization of RuO2 electrode on Zr silicate and ZrO2 dielectrics,” Appl. Phys. Lett., vol. 78, pp.

1134–1136, 2001.

[26] Y.-S. Suh, G. Heuss, H. Zhong, S.-N. Hong, and V. Misra, “Electrical characteristics of TaSixNy gate electrodes for dual gate Si_CMOS devices,” in VLSI Symp. Dig. Tech.

Papers, 2001, pp. 47–48.

[27] D.-G. Park, K.-Y. Lim, H.-J. Cho, T.-H. Cha, J.-J. Kim, J.-K. Ko, I.-S. Yeo, and J.W.

Park, “Novel damage-free direct metal gate process using atomic layer deposition,” in VLSI Symp. Dig. Tech. Papers, 2001, pp. 65–66.

[28] Q. Lu, R. Lin, P. Ranada, P. Ranade, T.-J. King, and C. Hu, “Metal gate work function adjustment for future CMOS technology,” in VLSI Symp. Dig. Tech. Papers, 2001, pp.

45–46.

[29] R.H. Dennard, F.H. Gaensslen, H.-N. Yu, V.L. Rideout, E. Bassous, and A.R. LeBlanc,

“Design of ion-implanted MOSFET’s with very small physical dimensions,” IEEE Journal of Solid-State Circuits, vol. SC-9, pp. 256−268, 1974.

[30] T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi, and M. Bohr,

“Scaling challenges and device design requirements for higher performance sub-50nm gate length planar CMOS transistors,” Symposium on VLSI Technology Digest, 2000, pp.174−175.

[31] T. Ghani, S. Ahmed, P. Aminzadeh, J. Bielefeld, P. Charvat, C. Chu, M. Harper, P.

Jacob, C. Jan, J. Kavalieros, C. Kenyon, R. Nagisetty, P. Packan, J. Sebastian, M.

Taylor, J. Tsai, S. Tyagi, S. Yang, and M. Bohr, “100 nm gate length high performance / low power CMOS transistor structure,” IEDM Technical Digest, 1999, pp. 415−418.

[32] M. Hargrove, S. Crowder, E. Nowak, R. Logan, L. K. Han, H. Ng, A. Ray, D. Sinitsky, P. Smeys, F. Guarin, J. Oberschmidt, E. Crabbé, D. Yee, and L. Su, “High-performance sub-0.08 µm CMOS with dual gate oxide and 9.7 ps inverter delay,” IEDM Technical Digest, 1998, pp. 627−630.

[33] M. Rodder, S. Hattangady, N. Yu, W. Shiau, P. Nicollian, T. Laaksonen, C. P. Chao, M.

Mehrotra, C. Lee, S. Murtaza, and S. Aur, “A 1.2V, 0.1µm gate length CMOS technology: design and process issues,” IEDM Technical Digest, 1998, pp. 623−626.

[34] S.-H. Lo, D. A. Buchanan, and Y. Taur, “Modeling and characterization of quantization,

polysilicon depletion, and direct tunneling effects in MOSFETs with ultrathin oxides,”

IBM Journal of Research and Development, vol. 43, pp. 327−337, 1999.

[35] F. J. Pollack, “New microarchitecture challenges in the coming generations of CMOS process technologies,” 32nd Annual International Symposium on Microarchitecture, Haifa, Israel, November 16-18, 1999, p. 2.

[36] S.-H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, “Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET’s,”

IEEE Electron Device Letters, vol. 18, pp. 209−211, 1997.

[37] D. A. Muller, T. Sorsch, S. Moccio, F. H. Baumann, K. Evans-Lutterodt, and G. Timp,

“The electronic structure at the atomic scale of ultrathin gate oxides,” Nature, vol. 399, pp. 758−761, 1999.

[38] M. Schulz, “The end of the road for silicon?,” Nature, vol. 399, pp. 729−730, 1999.

[39] S. Tang, R.M. Wallace, A. Seabaugh, and D. King-Smith, “Evaluating the minimum thickness of gate oxide on silicon using first-principles method,” Applied Surface Science, vol. 135, pp. 137−142, 1998.

[40] C. Kaneta, T. Yamasaki, T. Uchiyama, T. Uda, and K. Terakura, “Structure and electronic property of Si(100)/SiO2 interface,” Microelectronic Engineering, vol. 48, pp.

117−120, 1999.

[41] A. I. Kingon, J.-P. Maria, and S. K. Streiffer, “Alternative dielectrics to silicon dioxide for memory and logic devices,” Nature, vol. 406, pp. 1032−1036, 2000.

[42] G. D. Wilk, R. M. Wallace, and J. M. Anthony, “High-k gate dielectrics: Current status and materials properties considerations,” Journal of Applied Physics, vol. 89, pp.

5243−5275, 2001.

[43] D. A. Buchanan, “Scaling the gate dielectric: Materials, integration, and reliability,”

IBM Journal of Research and Development, vol. 43, pp. 245−264, 1999.

[44] B. Cheng, M. Cao, P. V. Voorde, W. Greene, H. Stork, Z. Yu, and J. C. S. Woo,

“Design considerations of high-k gate dielectrics for sub-0.1-µm MOSFET’s,” IEEE Transactions on Electron Devices, vol. 46, pp. 261−262, 1999.

[45] C. Kittel, Introduction to Solid State Physics, 7th Edition, John Wiley & Sons, Inc., New York, 1996.

[46] K. Cho, “First-principles modeling of high-k gate dielectric materials,” Computational Materials Science, vol. 23, pp. 43−47, 2002.

[47] C. Chaneliere, J.L. Autran, R.A.B. Devine, and B. Balland, “Tantalum pentoxide (Ta2O5) thin films for advanced dielectric applications,” Materials Science &

Engineering, vol. R22, pp. 269−322, 1998.

[48] G. B. Alers, D. J. Werder, Y. Chabal, H. C. Lu, E. P. Gusev, E. Garfunkel, T.

Gustafsson, and R. S. Urdahl, “Intermixing at the tantalum oxide/silicon interface in gate dielectric structures,” Applied Physics Letters, vol. 73, pp. 1517−1519, 1998.

[49] S. A. Campbell, D. C. Gilmer, X. Wang, M. Hsieh, H. Kim, W. L. Gladfelter, and J.

Yan, “MOSFET transistors fabricated with high permittivity TiO2 dielectrics,” IEEE Transactions on Electron Devices, vol. 44, pp. 104−109, 1997.

[50] S. A. Campbell, R. Smith, N. Hoilien, B. He, and W. L. Gladfelter, “Group IVB metal oxides: TiO2, ZrO2, and HfO2 as high permittivity gate insulators,” Proceedings of MRS Workshop on High-k Gate Dielectrics, New Orleans, June 2000, p. 9.

[51] Y. Nishioka, H. Shinriki, and K. Mukai, “Influence of SiO2 at the Ta2O5/Si interface on dielectric characteristics of Ta2O5 capacitors,” Journal of Applied Physics, vol. 61, pp.

2335−2338, 1987.

[52] G. D. Wilk and R. M. Wallace, “Electrical properties of hafnium silicate gate dielectrics deposited directly on silicon,” Applied Physics Letters, vol. 74, pp.

2854−2856, 1999.

[53] G. D. Wilk and R. M. Wallace, “Stable zirconium silicate gate dielectrics deposited directly on silicon,” Applied Physics Letters, vol. 76, pp. 112−114, 2000.

[54] G. D. Wilk, R. M. Wallace, and J. M. Anthony, “Hafnium and zirconium silicates for advanced gate dielectrics,” Journal of Applied Physics, vol. 87, pp. 484−492, 2000.

[55] J. Lee, W. Qi, R. Nieh, B. Lee, L. Kang, K. Onishi, Y. Jeon, and E. Dharmarjan, “HfO2, ZrO2 and their silicates for gate dielectric applications,” Proceedings of MRS Workshop on High-k Gate Dielectrics, New Orleans, June 2000, p. 23.

[56] M. Copel, M. Gribelyuk, and E. Gusev, “Structure and stability of ultrathin zirconium oxide layers on Si(001),” Applied Physics Letters, vol. 76, pp. 436−438, 2000.

[57] C. M. Perkins, B. B. Triplett, P. C. McIntyre, K. C. Saraswat, S. Haukka, and M.

Tuominen, “Electrical and materials properties of ZrO2 gate dielectrics grown by atomic layer chemical vapor deposition,” Applied Physics Letters, vol. 78, pp.

2357−2359, 2001.

[58] D. A. Buchanan, “Scaling the gate dielectric: material, integration, and reliability,” IBM J. Res. Develop., vol. 43, no. 3, pp. 245−264, May 1999.

[59] H.-H. Tseng, D. O’Meara, P. Tobin, V. Wang, X. Guo, R. Hegde, I. Yang, P. Gilbert, R.

Cotton, and L. Hebert, “Reduced gate leakage current and boron penetration of 0.18 µm 1.5 V MOSFET’s using integrated RTCVD oxynitride gate dielectric,” in IEDM Tech. Dig., 1988, pp. 793–796.

[60] T. P. Ma, “Making silicon nitride film a viable gate dielectric,” IEEE Trans. Electron Devices, vol. 45, pp. 680–691, Mar. 1998.

[61] H. N. Al-Shareef, A. Karamcheti, T. Y. Luo, G. Bersuker, G. A. Brown, R. W. Murto, M. D. Jackson, H. R. Huff, D. Lopez, C. Olsen, and G. Miner, “Device performance of in-situ steam generated gate dielectric nitrided by remote plasma nitridation,” Appl.

Phys. Lett., vol. 78, no. 24, pp. 3875–3877, June 11, 2001.

[62] P. E. Nicollian, G. C. Baldwin, K. N. Eason, D. T. Grider, S. V. Hattangady, J. C. Hu, W. R. Hunter, M. Rodder, and A. L. P. Rotondaro, “Extending reliability scaling limit of SiO2 through plasma nitridation,” in IEDM Tech. Dig., 2000, pp. 545–548.

[63] S. C. Song, H. F. Luan, Y. Y. Chen, M. Gardner, J. Fulford, M. Allen, and D. L.

Kwong, “Ultra thin (<20 Å) CVD Si3N4 gate dielectric for deep-sub-micron CMOS devices,” in IEDM Tech. Dig., 1998, pp. 373–376.

[64] H. Yang, H. Niimi, J. W. Keister, G. Lucovsky, and J. E. Rowe, “The effects of interfacial sub-oxide transition regions and monolayer level nitridation on tunneling

currents in silicon devices,” IEEE Electron Device Lett., vol. 21, pp. 76–78, Feb. 2000.

[65] Y. Wu, Y. M. Lee, and G. Lucovsky, “1.6 nm oxide equivalent gate dielectrics using nitride/oxide (N/O) composites prepared by RPECVD/oxidation process,” IEEE Electron Device Lett., vol. 21, pp. 116–118, Mar. 2000.

[66] C. H. Chen, Y. K. Fang, C. W. Yang, S. F. Ting, Y. S. Tsair, M. C. Yu, T. H. Hou, M.

F. Wang, S. C. Chen, C. H. Yu, and M. S. Liang, “Thermally-enhanced remote plasma nitrided ultrathin (1.65 nm) gate oxide with excellent performances in reduction of leakage current and boron diffusion,” IEEE Electron Device Lett., vol. 22, pp. 378–380, Aug. 2001.

[67] J. E. Chung, P. K. Ko, and C. Hu, “A Model for hot-electron-induced MOSFET linear-current degradation based on mobility reduction due to interface-state generation,” IEEE Trans. Electron Devices, vol. 38, pp. 1362–1370, June 1991.

[68] H. S. Momose, T. Morimoto, Y. Ozawa, K. Yamabe, and H. Iwai, “An improvement of hot-carrier reliability in the stacked nitride-oxide gate n- and p-MISFET’s,” IEEE Trans. Electron Devices, vol. 42, pp. 704–712, Apr. 1995.

[69] M. T. Takagi and Y. Toyoshima, “Importance of Si-N atomic configuration at the Si/oxynitride interfaces on the performance of scaled MOSFETs,” in IEDM Tech. Dig., 1998, pp. 575–578.

[70] Chenming Hu, “Hot-electron effects in MOSFETs,” in IEDM Tech. Dig., 1983, pp.

176–181.

[71] E. Takeda, C. Y. Yang, and A. Miura-Hamada, Hot-Carrier Effects in MOS Devices,

New York: Academic, 1995.

[72] C. Hu, S. Tann, F. C. Hsu, P. K. Ko, and R. S. Muller, “Correlating the channel, substrate, gate and minority-carrier currents in MOSFET’s,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., 1983, pp. 88−89.

[73] J. W. Lyding, K. Hess, and I. C. Kizilyalli, “Reduction of hot electron degradation in MOS transistors by deuterium processing,” Appl. Phys. Lett., vol. 68, pp. 2526−2528, 1996.

[74] K. Hess, I. C. Kizilyalli, and J. W. Lyding, “Giant isotope effect in hot electron degradation of metal oxide silicon devices,” IEEE Trans. Electron Devices, vol. 45, pp.

406−416, 1998.

[75] E. H. Poindexter, E. R. Ahlstrom, and P. J. Caplan, “ESR Centers and charge defects near the Si-SiO2 interface,” in The Physics of SiO2 and Its Interfaces, S. T. Pantelides, Ed. New York: Pergamon, 1978, pp. 227−231.

[76] N. Kimizuka, K. Yamaguchi, K. Imai, T. Iizuka, C.T. Liu, R.C. Keller, and T. Horiuchi,

“NBTI enhancement by nitrogen incorporation into ultrathin gate oxide for 0.10-µm gate CMOS generation,” in Proc. Symp. VLSI Technol. 2000, pp. 92−93.

[77] N. Soin, J.F. Zhang, and G. Groeseneken, “MOSFETs reliability: electron trapping in gate dielectric,” in Proc. Int. Conf. Semiconductor Electronics, 2000, pp. 104−109.

[78] R. Degraeve, G. Groeseneken, R. Bellens, J. L. Ogier, M. Depas, P. J. Roussel, and H. E.

Maes, “New insights in the relation between electron trap generation and the statistical properties of oxide breakdown,” IEEE Trans. Electron Devices, vol. 45, pp. 904−911,

Apr. 1998.

[79] H. Wong and V. A. Gritsenko, “Dielectric traps in amorphous silicon oxynitride,” in Proc. Hong Kong Electron Devices Meeting, 2001, pp. 132−139.

[80] K. Eriguchi, T. Yamada, Y. Kosaka, and M. Niwa, “Impacts of plasma process–induced damage on ultra-thin gate oxide reliability,” in Proc. Int. Reliability Physics Symp., 1997, pp. 178−183.

[81] M. Togo, K. Watanabe, M. Terai, S. Kimura, A. Morioka, T. Yamamoto, T. Tatsumi, and T. Mogami, “Controlling base-SiO2 density of low-leakage 1.6 nm gate-SiON for high-performance and highly reliable n/pFETs” in Proc. Symp. VLSI Technol. 2001, pp.

81−82.

[82] D. A. Buchanan, “Scaling the gate dielectric: Materials, integration, and reliability,”

IBM J. Res. & Dev, vol. 43, no. 3, pp. 245−264, May 1999.

[83] H. Yang, H. Niimi, J. W. Keister, G. Lucovsky, and J. E. Rowe, “The effects of interfacial sub-oxide transition regions and monolayer level nitridation on tunneling currents in silicon devices,” IEEE Electron Device Lett., vol. 21, pp. 76−78, Feb. 2000.

[84] Y. Wu, Y. M. Lee, and G. Lucovsky, “1.6 nm oxide equivalent gate dielectrics using nitride/oxide (N/O) composites prepared by RPECVD/oxidation process,” IEEE Electron Device Lett., vol. 21, pp. 116−118, Mar. 2000.

[85] C. H. Chen, Y. K. Fang, C. W. Yang, S. F. Ting, Y. S. Tsair, M. C. Yu, T. H. Hou, M.

F. Wang, S. C. Chen, C. H. Yu, and M. S. Liang, “Thermally-enhanced remote plasma

nitrided ultrathin (1.65 nm) gate oxide with excellent performances in reduction of leakage current and boron diffusion,” IEEE Electron Device Lett., vol. 22, pp. 378−380, Aug. 2001.

[86] D. Park, Y.-C. King, Q. Lu, T.-J. King, C. Hu, A. Kalnitsky, S.-P. Tay, and C.-C.

Cheng, “Transistor characteristics with Ta2O5 gate dielectric,” IEEE Electron Device Lett., vol. 19, pp. 441−443, Nov. 1998.

[87] A. Chin, Y.H. Wu, S.B. Chen, C.C. Liao, and W.J. Chen, “High quality La2O3 and Al2O3 gate dielectrics with equivalent oxide thickness 5−l0A,” in Proc. Symp. VLSI Technol. 2000, pp. 16−17.

[88] Y. Ma, Y. Ono, L. Stecker, D.R. Evans, and S.T. Hsu, “Zirconium oxide based gate dielectrics with equivalent oxide thickness of less than 1.0 nm and performance of submicron MOSFET using a nitride gate replacement process,” in IEDM Tech. Dig., 1999, pp. 149−152.

[89] L. Kang, Y. Jeon, K. Onishi, B. H. Lee, W.-J. Qi, R. Nieh, S. Gopalan, and J.C. Lee,

“Single-layer thin HfO2 gate dielectric with n+-polysilicon gate,” in Proc. Symp. VLSI Technol. 2000, pp. 44−45.

[90] S. C. Song, H. F. Luan, Y.Y. Chen, M. Gardner, J. Fulford, M. Allen, and D.L. Kwong,

“Ultra thin (<20A) CVD Si3N4 gate dielectric for deep-sub-micron CMOS devices,” in IEDM Tech. Dig., 1998, pp. 373−376.

[91] S. Mahapatra, V. Ramgopal Rao, K.N. ManjulaRani, C. D. Parikh, J. Vasi, B. Cheng, M.

Khare, and J. C. S. Woo, “100 nm channel length MNSFETs using a jet vapor deposited ultra-thin silicon nitride gate dielectric,” in Proc. Symp. VLSI Technol. 1999, pp. 79−80.

[92] I. Polishchuk, Q. Lu, Y.-C. Yeo, T.-J. King, and C. Hu, “Reliability of ultra-thin JVD gate nitride and MOSFET reliability projections,” TECHCON 2000, Phoenix, AZ, Sep.

2000.

[93] T.-C. Ong, P.-K. Ko, and C. Hu, “Modeling of substrate current in p-MOSFET’s,”

IEEE Electron Device Lett., vol. EDL-8, pp. 413−416, Sep. 1987.

[94] T.-C. Ong, P.-K. Ko, and C. Hu, “Hot-carrier current modeling and device degradation in surface-channel p-MOSFET’s,” IEEE Trans. Electron Devices, vol. 37, pp.

1658–1666, Jul. 1990.

[95] T. Tsuchiya, Y. Okazaki, M. Miyake, and T. Kobayashi, “New hot-carrier degradation mode and lifetime prediction method in quarter-micrometer PMOSFET,” IEEE Trans.

Electron Devices, vol. 39, pp. 404–408, Feb. 1992.

[96] R. Woltjer, G. M. Paulzen, H.G. Pomp, H. Lifka, and P.H. Woerlee, “Three hot-carrier degradation mechanisms in deep-submicron PMOSFET’s,” IEEE Trans. Electron Devices, vol. 42, pp. 109–115, Jan. 1995.

[97] A. Bravaix, “Hot-carrier degradation evolution in deep-submicrometer CMOS technologies,” IEEE International Integrated Reliability Workshop Final Report, pp.

174–183, 1999.

[98] G. La Rosa, F. Guarin, S. Rauch, A. Acovic, J. Lukaitis, and E. Crabbe, “NBTI-channel hot carrier effects in pMOSFETs in advanced CMOS technologies,” in Int. Reliab. Phys.

Symp., 1997, pp. 282−286.

[99] T.Yamamoto, K. Uwasawa, and T. Mogami, “Bias temperature instability in scaled p+

polysilicon gate p-MOSFET’s,” IEEE Trans. Electron Devices, vol. 46, no. 5, pp.

921−926, May 1999.

[100] N. Kimizuka, K. Yamaguchi, K. Imai, T. Iizuka, C. T. Liu, R. C. Keller, and T. Horiuchi,

“NBTI enhancement by nitrogen incorporation into ultrathin gate oxide for 0.10-µm gate CMOS generation,” in Proc. Symp. VLSI Technol. 2000, pp. 92−93.

[101] Q. Xiang, J. Jeon, P. Sachdey, B. Yu, K. C. Saraswat, and M.-R. Lin, “Very high performance 40nm CMOS with ultra-thin nitride/oxynitride stack gate dielectric and pre-doped dual poly-Si gate electrodes,” in IEDM Tech. Dig., 2000, pp. 860−862.

[102] M. Togo, K. Watanabe, T. Yamamoto, N. Ikarashi, K. Shiba, T. Tatsumi, H. Ono, and T.

Mogami, “Low-leakage and highly-reliable 1.5 nm SiON gate-dielectric using radical oxynitridation for sub-0.1 µm CMOS,” in Proc. Symp. VLSI Technol. 2000, pp.

116−117.

[103] S. Tsujikawa, T. Mine, Y. Shimamoto, O. Tonomura, R. Tsuchiya, K. Ohnishi, H.

Hamamura, K. Torii, T. Onai, and J. Yugami, “An ultra-thin silicon nitride gate dielectric with oxygen-enriched interface (OI-SiN) for CMOS with EOT of 0.9 nm and beyond,” in Proc. Symp. VLSI Technol. 2002, pp. 202−203.

[104] K. O. Jeppson and C. M. Svensson, “Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices,” J. Appl. Phys., vol. 48, (5), pp.

2004−2014, 1977.

[105] C. Hu, “Gate oxide scaling limits and projection,” in IEDM Tech. Dig., 1996, pp.

319−322.

[106] Y. Momiyama, H. Minakata, and T. Sugii, “Ultra-thin Ta2O5/SiO2 gate insulator with TiN gate technology for 0.1 µm MOSFET’s,” in Symp. VLSI Technol. Dig. Tech.

Papers, 1997, pp. 135−136.

[107] A. Yagishita, T. Saito, K. Nakajima, S. Inumiya, K. Matsuo, T. Shibata, Y. Tsunashima, K. Suguro, and T. Arikado, “Improvement of threshold voltage deviation in damascene metal gate transistors,” IEEE Trans. Electron Devices, vol. 48, pp. 1604−1611, Aug.

2001.

[108] J. L. Autran, R. Devine, C. Chaneliere, and B. Balland, “Fabrication and characterization of Si-MOSFET’s with PECVD amorphous Ta2O5 gate insulator,” IEEE Electron Device Lett., vol. 18, pp. 447−449, Sep. 1997.

[109] A. Chin, Y. H. Wu, S. B. Chen, C. C. Liao, and W. J. Chen, “High quality La O and Al O gate dielectrics with equivalent oxide thickness 5-10 Å

2 3

2 3 ,” in Symp. VLSI Technol.

Dig. Tech. Papers, 2000, pp. 16−17.

[110] C. H. Lee, H. F. Luan, W. P. Bai, S. J. Lee, T. S. Jeon, Y. Senzaki, D. Roberts, and D. L.

Kwong, “MOS characteristics of ultra thin rapid thermal CVD ZrO2 and Zr silicate gate dielectrics,” in IEDM Tech. Dig., 2000, pp. 27−30.

[111] L. Kang, K. Onishi, Y. Jeon, B. H. Lee, C. Kang, W.-J. Qi, R. Nieh, S. Gopalan, R.

Choi, and J. C. Lee, “MOSFET devices with polysilicon on single-layer HfO2 high-κ dielectrics,” in IEDM Tech. Dig., 2000, pp. 35−38.

[112] C.K. Maiti, S. Chatterjee, G.K. Dalapati, and S.K. Samanta, “Electrical properties of Ta2O5 gate dielectric on strained-Si,” Electronics Lett., vol. 39, pp. 497−499, Mar.

2003.

[113] A. Chin, C.C. Liao, C.H. Lu, W.J. Chen, and C. Tsai, “Device and reliability of high-κ Al2O3 gate dielectric with good mobility and low Dit,” in Symp. VLSI Technol. Dig.

Tech. Papers, 1999, pp. 135−136.

[114] G. D. Wilk, R. M. Wallace, and J. M. Anthony, “Hafnium and zirconium silicates for advanced gate dielectrics,” J. Appl. Phys., vol. 87, no. 1, pp. 484−492, 2000.

[115] G. D. Wilk, and R. M. Wallace, “Electrical properties of hafnium silicate gate dielectrics deposited directly on silicon,” Appl. Phys. Lett., vol. 74, no. 19, pp.

2854−2856, 1999.

[116] T. Ma, S. A. Campbell, R. Smith, N. Hoilien, B. He,W. L. Gladfelter, C. Hobbs, D.

Buchanan, C. Taylor, M. Gribelyuk, M. Tiner, M. Coppel, and J. J. Lee, “Group IVB metal oxides high permittivity gate insulators deposited from anhydrous metal nitrates,”

IEEE Trans. Electron Devices, vol. 48, pp. 2348−2356, Jun. 2001.

[117] L. Kang, Y. Jeon, K. Onishi, B. H. Lee, W.-J. Qi, R. Nieh, S. Gopalan, and J. C. Lee,

“Single-layer thin HfO2 gate dielectric with n+-polysilicon gate,” in Symp. VLSI Technol. Dig. Tech. Papers, 2000, pp. 44−45.

[118] E. P. Gusev, D. A. Buchanan, E. Cartier, A. Kumar, D. DiMaria, S. Guha, A. Callegari, S. Zafar, P. C. Jamison, D. A. Neumayer, M. Copel, M. A. Gribelyuk, H.

Okorn-Schmidt, C. D'Emic, P. Kozlowski, K. Chan, N. Bojarczuk, L.-A. Ragnarsson, P.

Okorn-Schmidt, C. D'Emic, P. Kozlowski, K. Chan, N. Bojarczuk, L.-A. Ragnarsson, P.