The hot carrier injection reliability of nMOSFET’s with ultrathin plasma nitrided gate oxide is investigated in this chapter. The devices with plasma nitrided oxide suffer more transconductance reduction and threshold voltage shift. The degradation is direct proportional to the plasma nitridation time. For channel hot-carrier stressing, the most efficient stressing condition is located at Vg = Vd, rather than maximum substrate current or Vg = Vd / 2 which is often utilized for traditional nMOSFETs. For substrate hot-carrier stressing, the raising of substrate voltage can enhance the device degradation considerably. We report, for the first time, an enhanced degradation under negative substrate bias in nMOSFETs with ultrathin plasma nitrided gate dielectric. The enhanced degradation is attributed to the introduction of paramagnetic electron trap precursors during plasma nitridation. Similar to NBTI in
pMOSFETs, our findings are important for nMOSFETs from the reliability point of view.
Even though the incorporation of nitrogen into thermal oxide is advantageous in many respects, our findings suggest that careful attentions need to be paid to ensure that plasma-nitrided gate dielectric meets the reliability requirements for the sub-100nm device technology node.
Drain Voltage (V)
deep submicron (W/L = 10/0.13 µm) devices with thermal oxide (N0) and plasma nitrided oxides (N1, N2).Gate Voltage (V)
deep submicron (W/L = 10/0.13 µm) devices with thermal oxide (N0) and plasma nitrided oxides (N1, N2).Effective Gate Drive (V)
devices with thermal oxide (N0) and plasma nitrided oxides (N1, N2).Gate Voltage (V)
submicron (W/L = 10/0.13 µm) devices with thermal oxide (N0) and plasma nitrided oxides (N1, N2).Effective Gate Drive (V)
thermal oxide (N0) and plasma nitrided oxides (N1, N2).Stress Time (sec)
10
010
110
210
310
410
5−∆ Gmmax / Gmmax (%)
10
-210
-110
010
110
2N0 N1 N2 Vd = 1.8V
(a)
Stress Time (sec)
10
010
110
210
310
410
5−∆ Gmmax / Gmmax (%)
10
-210
-110
010
110
2N0 N1 N2 Vd = 2.0V
(b)
Stress Time (sec)
10
010
110
210
310
410
5−∆ Gmmax / Gmmax (%)
10
-210
-110
010
110
2N0 N1 N2 Vd = 2.2V
(c)
Fig. 3.6 Stress time dependence of Gm,max degradation (∆Gm,max / Gm,max(0)) in devices with thermal oxide (N0) and plasma nitrided oxides (N1, N2) at (a) Vd = 1.8V, Vg = Isub,max, (b) Vd = 2.0V, Vg = Isub,max, and (c) Vd = 2.2V, Vg = Isub,max.
Gate Voltage (V)
0.0 0.5 1.0 1.5 2.0
(−) Substrate Current (µA)
10-3 10-2 10-1 100 101
Fig. 3.7 Typical substrate current curve as a function of gate voltage to estimate the stressing condition.
Stress Time (sec)
Stress Time (s)
with thermal oxide (N0) and plasma nitrided oxides (N1, N2) at Vd = 1.8V and Vg = 0.9, 1.3, and 1.8V.Stress Time (sec)
10
010
110
210
310
410
5Threshold Voltage Shift (V) 10
-510
-4Stress Time (sec)
Threshold Voltage Shift (V) 10
-510
-4Fig. 3.10 Threshold voltage shift of devices with thermal oxide (N0) and plasma nitrided oxides (N1, N2) as a function of stress time at (a) Vd = 1.8V, Vg = Isub,max, (b) Vd
= 2.0V, Vg = Isub,max, and (c) Vd = 2.2V, Vg = Isub,max.
Stress Time (sec)
10
010
110
210
310
410
5Threshold Voltage Shift (V) 10
-510
-4Threshold Voltage Shift (V) 10
-510
-4Fig. 3.11 Threshold voltage shift of devices with thermal oxide (N0) and plasma nitrided oxides (N1, N2) as a function of stress time at (a) Vd = 1.8V, Vg = 0.9V and (b) Vd = Vg = 1.8V.
Stress Time (s)
Fig. 3.12 Threshold voltage shift of devices with thermal oxide (N0) and plasma nitrided oxides (N1, N2) as a function of stress time at Vd = 1.8V and Vg = 0.9, 1.3, and Vd = 1.8V stress 10000s
Fig. 3.13 Id-Vg characteristics of device with plasma nitrided oxide (N2) before and after 10,000 sec stressing at Vd = 1.8V, Vg = 0.9, 1.3, and 1.8V.
Stress Time (sec)
Stress Time (sec)
10
010
110
210
310
410
5Threshold Voltage Shift (V) 10
-410
-3N0 N1 N2
Vg = 1.8V
(a)
Stress Time (sec)
10
010
110
210
310
410
5Threshold Voltage Shift (V) 10
-510
-410
-310
-210
-1N0 N1 N2
Vg = 1.8V Vb = −2V
(b)
Fig. 3.15 Threshold voltage shift of devices with thermal oxide (N0) and plasma nitrided oxides (N1, N2) as a function of stress time at (a) Vg = 1.8V, Vd = Vs = Vb = 0V and (b) Vg = 1.8V, Vb = −2V, Vd = Vs = 0V.
Stress Time (sec)
10
010
110
210
310
410
5−∆ Gmmax / Gmmax (%)
10
-210
-110
0N0 N1 N2
Vg = 2.2V
(a)
Stress Time (sec)
10
010
110
210
310
410
5Threshold Voltage Shift (V) 10
-410
-310
-2N0 N1 N2
Vg = 2.2V
(b)
Fig. 3.16 (a) Gm,max degradation (∆Gm,max / Gm,max (0)) and (b) threshold voltage shift of devices with thermal oxide (N0) and plasma nitrided oxides (N1, N2) as a function of stress time at Vg = 2.2V, Vd = Vs = Vb = 0V.
Stress Time (sec)
Stress Time (sec)
10
010
110
210
310
410
5−∆ Id / Id (%)
10
-310
-210
-110
010
110
2N0 N1 N2 Vg = 2.2V
Vb = −2V
(c)
Fig. 3.17 Stress time dependence of (a) Gm,max degradation (∆Gm,max / Gm,max (0)), (b) threshold voltage shift, and (c) drain current degradation (∆Id / Id(0)) in devices with thermal oxide (N0) and plasma nitrided oxides (N1, N2) at Vg = 2.2V, Vb
= −2V, Vd = Vs = 0V.
Stress Time (sec)
Threshold Voltage Shift (V) 10
-510
-4Fig. 3.18 Substrate hot electron (SHE) stress time dependence of (a) relative Gm
degradation and (b) threshold voltage (Vt) shift for devices with thermal oxide (N0) and plasma nitrided oxides (N1 and N2). Substrate biases are 0V and –2V.
Substrate Voltage (V)
Threshold V o ltage Shift (V)
10
-4Fig. 3.19 Threshold voltage (Vt) shift of the devices with thermal oxide (N0) and plasma nitrided oxides (N1, N2) as a function of substrate bias after 104 sec of SHE stressing.
Fig. 3.20 Relative gate leakage current change as a function of SHE stress time for different samples.
Chapter 4
Reliability of pMOSFETs with Ultrathin Plasma Nitrided Gate Dielectric
4.1 Backgrounds and Motivation
For MOSFETs employing ultrathin gate oxide, the drastic increase in standby power consumption as a result of the direct tunneling leakage current in the dielectric is a challenging issue, especially as device scaling leads to higher device density in a chip. In addition, the dopant impurity penetration through the ultrathin gate dielectric represents another major concern on the oxide scaling. In the past, nitrogen incorporation into the ultrathin gate oxide to form oxynitride and/or nitride/oxide stacks have been successfully demonstrated to alleviate the above shortcomings [82]. Among the available nitridation techniques, plasma nitridation is particularly viable and popular for preparing reliable ultrathin gate dielectric due to its uniformity, relatively high nitrogen concentration, low process temperature, and the ability to preserve high quality oxide/Si interface [83]−[85].
As gate oxide thickness in MOS devices is reduced, the increasing gate leakage current poses a major challenge to continued transistor scaling. Reliability of the ultrathin SiO2
presents another major concern. Thus a transition to a gate material with a higher dielectric constant is critical for further CMOS scaling. A number of high-κ dielectrics, such as Ta2O5 [86], Al2O3 [87], La2O3 [87], ZrO2 [88], HfO2 [89] and several silicates have been proposed to replace SiO2 in the gate stack. Stability of these materials in contact with silicon during
high-temperature processing steps remains a major problem. Thus it might be a few years before a successful integration of a high-κ dielectric into CMOS fabrication process becomes reality. At the same time Si3N4, which has a relatively high dielectric constant of 7.5 (almost twice that of SiO2), has been used by the semiconductor industry for decades and is relatively easy to integrate into the fabrication process. Good performance of Si3N4 transistors has already been demonstrated [90]. It is necessary to demonstrate good reliability of thin Si3N4 before it can replace SiO2 as gate dielectric, however. Studies of time-dependent dielectric breakdown [90], [91], and time-dependent dielectric wear out [92] indicate that Si3N4 under Fowler-Nordheim stress meets reliability requirements. It still remains to be shown that hot-carrier reliability of Si3N4 gate dielectrics is acceptable. Earlier work [91] indicates good hot-carrier reliability of nMOSFET JVD nitride transistors with 3.1 nm equivalent oxide thickness. In this chapter we will examine the hot-carrier reliability of Si3N4 pMOSFETs as well as SiO2 pMOSFETs.
We also examine the mechanism responsible for pMOSFET degradation. It has been long known that the mechanism responsible for the device degradation in nMOSFET is interface-state generation. The situation for pMOSFETs is less clear. It had long been believed that hot-carrier reliability of pMOSFETs is not as serious an issue as hot-carrier reliability of nMOSFETs for the following reason: The mean free path of holes in silicon is about one half that of the electrons [93]; therefore holes scatter more frequently and fewer of them reach high enough energies (about 4 eV) to create interface states [94]. However, as the transistor channel length has been scaled down into the deep-sub-micron regime (and supply voltages have been reduced) hot-carrier induced degradation of pMOSFETs has been approaching that of nMOSFETs [95]. Consequently the hot-carrier reliability of pMOSFETs has been studied in more detail. Three hot-carrier degradation mechanisms in pMOSFET’s have been identified [96], [97]. The first is negative oxide charge trapping. Electron trapping
near the drain region leads to a reduction in the threshold voltage and to the effective channel shortening. As a result, pMOSFET drive current increases. This mechanism is most important in longer channel pMOSFETs, and gate current Ig has been used as a predictor of the device lifetime. The second mechanism is the generation of interface states by hot holes, which leads to channel mobility degradation. In this case the substrate current Isub should be used to predict the device lifetime. And the third mechanism is positive oxide charge trapping.
Interface-state generation has been shown to be the dominant degradation mechanism for 0.25 µm surface channel pMOSFETs [96]. We will show that this conclusion remains true for our devices, for both oxide and nitride gate dielectrics.
4.2 Experimental Procedure
Deep submicron (0.13 µm) pMOSFETs with ultrathin gate dielectrics were used in this study. After active device area definition, conventional thermal oxides were grown at 900°C.
In order to achieve a final equivalent oxide thickness (EOT) of approximately 2.0 nm for all splits, thermal oxides with various starting thickness were subjected to various plasma nitridation times. After deposition and patterning of a 150 nm thick un-doped poly-Si film, boron dopants were implanted with energy of 5 keV to dope the gate electrode and also to form the shallow source/drain junction. For activation, all samples were annealed using rapid thermal annealing (RTA) in N2 gas ambient for 30 sec. Subsequently, cobalt salicide, borophosphosilicate glass (BPSG), and metallization processes were performed to complete the device fabrication. The hot-carrier stress of pMOSFETs was carried out subjecting to the drain voltage of −2.1V, −2.3V, and −2.5V with the gate voltage at the condition of maximum gate current. For time-dependent reliability testing, constant negative voltage of −2.1V, −2.3V, and −2.5V were applied to the gate with the source, drain, and substrate grounded at room
temperature. For negative bias temperature instability (NBTI) testing, the temperature was ranged from room temperature to elevated 100°C. Device characteristics were recorded at certain time interval for stress time up to 104 seconds. The indicators of reliability degradation are transconductance Gm reduction and threshold voltage Vt shift. Gm is defined as the peak value of the transconductance of a device in linear region, while threshold voltage is defined at the interception extrapolated from the peak value.