GATE-OXIDE OVERSTRESS PROBLEM

With the advantages in speed, power and cost, thin-oxide devices are more suitable in high-speed and low-power applications. However, thin gate oxide with large gate-to-source voltage is vulnerable to gate-oxide breakdown. The breakdown can happen instantaneously or over time [15], [16]. The lifetime of gate oxide over the voltage stress can be expressed as equation 1.3 [15].

,where τ0and G are two constants, Xeff is the effective thickness of the gate oxide due to the defeats, and Vox(t) is the time-dependent voltage across the gate oxide. As expressed in equation 1.3, the accumulation of the voltage stress over time determines the gate-oxide breakdown. Thus, the damage caused by transient overstress is still non-ignorable if it happens frequently and lasts for enough time.

In addition to the consideration of hot-carrier degradation, the absolute value of gate-to-source and gate-to-drain voltage should be less than the supply voltage and the drain-to-source voltage in NMOS devices and source-to-drain voltage in PMOS devices must be less than the supply voltage when devices work in “on” state.

1.5 B

I

PCI-X

The operating frequency used in the simulation of the new proposed I/O buffer is 133 MHz, which is the specification of PCI-X application.

PCI-X, the initial of “Peripheral Component Interconnect Extended,” is the standard for the computer bus and expansion card jointly developed by IBM, HP and Compaq [17]-[18].

With higher data width, PCI-X is an improved version of PCI for higher throughput. Such a

standard is required in some devices such as gigabit ethernet cards, fibre Channel, ultra 320 SCSI controllers, and cluster interconnects. Four frequency grades for cards or slots based on PCI-X standard are 66 MHz, 133 MHz, 266 MHz, and 533 MHz. For both PCI-X 1.0 and PCI-X 2.0, 133 MHz is included in the specifications and is most common in applications.

Thus, 133 MHz is a suitable operating frequency for I/O buffer design with the expectation to be applied to the interface circuit.

Chapter 2

Prior I/O Buffers with 2xVDD Tolerance

In this chapter, three 2xVDD tolerant mixed-voltage I/O buffers ([14], [19], and [20]) and I/O buffers with dual-oxide devices are retrospected before the section of new proposed I/O buffer.

[19] was designed with eliminated reliability problems in steady state but suffers hot-carrier degradation and gate-oxide overstress problem in transient state. [14] proposed a technique which can be used to solve the hot-carrier degradation problem in stacked NMOS or PMOS transistors but it was unable to solve transient hot-carrier degradation and gate-oxide overstress happening in some transistors completely.

To realize an I/O buffer with 1.8/3.3/5-V mixed-voltage tolerance without reliability issues, 0.35-μm devices had been used in [21] and the voltage differences are kept within the supply voltage of 3.3 V. Dual-oxide (thick-oxide and thin-oxide) processes [22]-[24] had been used to prevent reliability issues in mixed-voltage in I/O buffers. Using two kinds of devices (such as 1-V and 2.5-V devices) had also been adopted in [25] to transmit 3.3-V signals without reliability issue. However, using two masks increases the cost in the fabrication.

To eliminate hot-carrier degradation and gate-oxide overstress problems in prior circuits, [20] and this work [7] are proposed. [20] will be also introduced in this chapter, and will be compared with the new proposed I/O buffer in later section.

2.1 P

D

I

2.1.1 Basic Operation

A conventional mixed-voltage I/O buffer with the gate-tracking circuit and the dynamic n-well bias circuit is shown in Fig. 2.1 [19]. With the new dynamic n-well bias circuit (composed of transistor MP4 and MP6) and gate-tracking circuit (composed of transistor MN2 to MN4, transistor MP2, MP3 and MP5), this conventional I/O buffer was realized with only the thin gate-oxide devices, and it occupied smaller silicon area than the prior designs [8]-[10]. When the control signal OE is at VDD (logic “1”), the I/O buffer is operated in the transmit mode. The PD port from the pre-driver circuit is directly connected to the gate terminal of the pull-down NMOS device, MN1. The PU port of the pre-driver circuit is connected to the gate terminal of the pull-up PMOS device, MP0, through the gate-tracking circuit. According to the signal Dout controlled by the internal circuits of the IC and the turned on of transmission gate MN2

Fig. 2.1 The conventional mixed-voltage I/O buffer designed with gate-tracking circuit and dynamic n-well bias circuit to solve gate-oxide reliability issue [19].

and MP2, the PU signal and PD signal control the driving NMOS or PMOS transistors to charge I/O PAD to VDD or discharge I/O PAD to 0 V, respectively. At that time, MP4 is also

turned on to bias the floating n-well to VDD so the pn-junction diodes in transistors MP0 and MP4 are reverse biased to eliminate leakage current. When the I/O buffer is operated in the receive mode with OE signal biased at 0 V, the PU and PD ports of the pre-driver circuit are kept at VDD and 0 V, respectively. Thus, transistors MP0 and MN1 are turned off. The Din signal rises or falls according to the received signal at the I/O PAD. Transistor MP3 is used to track the signal at the I/O PAD to the gate voltage of transistor MP0 to prevent the undesired leakage current from the I/O PAD to the power supply (VDD) through the pull-up PMOS device MP0. When the voltage level at the I/O PAD exceeds VDD+|Vtp| and rise to 2xVDD, transistor MP3 is turned on to turn off transistor MP0 to prevent the leakage current through its drain to source. Transistor MP4 is also turned off while transistor MP6 is turn on to bias the floating n-well at 2xVDD to reverse bias the parasitic pn-junction diode for eradicating leakage current from the I/O PAD to VDD. Besides, MP2 is also turned off due to the turned on of transistor MP5 to eliminate the conductance and leakage current from the I/O PAD to the PU port. The input signal from the I/O PAD is transferred to the internal node Din by MN0, MP1, inverter INV1 and INV2. MN0 is used to decrease the received voltage level at the drain of MN1. Because the gate terminal of MN0 is connected to VDD, the input voltage of inverter INV is limited to VDD-Vtn when the voltage level at the I/O pad is 2xVDD.

However, MP1 turns on while the input node of inverter INV1 rises over the threshold to pull down the output node of inverter INV1 to 0 V. Thus, the drain voltage of transistor MN1 is kept at VDD and the signal at the I/O pad can also be successfully received by the internal input node Din.

2.1.2 Prior Design I with Reliability Concern

Mixed-voltage I/O buffer in Fig. 2.1 can tolerate 2xVDD input signal at the I/O PAD without suffering gate-oxide reliability, hot-carrier degradation, and undesired circuit leakage

in the steady state. However, during the transition from receiving 2xVDD input signal to transmitting 0-V output signal, MN0 and MN3 suffer hot-carrier degradation problem. MP5 also suffers gate-oxide reliability problem. Moreover, MN2, MP2, and MN3 also suffer hot-carrier degradation problem during the transition from receiving 2xVDD input signal to transmitting VDD output signal.

The limitations for the gate-to-source voltage and drain-to-source voltage of the transistors mentioned in the end of chapter 1 are followed in some prior arts as Fig. 2.1 in steady state. However, during the transition from receiving 2xVDD input signal to transmitting 0-V output signal, the drain-to-source voltage (Vds) of MN0 and MN3 will be much higher than VDD. The reason is that the drain-to-source voltage starts to increase from VDD since the source terminal is pulled down faster than the drain terminal at the beginning of this transition. MP5 also has larger Vgs since its source and gate are connected to the drain and source of MN0. Moreover, MN2, MP2, and MN3 also come across similar problem during the transition from receiving 2xVDD input signal to transmitting VDD output signal.

While PU signal is suddenly pulled down from VDD to 0, the drain terminal of MN2 are pulled down much slower since the transistors are turned on accordingly and it also takes time for the gate terminal of MP2 to be pulled down from 2xVDD to turn on MP2. The above mentioned transient situations for MN0, MN3, MP5, MN2, and MP2 with high voltage across drain and source terminals are verified by HSPICE simulation results in a 0.13-μm CMOS technology with 1.2-V VDD and 2.5-V 2xVDD. As shown in Fig. 2.2, Fig. 2.3(a), (b), and Fig. 2.4, Vds of MN0 (also the Vsg of MP1), MN3, MN2, and MP2 are much larger than VDD during a certain time. The peak values are 1.96 V, 2.11 V, 2.09 V, and 2.07 V respectively. Thereby, it results in serious hot-carrier degradation or gate-oxide overstress in the transition from receiving 2.5-V input signal to transmitting 0-V or 1.2-V output signal.

Fig. 2.2 Drain-to-source voltage (Vds) of MN0 (and also the source-to-gate voltage (Vsg) of transistor MP5) in Fig. 2.1 during the transition from receiving 2xVDD input signal to transmitting 0-V output signal.

(a)

(b)

Fig. 2.3. Drain-to-source voltage (Vds) of transistor MN3 in Fig. 2.1 (a) during the transition from receiving 2xVDD input signal to transmitting 0-V output signal and (b) during the transition from receiving 2xVDD input signal to transmitting VDD output signal.

Fig. 2.4. Drain-to-source voltage (Vds) of MN2 (source-to-drain voltage (Vsd)) of MP2 in Fig. 2.1 during the transition from receiving 2xVDD input signal to transmitting VDD output signal.

2.2 P

D

II

2.2.1 Basic Operation

To solve the hot-carrier degradation problems happened in some prior arts as Fig. 2.1, a technique with three or more stacked NMOS transistors and related PMOS transistors as gate control circuits had been reported in [14]. A modified 2xVDD-tolerant I/O buffer with this technique to eliminate hot-carrier issue is shown in Fig. 2.5 with similar steady state operation as listed in TABLE 1.1. When the I/O buffer receives 2xVDD input signal, the gate terminal of MN5 and MN6 are biased at 2xVDD through MPT1 and MPT3, respectively. On the other hand, the gate terminal of transistor MN5 and MN6 are biased at VDD if a VDD signal is transmitted or a 0-V signal appears at the I/O PAD whether received or transmitted.

Fig. 2.5. Modified mixed-voltage I/O buffer designed with three-stacked transistors to prevent hot-carrier degradation [14].

2.2.2 Prior Design Ⅱ with Reliability Concern

During the transition from receiving 2xVDD input signal to transmitting 0-V output signal, the source terminal of MN5 and MN6 are biased at 2xVDD-ΔV initially (where ΔV is the Vds of the diode-connected transistors) because of their diode connected structure.

Meanwhile, the source terminal of MN0 and MN3 are pulled down by MN1 and MN4 in a 0.13-μm technology, respectively. Comparing the MN0 and MN3 in Fig. 2.1 with the same transistors in I/O buffer in Fig. 2.5 during this transient time, the transistors in I/O buffer in Fig. 2.5 have smaller Vds since the drain voltage is initially smaller by –ΔV.

Fig. 2.6, Fig. 2.7(a), (b), Fig. 2.8 and Fig. 2.9 are the HSPICE simulation results using 0.13-μm CMOS technology when VDD is 1.2 V. With smaller maximum of Vds, the I/O buffer in Fig. 2.5 can almost eliminate most serious hot-carrier degradation happened in previous designs, as shown in Fig. 2.6, Fig. 2.7(a), and (b). However, the gate-oxide

overstress still happens in MP1 in Fig. 2.5 during the transition from receiving 2xVDD to transmitting 0 V, as shown in Fig. 2.8. Also, the transmission circuit (with MN2 and MP2 in Fig. 2.5) still suffers the hot-carrier degradation, as shown in Fig. 2.9.

Fig. 2.6. Drain-to-source voltage (Vds) of MN0 in Fig. 2.5 during the transition from receiving 2xVDD input signal to transmitting 0-V output signal.

(a)

(b)

Fig. 2.7. Drain-to-source voltage (Vds) of MN3 in Fig. 2.5 during the transition from receiving 2xVDD input signal (a) to transmitting 0-V output signal and (b) to transmitting VDD output signal.

Fig. 2.8. Source-to-gate voltage (Vsg) of MP1 in Fig. 2.5 during the transition from receiving 2xVDD input signal to transmitting 0 output signal

Fig. 2.9. Drain-to-source voltage (Vds) of MN2/MP2 in Fig. 2.5 during the transition from receiving 2xVDD input signal to transmitting VDD output signal.

2.3 P

D

III

Using dual-oxide (thick-oxide and thin-oxide) process [22]-[24] provided by foundry is also a method to eliminate reliability issues as gate-oxide overstress and hot-carrier degradation in mixed-voltage I/O buffers. From equation 1.2 and 1.3, increasing channel length and gate-oxide thickness leads to increased tolerance of absolute drain-to-source and gate-to-source voltage are increased. With such a characteristic, thick-oxide devices with longer channel length are more robust than the thin-oxide device and can be used to sustain large drain-to-source or gate-to-source voltage. For example, [21] used 0.35-μm devices with voltage differences kept within the supply voltage of 3.3 V to realize an I/O buffer with 1.8/3.3/5-V mixed-voltage tolerance without reliability issues. Two kinds of devices (1-V and 2.5-V transistors) had been also adopted in [25] to output 3.3-V signal without aforesaid issues.

In the 2xVDD tolerant I/O buffer, Fig. 2.10 shows the mixed-voltage I/O buffer with dual-oxide (thick-oxide and thin-oxide) devices. An external n-well bias voltage is also connected to the body terminal of the pull-up PMOS device in the I/O buffer to avoid leakage current path from the I/O pad to the power supply (VDD) through the parasitic drain-to-well pn-junction diode. However, adding an external bias voltage VDDH requires an extra pad and another power supply, which results in increased silicon area and the cost of the whole system.

Threshold voltage of the pull-up PMOS device is also increased due to the body effect with non-zero body-to-source voltage (VDDH-VDD). Therefore, the n-well biasing circuit can be replaced with the dynamic n-well bias circuit as shown in Fig. 2.1 for providing appropriate body bias. Besides, a gate-tracking circuit is still needed to avoid the leakage current path induced by the incorrect conduction of the pull-up PMOS transistor.

Fig. 2.10 Mixed-voltage I/O buffer designed with dual-oxide devices and external n-well bias to prevent reliability issues.

The thick-oxide device with longer channel length can sustain higher gate-to-source and drain-to-source voltage and the thin-oxide device has higher driving capacity under same device dimension. Therefore, core circuits can be designed with thin-oxide devices to decrease the chip area and power consumption but the I/O circuits can be designed with thick-oxide devices to avoid the gate-oxide reliability issue. However, using dual-oxide process requires two masks in the fabrication of the circuit and extra cost.

2.4 P

D

IV

2.4.1 Basic Operation

To realize the I/O buffer by only thin-oxide devices without reliability issues, a

2xVDD-tolerant I/O buffer with two-stacked transistors is proposed in [20] and the concept is shown in Fig. 2.11. This design uses an extra tracking circuit to decide whether the I/O PAD is conducted to VDD or not. The tracking circuit with switch SW0 is used to speed up the voltage drop from 2xVDD to VDD at the I/O PAD when the I/O buffer is in transient state from receiving 2xVDD signal to transmit 0-V or VDD signal. A delay element is inserted between the PD port and the gate terminal of MN1 to let MN1 receive a delayed PD signal from the pre-driver.

During transition from receiving 2xVDD input signal to transmitting 0-V output signal, with the change of the enable signal OE from 0 V to VDD, the control signal VCTRL will turn on the switch SW0 to pull down I/O PAD to VDD. If the inserted delay is long enough, the I/O PAD is pulled down to VDD before the MN1 is turned on.

Fig. 2.11 Design concept to overcome the hot-carrier issue in the 2xVDD-tolerant I/O buffer with only two-stacked transistors [20].

The hot-carrier-prevented circuits (including the tracking circuit and switch) and delay element in this prior buffer are shown in Fig. 2.12, where other non-modified parts are

omitted. All bulks of PMOS transistors in the hot-carrier-prevented circuits are connected to the dynamic-biased n-well to avoid leakage paths. The switch SW0 is realized by the PMOS transistor MP7 with a tracking circuit controlled by the OE signal. Inverter chain and an additional capacitance are used to implement the delay element. The tracking circuit includes MP8, MP9, MN5, and a level shifter which shifts the voltage level of its input signal from 0-to-VDD swing to VDD-to-2xVDD swing. The corresponding voltages in steady states (transmit and receive modes) of the prior I/O buffer in Fig. 2.12 are listed in TABLE 2-1.

Fig. 2.12 The implementation of the hot-carrier-prevented circuit for 2xVDD-tolerant I/O buffer with two-stacked transistors.

TABLE 2.1

OPERATIONS OF PRIOR I/OBUFFER WITH HOT-CARRIER-PREVENTED CIRCUIT IN FIG.2.12

Modes OE I/O PAD V

Receive

0 V

0 V VDD

Receive 2xVDD 2xVDD

Transmit VDD X VDD

2.4.2 Prior Design IV with Reliability Concern

With drain voltage drops earlier and the source voltage drops later than the original design, the drain-to-source voltage of MN0 during such transition is within VDD. In the receive mode and transmit mode, the switch SW0 must be kept off in all states except the high-to-low transition to avoid interfering the steady state operation of the I/O buffer. Hence, this prior circuit in Fig. 2.11 does not suffer serious hot-carrier degradation.

When the I/O buffer in Fig. 2.12 is at the transition from receiving 2xVDD input signal to transmitting 0-V output signal, the gate voltage of MN1 is initially kept at 0 V while the PD signal is changing from 0 V to VDD. In the meantime, the VCTRL is set to VDD by turning on MN5 with 2xVDD gate voltage. Consequently, MP7 is turned on to discharge the initial voltage of 2xVDD at the I/O PAD until the voltage at I/O PAD is pulled down to ~VDD. The gate voltage of MN1 is also pulled up to VDD after the delay from the inverter chain and pulls down the I/O PAD voltage to 0 V. Thus, the drain-to-source voltage of MN0 can be kept less than VDD during the transient states.

(a)

(b)

(c)

Fig. 2.13 Hot-carrier-prevented circuits (a) for MN0, (b) for MN3, and (c) for MN2 and MP2.

Fig. 2.14. Whole mixed-voltage I/O buffer with the hot-carrier-prevented circuits [17].

The hot-carrier-prevented circuits are shown in Fig. 2.13.By applying the structure in Fig.

2.13 to the corresponding node in Figs. 2.12, the 2xVDD-tolerant I/O buffer without suffering serious reliability issues is shown in Fig. 2.14.

2.4.3 Discussion for Prior Design IV

Although prior design IV solves the serious hot-carrier degradation and gate-oxide overstress problems, it requires larger area to adopt the hot-carrier prevented circuits to the corresponding nodes. The VDDH voltage used in the level shifter also contributes to extra power and chip area. If the bulk voltage of each PMOS transistors in the hot-carrier prevented circuit is biased by the dynamic n-well circuit, the effective capacitance in the floating n-well point will be much larger which will increase the power consumption in the received mode since the VDD to 2xVDD swing in the n-well biasing circuit indicates that the effective large capacitor in the N-well is charged to 2xVDD or discharged to VDD by received signal continually. Tape buffers are usually inserted between the ideal pulse signal and the I/O PAD to provide a more practical input to I/O buffer. However, the HSPICE-simulated results of

power consumption for I/O buffer in the receive mode in HSPICE simulation is probably not so confident since merely inserting the tape buffer can not represent the real situation happens in I/O PAD in receive mode. This prior art is complex to realize reliability problem prevented

power consumption for I/O buffer in the receive mode in HSPICE simulation is probably not so confident since merely inserting the tape buffer can not represent the real situation happens in I/O PAD in receive mode. This prior art is complex to realize reliability problem prevented