New Proposed Blocks

The new proposed 2xVDD-tolerant I/O buffer realized with only 1xVDD devices to prevent transistors against gate-oxide overstress and hot-carrier degradation is shown in Fig.

3.1, which keeps the significant design advantages of the prior arts with three additional new modifications. The design concepts of the major parts in this new proposed I/O buffer are introduced in the following.

Fig. 3.1 New proposed 2xVDD-tolerant I/O buffer realized with only 1xVDD devices to prevent transistors against gate-oxide overstress and hot-carrier degradation.

A. Circuit Operation

The basic structure for this mixed-voltage I/O buffer typically includes a pre-driver, a dynamic n-well bias circuit, two or three-stacked transistors, gate-tracking circuit, and an input stage unit, which is controlled by an enable signal OE. The circuit operating modes include a receive mode (for receiving input signal from I/O PAD) and a transmit mode (for transmitting output signal to I/O PAD). The corresponding steady-state circuit operating voltages in the proposed 2xVDD-tolerant I/O buffer circuit in Fig. 3.1 are listed in TABLE 2.1 in section 1.3.

B. Gate Control Circuit

Dynamic floating n-well technique is applied to the mixed-voltage I/O circuit to prevent the possible leakage current path in the PMOS transistors of the pull-up network. By surveying the voltage waveform of the floating n-well, the floating n-well voltage is kept at VDD on one hand in receiving 0-V input signal from I/O PAD and in transmit mode. On the other hand, it is kept at 2xVDD for receiving input signal of 2xVDD from the I/O PAD. Such a voltage level at the floating n-well presents a similar function to the gate control signal for the top transistor (MN5 and MN6) of the three-stacked NMOS structures in Fig. 2.5.

Therefore, the new gate control circuit of these transistors can be directly implemented by the dynamic floating n-well self-biased circuit to save silicon area.

C. Transmitting Circuit

The new transmitting circuit applies the “stacked” concept in both PMOS and NMOS transistors appropriately to create a new “stacked transmission gate.” As shown in Fig. 3.1, the gate terminal of MN2 is connected to VDD and the gate terminal of MN7 is connected to the floating n-well terminal, so are MN5 and MN6. Aside from NMOS transistors, the gate terminals of other two PMOS transistors, MP2 and MP7, are connected together to the drain

terminal of MN6. In the transmit mode, the transistors MN7 and MP7 serve as a transmission gate (similar to MN2 and MP2). When receiving an input signal of 2xVDD at I/O pad, transistors MP2 and MP7 are turned off and the transistors MN7 and MN2 prevent high drain-to-source voltage (Vds). During the transition from receiving an input signal of 2xVDD to transmitting an output signal of VDD, the drain voltage of transistor MN2 keeps at 2xVDD -ΔV initially due to the diode-connected transistor MN7 (where ΔV is the Vds of the diode-connected transistor MN7). Then, it keeps a lower Vds across MN2 and MP2 when the source voltage of MN2 starts to be pulled down to 0 V. Due to the lower Vds of the stacked structures, the mentioned hot-carrier degradation problem in the transmission gates of Fig. 2.1 and Fig. 2.5 does not happen in this new design. Moreover, since the gate voltage of MP2 and MP7, and the drain and source terminals of MN7 are pulled down to 0 V while the gate terminal of MP0 is pulled down to 0 V, the gate-to-source voltages and the gate-to-drain voltages of MN7, MP7, MN2 and MP2 keep in a safe region (around or lower than VDD).

Thus, the new transmitting circuit does not suffer hot-carrier degradation and gate-oxide overstress problems.

D. Modification to Prevent Gate-Oxide Overstress

In Fig. 2.1, the gate terminal and the source terminal of transistor MP5 are connected to the drain terminal and the source terminal of MN0, respectively. In Fig. 2.5, the gate terminal and the source terminal of the MP1 are connected to the source terminal of MN0 and the drain terminal of MN5, respectively. During the transition from receiving an input signal of 2xVDD to transmitting an output signal of 0 V, transistor MN0 in Fig. 2.1 suffers hot-carrier degradation and the voltage difference between the drain terminal of MN5 and the source terminal of MN0 in Fig. 2.5 is much larger than VDD, therefore transistor MP5 in Fig. 2.1 and transistor MP1 in Fig. 2.5 also suffer gate-oxide reliability problem.

To solve such a problem, the gate terminal of MOS transistor can be connected to an

appropriate node instead of the original one, which is the source terminal of MN0 in Fig. 2.1 and Fig. 2.5. In Fig. 3.1, the appropriate point is realized by the additional connection of a PMOS transistor and an NMOS transistor. Transistor MN8 provides similar function as transistor MN0 with smaller size, and transistor MP8 works similarly as transistor MP5. With the similar structure, the gate terminal of transistor MP1 receives similar voltage as that of transistor MP1 in previous design. In the receive mode, the gate voltage of transistor MP1 is conducted to VDD (for 2xVDD input signal from I/O PAD) or 0 V (for 0-V input signal from I/O PAD) by transistor MN8 and MP8, respectively. In the transmit mode, the gate voltage is conducted to 0 V or VDD as the drain terminal of transistor MN1 does. However, since the gate terminal of transistor MP1 does not drop to ground as immediately as the drain terminal of transistor MN1 does, large |Vgs| value does not occur in transistor MP1. The gate voltage of transistor MP1 is pulled down gradually by MN8 and the other NMOS transistors when transition from receiving 2xVDD input signal to transmitting 0-V output signal. Thus, the new proposed design does not suffer gate-oxide reliability problem in both steady state and transient state.