I/O BUFFER BASICS - 抑制熱載子劣化效應與閘極氧化層過壓之混合電壓輸入輸出緩衝器設計

Chapter 1 Introduction

1.3 I/O BUFFER BASICS

The basic structure for mixed-voltage I/O buffer typically includes a pre-driver, several large transistors to charge or discharge the output terminal, and an input unit, as shown in Fig.

1.1. The circuit operating modes controlled by an enable signal EN include a receive

Fig. 1.1 Conventional tri-state I/O buffer used to transmit 0-to-VDD output signal or to receive 0-to-2xVDD input signal.

mode (for receiving an input signal) and a transmit mode (for transmitting an output signal corresponding to the data signal Dout). However, the conventional structure suffers reliability problems such as gate-oxide overstress, hot-carrier degradation, and leakage paths from I/O pad to the VDD through the drain to source and drain to bulk (parasitic pn junction) of the main driving PMOS transistor. Several designs had been proposed to solve such issues [8] to [10].

To solve the leakage problem from the I/O PAD to VDD through the parasitic pn junction in the PMOS transistor, gate-tracking and dynamic N -well bias voltage techniques had been adopted in the prior arts [8]-[10], as shown in Fig. 1.2. Placing NMOS and PMOS transistors appropriately is also an important key to solve the overstress problem. The corresponding circuit operating voltages in the 2xVDD-tolerant I/O buffer in Fig. 1.2 are listed in Tab 1.1.

Fig. 1.2 Basic schematic for mixed-voltage I/O buffer realized with only thin-oxide devices.

TABLE 1.1

BASIC OPERATIONS OF 2XVDD-TOLERANT I/O BUFFER IN STEADY STATE

1.4 H

-

CARRIER

D

EGRADATION

C

ONCERN

1.4.1 Mechanism

When the MOSFET devices feature extremely short channel length and high electrical field in deep-submicron technologies, hot-carrier degradation problem becomes more critical in reliability design. The mechanism of hot-carrier effect can be simply illustrated by a typical enhancement-mode n-channel MOS transistor, as shown in Fig. 1.3. With positive stress on gate and drain terminals, the electrons traveling from the source to drain gain kinetic energy while expensing electrical potential energy. When high lateral electrical field appears across drain and source terminals, electrons continually increase instant velocity and become “hot”

while the average velocity saturates [11]. “Hot carriers,” including both hot electrons and hot holes but mainly hot electrons due to the larger mobility and lower interface energy barrier, can create secondary electron and hole pairs by impact ionization [12]. Collecting the secondary electrons at bulk terminal and hot electrons at drain terminals increases the value of substrate current

Operating Modes

Signals at I/O

PAD PU PD Voltage Level of the

Floating N-well

Receive Low (0 V) VDD 0 VDD

Receive High (2xVDD) VDD 0 2xVDD

Transmit Low (0 V) VDD 0 VDD

Transmit High (VDD) 0 VDD VDD

Fig. 1.3 The mechanism of hot-carrier effect depicted of a typical enhancement-mode n-channel MOS transistor.

(Isub) and drain current (Id). When high-energey electrons tunnel into the oxide, the effective gate resistance (Rg) is reduced. Generated hot carriers can also cause time-dependent shifts threshold and conveyed conductance by rupturing the Si-H bonds. More detailed, hot-carrier injection can be subdivided into four categories as listed in TABLE 1.2 [5]. Since the life time of devices, the correctness of expected operations and the performance of circuits are affected by hot carrier injection as deign parameters vary with time, it makes hot-carrier effect a non-ignorable issue, especially in design of robust mixed-voltage interface circuit in nanoscale CMOS process.

TABLE 1.2

HOT CARRIER INJECTION MECHANISM AND RELATED EFFECT

Injection Type Condition Related effect

Drain avalanche hot carrier 2. Shift of conductance (gm).

3. Space charge or gate current

4. Substrate’s drift current (may disturb current flow and ease latchup) Channel hot electron

injection (CHE)

VD≈VG 1. Space charge or gate current

Substrate hot electron injection (SHE)

|VB|>>0 1. Trapped charge or gate current 2. Carriers flow from substrate to oxide

Secondary generated hot

Similar to DAHC but influenced by an extra field due to the bias voltage of substrate.

1.4.2 Lifetime Issue

Tests for the dependence of hot-carrier degradation on the device sizes had been reported in [13]. Worst stress condition of the peak substrate current (Vd=2xVg) and Vd=Vg are often seen in the tests and parameters as the degradation of the saturation drain current, ΔId/Id, Δgm/gm and ΔVth/Vth are often measured as a reference for the lifetime extrapolation in different processes.

The degradation caused by hot carriers deeply relies on the length and the biasing conditions of the device [14]. In the worse-case condition of the gate-to-source voltage (Vgs), which means the transistor is in saturation region with large drain current, the drain-to-source

Fig. 1.4 Channel-hot-carrier lifetime as a function of Vds and Vgs (typical behavior for 0.25-μm CMOS process)

voltage (Vds) and life time (τ) typically has an exponential relationship of:

τ

^life

= A exp( − B V /

^ds

)

(1.1)

,where A and B are constants, which are process-dependent.

The relationship of lifetime and the length of device are also expressed as equation 1.2:

τ

^life

∝ L

(1.2)

,where C is a constant equals 1~5.

The channel length tends to have weaker effect compared with the Vds to lifetime. The relationship of lifetime and gate-to-source voltage is more complex. When the transistor is at

“off” state or linear region with very high gate-to-source voltage, only little current flows in the channel and very few hot carriers are generated.

The lifetime versus drain-to source voltage (Vds) and gate-to-sourse voltage (Vgs) are depicted in Fig. 1.3 [14]. Generally, to ensure a 5~10 year life time with gate-to-source voltage (Vgs) = 0.5~1 times of power supply voltage (VDD), the drain-to-source voltage (Vds) must be kept within 1~1.1 times of power supply voltage (VDD).

1.4.3 Techniques to Increase Robustness of Circuits against Hot-carrier Degradation

Several techniques can probably be adopted in circuits to eliminate the circuit performance deterioration caused by hot-carrier effect include:

1. Methods with process modification

(1) N+ / N- double diffusion of sources and drains (2) Graded drain junctions such as LDD structure

(3)Self-aligned n- regions between the channel and the n+ junctions to create an offset gate

(4) Buried p+ channels.

2. Methods without process modifications:

(1) Different aspect ratios for the two transistors.

(2) Longer channel length.

(3) Non-stationary gate voltage.

(4) More stacked transistors.

In this thesis, floating n-well biasing voltage is used to provide the appropriate control voltage and reduce the number of transistors. The concept of stacked transistors technique is also adopted on transmission gate to suppress hot-carrier degradation.

1.5 G

ATE

-O

XIDE

O

VERSTRESS

P

ROBLEM

With the advantages in speed, power and cost, thin-oxide devices are more suitable in high-speed and low-power applications. However, thin gate oxide with large gate-to-source voltage is vulnerable to gate-oxide breakdown. The breakdown can happen instantaneously or over time [15], [16]. The lifetime of gate oxide over the voltage stress can be expressed as equation 1.3 [15].

,where τ0and G are two constants, Xeff is the effective thickness of the gate oxide due to the defeats, and Vox(t) is the time-dependent voltage across the gate oxide. As expressed in equation 1.3, the accumulation of the voltage stress over time determines the gate-oxide breakdown. Thus, the damage caused by transient overstress is still non-ignorable if it happens frequently and lasts for enough time.

In addition to the consideration of hot-carrier degradation, the absolute value of gate-to-source and gate-to-drain voltage should be less than the supply voltage and the drain-to-source voltage in NMOS devices and source-to-drain voltage in PMOS devices must be less than the supply voltage when devices work in “on” state.

1.5 B

RIEF

I

NTRODUCTION OF

PCI-X

The operating frequency used in the simulation of the new proposed I/O buffer is 133 MHz, which is the specification of PCI-X application.

PCI-X, the initial of “Peripheral Component Interconnect Extended,” is the standard for the computer bus and expansion card jointly developed by IBM, HP and Compaq [17]-[18].

With higher data width, PCI-X is an improved version of PCI for higher throughput. Such a

standard is required in some devices such as gigabit ethernet cards, fibre Channel, ultra 320 SCSI controllers, and cluster interconnects. Four frequency grades for cards or slots based on PCI-X standard are 66 MHz, 133 MHz, 266 MHz, and 533 MHz. For both PCI-X 1.0 and PCI-X 2.0, 133 MHz is included in the specifications and is most common in applications.

Thus, 133 MHz is a suitable operating frequency for I/O buffer design with the expectation to be applied to the interface circuit.

Chapter 2 Prior I/O Buffers with 2xVDD Tolerance

In this chapter, three 2xVDD tolerant mixed-voltage I/O buffers ([14], [19], and [20]) and I/O buffers with dual-oxide devices are retrospected before the section of new proposed I/O buffer.

[19] was designed with eliminated reliability problems in steady state but suffers hot-carrier degradation and gate-oxide overstress problem in transient state. [14] proposed a technique which can be used to solve the hot-carrier degradation problem in stacked NMOS or PMOS transistors but it was unable to solve transient hot-carrier degradation and gate-oxide overstress happening in some transistors completely.

To realize an I/O buffer with 1.8/3.3/5-V mixed-voltage tolerance without reliability issues, 0.35-μm devices had been used in [21] and the voltage differences are kept within the supply voltage of 3.3 V. Dual-oxide (thick-oxide and thin-oxide) processes [22]-[24] had been used to prevent reliability issues in mixed-voltage in I/O buffers. Using two kinds of devices (such as 1-V and 2.5-V devices) had also been adopted in [25] to transmit 3.3-V signals without reliability issue. However, using two masks increases the cost in the fabrication.

To eliminate hot-carrier degradation and gate-oxide overstress problems in prior circuits, [20] and this work [7] are proposed. [20] will be also introduced in this chapter, and will be compared with the new proposed I/O buffer in later section.

2.1 P

RIOR

D

ESIGN

I

2.1.1 Basic Operation

A conventional mixed-voltage I/O buffer with the gate-tracking circuit and the dynamic n-well bias circuit is shown in Fig. 2.1 [19]. With the new dynamic n-well bias circuit (composed of transistor MP4 and MP6) and gate-tracking circuit (composed of transistor MN2 to MN4, transistor MP2, MP3 and MP5), this conventional I/O buffer was realized with only the thin gate-oxide devices, and it occupied smaller silicon area than the prior designs [8]-[10]. When the control signal OE is at VDD (logic “1”), the I/O buffer is operated in the transmit mode. The PD port from the pre-driver circuit is directly connected to the gate terminal of the pull-down NMOS device, MN1. The PU port of the pre-driver circuit is connected to the gate terminal of the pull-up PMOS device, MP0, through the gate-tracking circuit. According to the signal Dout controlled by the internal circuits of the IC and the turned on of transmission gate MN2

Fig. 2.1 The conventional mixed-voltage I/O buffer designed with gate-tracking circuit and dynamic n-well bias circuit to solve gate-oxide reliability issue [19].

and MP2, the PU signal and PD signal control the driving NMOS or PMOS transistors to charge I/O PAD to VDD or discharge I/O PAD to 0 V, respectively. At that time, MP4 is also

turned on to bias the floating n-well to VDD so the pn-junction diodes in transistors MP0 and MP4 are reverse biased to eliminate leakage current. When the I/O buffer is operated in the receive mode with OE signal biased at 0 V, the PU and PD ports of the pre-driver circuit are kept at VDD and 0 V, respectively. Thus, transistors MP0 and MN1 are turned off. The Din signal rises or falls according to the received signal at the I/O PAD. Transistor MP3 is used to track the signal at the I/O PAD to the gate voltage of transistor MP0 to prevent the undesired leakage current from the I/O PAD to the power supply (VDD) through the pull-up PMOS device MP0. When the voltage level at the I/O PAD exceeds VDD+|Vtp| and rise to 2xVDD, transistor MP3 is turned on to turn off transistor MP0 to prevent the leakage current through its drain to source. Transistor MP4 is also turned off while transistor MP6 is turn on to bias the floating n-well at 2xVDD to reverse bias the parasitic pn-junction diode for eradicating leakage current from the I/O PAD to VDD. Besides, MP2 is also turned off due to the turned on of transistor MP5 to eliminate the conductance and leakage current from the I/O PAD to the PU port. The input signal from the I/O PAD is transferred to the internal node Din by MN0, MP1, inverter INV1 and INV2. MN0 is used to decrease the received voltage level at the drain of MN1. Because the gate terminal of MN0 is connected to VDD, the input voltage of inverter INV is limited to VDD-Vtn when the voltage level at the I/O pad is 2xVDD.

However, MP1 turns on while the input node of inverter INV1 rises over the threshold to pull down the output node of inverter INV1 to 0 V. Thus, the drain voltage of transistor MN1 is kept at VDD and the signal at the I/O pad can also be successfully received by the internal input node Din.

2.1.2 Prior Design I with Reliability Concern

Mixed-voltage I/O buffer in Fig. 2.1 can tolerate 2xVDD input signal at the I/O PAD without suffering gate-oxide reliability, hot-carrier degradation, and undesired circuit leakage

in the steady state. However, during the transition from receiving 2xVDD input signal to transmitting 0-V output signal, MN0 and MN3 suffer hot-carrier degradation problem. MP5 also suffers gate-oxide reliability problem. Moreover, MN2, MP2, and MN3 also suffer hot-carrier degradation problem during the transition from receiving 2xVDD input signal to transmitting VDD output signal.

The limitations for the gate-to-source voltage and drain-to-source voltage of the transistors mentioned in the end of chapter 1 are followed in some prior arts as Fig. 2.1 in steady state. However, during the transition from receiving 2xVDD input signal to transmitting 0-V output signal, the drain-to-source voltage (Vds) of MN0 and MN3 will be much higher than VDD. The reason is that the drain-to-source voltage starts to increase from VDD since the source terminal is pulled down faster than the drain terminal at the beginning of this transition. MP5 also has larger Vgs since its source and gate are connected to the drain and source of MN0. Moreover, MN2, MP2, and MN3 also come across similar problem during the transition from receiving 2xVDD input signal to transmitting VDD output signal.

While PU signal is suddenly pulled down from VDD to 0, the drain terminal of MN2 are pulled down much slower since the transistors are turned on accordingly and it also takes time for the gate terminal of MP2 to be pulled down from 2xVDD to turn on MP2. The above mentioned transient situations for MN0, MN3, MP5, MN2, and MP2 with high voltage across drain and source terminals are verified by HSPICE simulation results in a 0.13-μm CMOS technology with 1.2-V VDD and 2.5-V 2xVDD. As shown in Fig. 2.2, Fig. 2.3(a), (b), and Fig. 2.4, Vds of MN0 (also the Vsg of MP1), MN3, MN2, and MP2 are much larger than VDD during a certain time. The peak values are 1.96 V, 2.11 V, 2.09 V, and 2.07 V respectively. Thereby, it results in serious hot-carrier degradation or gate-oxide overstress in the transition from receiving 2.5-V input signal to transmitting 0-V or 1.2-V output signal.

Fig. 2.2 Drain-to-source voltage (Vds) of MN0 (and also the source-to-gate voltage (Vsg) of transistor MP5) in Fig. 2.1 during the transition from receiving 2xVDD input signal to transmitting 0-V output signal.

(a)

(b)

Fig. 2.3. Drain-to-source voltage (Vds) of transistor MN3 in Fig. 2.1 (a) during the transition from receiving 2xVDD input signal to transmitting 0-V output signal and (b) during the transition from receiving 2xVDD input signal to transmitting VDD output signal.

Fig. 2.4. Drain-to-source voltage (Vds) of MN2 (source-to-drain voltage (Vsd)) of MP2 in Fig. 2.1 during the transition from receiving 2xVDD input signal to transmitting VDD output signal.

2.2 P

RIOR

D

ESIGN

II

2.2.1 Basic Operation

To solve the hot-carrier degradation problems happened in some prior arts as Fig. 2.1, a technique with three or more stacked NMOS transistors and related PMOS transistors as gate control circuits had been reported in [14]. A modified 2xVDD-tolerant I/O buffer with this technique to eliminate hot-carrier issue is shown in Fig. 2.5 with similar steady state operation as listed in TABLE 1.1. When the I/O buffer receives 2xVDD input signal, the gate terminal of MN5 and MN6 are biased at 2xVDD through MPT1 and MPT3, respectively. On the other hand, the gate terminal of transistor MN5 and MN6 are biased at VDD if a VDD signal is transmitted or a 0-V signal appears at the I/O PAD whether received or transmitted.

Fig. 2.5. Modified mixed-voltage I/O buffer designed with three-stacked transistors to prevent hot-carrier degradation [14].

2.2.2 Prior Design Ⅱ with Reliability Concern

During the transition from receiving 2xVDD input signal to transmitting 0-V output signal, the source terminal of MN5 and MN6 are biased at 2xVDD-ΔV initially (where ΔV is the Vds of the diode-connected transistors) because of their diode connected structure.

Meanwhile, the source terminal of MN0 and MN3 are pulled down by MN1 and MN4 in a 0.13-μm technology, respectively. Comparing the MN0 and MN3 in Fig. 2.1 with the same transistors in I/O buffer in Fig. 2.5 during this transient time, the transistors in I/O buffer in Fig. 2.5 have smaller Vds since the drain voltage is initially smaller by –ΔV.

Fig. 2.6, Fig. 2.7(a), (b), Fig. 2.8 and Fig. 2.9 are the HSPICE simulation results using 0.13-μm CMOS technology when VDD is 1.2 V. With smaller maximum of Vds, the I/O buffer in Fig. 2.5 can almost eliminate most serious hot-carrier degradation happened in previous designs, as shown in Fig. 2.6, Fig. 2.7(a), and (b). However, the gate-oxide

overstress still happens in MP1 in Fig. 2.5 during the transition from receiving 2xVDD to transmitting 0 V, as shown in Fig. 2.8. Also, the transmission circuit (with MN2 and MP2 in Fig. 2.5) still suffers the hot-carrier degradation, as shown in Fig. 2.9.

Fig. 2.6. Drain-to-source voltage (Vds) of MN0 in Fig. 2.5 during the transition from receiving 2xVDD input signal to transmitting 0-V output signal.

(a)

(b)

Fig. 2.7. Drain-to-source voltage (Vds) of MN3 in Fig. 2.5 during the transition from receiving 2xVDD input signal (a) to transmitting 0-V output signal and (b) to transmitting VDD output signal.

Fig. 2.8. Source-to-gate voltage (Vsg) of MP1 in Fig. 2.5 during the transition from receiving 2xVDD input signal to transmitting 0 output signal

Fig. 2.9. Drain-to-source voltage (Vds) of MN2/MP2 in Fig. 2.5 during the transition from receiving 2xVDD input signal to transmitting VDD output signal.

2.3 P

RIOR

D

ESIGN

III

Using dual-oxide (thick-oxide and thin-oxide) process [22]-[24] provided by foundry is also a method to eliminate reliability issues as gate-oxide overstress and hot-carrier degradation in mixed-voltage I/O buffers. From equation 1.2 and 1.3, increasing channel length and gate-oxide thickness leads to increased tolerance of absolute drain-to-source and gate-to-source voltage are increased. With such a characteristic, thick-oxide devices with longer channel length are more robust than the thin-oxide device and can be used to sustain large drain-to-source or gate-to-source voltage. For example, [21] used 0.35-μm devices with voltage differences kept within the supply voltage of 3.3 V to realize an I/O buffer with 1.8/3.3/5-V mixed-voltage tolerance without reliability issues. Two kinds of devices (1-V and 2.5-V transistors) had been also adopted in [25] to output 3.3-V signal without aforesaid issues.

In the 2xVDD tolerant I/O buffer, Fig. 2.10 shows the mixed-voltage I/O buffer with dual-oxide (thick-oxide and thin-oxide) devices. An external n-well bias voltage is also connected to the body terminal of the pull-up PMOS device in the I/O buffer to avoid leakage current path from the I/O pad to the power supply (VDD) through the parasitic drain-to-well pn-junction diode. However, adding an external bias voltage VDDH requires an extra pad and another power supply, which results in increased silicon area and the cost of the whole system.

Threshold voltage of the pull-up PMOS device is also increased due to the body effect with non-zero body-to-source voltage (VDDH-VDD). Therefore, the n-well biasing circuit can be

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