Chapter 3 Design of Mixed-Voltage I/O Buffer with
3.1 NEW DESIGN: A MIX-VOLTAGE I/O BUFFER WITH NEW
3.1.2 Simulation Results
A. Simulated Waveform for Steady State Operation and Verification to New Modifications
The simulated results of the new proposed 2xVDD-tolerant I/O buffer to prevent hot-carrier degradation and gate-oxide reliability have been verified by the HSPICE simulation in a 0.13-μm CMOS model with VDD of 1.2 V. Fig. 3.2 and Fig. 3.3 show the simulated waveforms of the new proposed 2xVDD-tolerant I/O buffer well operating with speed of 150 MHz in the receive mode and transmit mode, respectively. As shown in Fig. 3.2, when new proposed mixed-voltage 2xVDD I/O buffer receives 0-V and 2.5-V signal from I/O PAD, it successively outputs 1.2-V and 0-V Din signal with N-well voltage biased at 1.2 V
and 2.5 V respectively. In Fig. 3.3, as Dout signal varies between 1.2 V and 0 V, new proposed I/O buffer transmits similar swing to I/O PAD accordingly and N-well voltage keeps near 1.2 V.
Fig. 3.4 shows the Vds of MN0 in the new proposed I/O buffer from receiving 2.5-V input signal to transmitting 0-V output signal. Fig. 3.5(a) and (b) shows the Vds of MN3 in the new proposed I/O buffer from receiving 2.5-V input signal to transmitting 0-V or VDD output signal, respectively. Comparing Fig. 3.4, Fig. 3.5(a) and (b) with previous figures (Fig.
2.2, Fig. 2.3(a), (b), Fig. 2.6, Fig. 2.8(a) and (b)) correspondingly, MN0 and MN3 in Fig. 2.1 suffer serious hot-carrier degradation problem due to the larger Vds. Since the drain-to-source voltage of MN0 and MN3 are nearly the same for the new buffer shown in Fig. 3.1 and the buffer shown in Fig. 2.5, the capabilities of preventing hot-carrier degradation when receiving 2.5-V input signal are almost the same between these two buffers (Fig. 2.5 and Fig. 3.1).
However, the new buffer is more efficient in area saving.
Fig. 3.2 Simulated waveforms of the proposed mixed I/O buffer (this invention) operating at 150 MHz when receiving 2.5-V to 0-V input signals at I/O PAD.
Fig. 3.3 Simulated waveforms of the proposed mixed I/O buffer (this invention) operating at 150 MHz when transmitting 1.2-V to 0-V output signals at I/O PAD.
Fig. 3.4 The drain-to-source voltage (Vds) of MN0 in the new proposed I/O buffer during the transition from receiving 2xVDD input signal to transmitting 0-V output signal.
(a)
(b)
Fig. 3.5 The drain-to-source voltage (Vds) of MN3 in the new proposed I/O buffer during the transition from receiving 2xVDD input signal (a) to transmitting 0-V output signal and (b) to transmitting VDD output signal.
Fig. 3.6 shows the Vds waveforms of the transistors in the transmitting circuit of the new proposed I/O buffer from receiving 2.5-V input signal to transmitting 1.2-V output signal.
As shown in Fig. 3.6, the transistors in the new proposed I/O buffer have lower drain-to-source voltage, which is more robust to prevent hot-carrier degradation.
Fig. 3.6 The drain-to-source voltage (Vds) of transistors in the new transmitting circuits of new proposed buffer during the transition from receiving 2xVDD input signal to transmitting VDD output signal.
Fig. 3.7 shows the gate-to-source voltages of transistor MP1 in the new proposed I/O buffer. The peak |Vgs| value of similar PMOS in the prior designs is larger than VDD of 1.2 V as shown in Fig. 2.2 and Fig. 2.8. However, the Vgs of MP1 in the proposed I/O buffer is close to VDD, which is confirmed more robust than the previous designs in both hot-carrier degradation and gate-oxide reliability.
Fig. 3.7 The gate-to-source (Vgs) voltage across transistor MP1 in the new proposed I/O buffer during the transition from receiving 2.5-V to transmitting 0-V output signals.
B. Power Performance of The New Proposed I/O Buffer and Prior Arts
The power consumption is compared as listed in TABLE 3.1 to TABLE 3.2 with 0.13-μm CMOS model and adopts average current of the supply voltage as reference. The temperature is set at 85℃, 25℃ and 50℃ under Typical Typical (TT) corner simulation. The output loading capacitor is 10 pF. According to the simulated results in transmit mode and in the listed two transient states, the average current of the supply voltage is near among the three buffers but the new buffer is slightly less than the other two prior arts in transmit mode.
In the receive mode, the power consumption without consideration the extra received power from I/O PAD of the new buffer is larger than the two prior arts. Another comparison is done by changing the temperature to 25℃ and 50℃ in the steady state as listed in TABLE 3.3 and TABLE 3.4, respectively. Thus, the new buffer has better power performance when operating in transmit mode and more robust in the transient states.
TABLE3.1
COMPARISON IN AVERAGE CURRENT OF THE SUPPLY VOLTAGE AMONG TWO PRIOR ARTS AND
NEW PROPOSED I/OBUFFER IN STEADY STATE AT 85℃
Mixed-voltage I/O designs Receive mode Transmit mode
Prior art in Fig. 2.1 [7] 0.68uA 2.98mA
Modified I/O buffer in Fig. 2.5 13.8uA 2.94mA
This work 95.6uA 2.7mA
TABLE3.2
COMPARISON IN AVERAGE CURRENT OF THE SUPPLY VOLTAGE AMONG TWO PRIOR ARTS AND
NEW PROPOSED I/OBUFFER IN CERTAIN TRANSIENT STATE AT 85℃
Mixed-voltage I/O designs From receive 2.5 V to transmit 0 V
From receive 2.5 V to transmit
1.2 V
Prior art in Fig. 2.1 [7] 24.4uA 0.136mA
Modified I/O buffer in Fig. 2.5 27.1uA 0.134mA
This work 26.37uA 0.135mA
TABLE3.3
COMPARISON IN AVERAGE CURRENT OF THE SUPPLY VOLTAGE AMONG TWO PRIOR ARTS AND
NEW PROPOSED I/OBUFFER IN STEADY STATE AT 25℃
Mixed-voltage I/O designs Receive mode Transmit mode
Prior art in Fig. 2.1 [7] 9.75uA 2.91mA
Modified I/O buffer in Fig. 2.5 22.55uA 2.89mA
This work 72.22uA 2.63mA
TABLE3.4
COMPARISON IN AVERAGE CURRENT OF THE SUPPLY VOLTAGE AMONG TWO PRIOR ARTS AND
NEW PROPOSED I/OBUFFER IN CERTAIN TRANSIENT STATE AT 50℃
Mixed-voltage I/O designs From receive 2.5 V to transmit 0 V
From receive 2.5 V to transmit
1.2 V
Prior art in Fig. 2.1 [7] 3.94uA 2.94mA
Modified I/O buffer in Fig. 2.5 19.85uA 2.92mA
This work 83.06.uA 2.66mA
C. Rise Time, Fall Time and Propagation Delay of The New Proposed I/O Buffer and Prior Arts
TABLE 3.5 and TABLE 3.6 show the comparison results of the rise time (tr), fall time (tf) and the propagation delay (from high to low: tphl, from low to high: tplh, and the half average of tphl and tplh: tp) of the new proposed I/O buffer and the two prior arts. The fall time and propagation delay of the modified I/O buffer in Fig. 2.5 are slightly longer than the new proposed design and the prior art in Fig. 2.1. The reason is attributed to the additional output loading due to MPT1 and MPT0 in Fig. 2.5. Since the prior art in Fig. 2.1 uses two-stacked NMOS transistors instead of tri-stacked NMOS transistors, the effected output loading of at I/O PAD is slightly smaller than the new proposed buffer and the modified I/O buffer in Fig. 2.5. However, since the capacitor at the I/O PAD in simulation for the effective output loading, 10 pf, is the dominant part, the transition performance including rise time, fall time, and propagation delay are not significant among the three circuits.
.
TABLE3.5
COMPARISON ON RISE AND FALL TIME OF THE POWER SUPPLY VOLTAGE (VDD) AMONG TWO
PRIOR ARTS AND NEW PROPOSED I/OBUFFER IN STEADY STATE AT 85℃
Mixed-voltage I/O designs
Receive mode Transmit mode
tr tf tr tf
Prior art in Fig. 2.1 [7] 0.71 ns 0.83 ns 0.4 ns 0.79 ns Modified I/O buffer in Fig. 2.5 0.71 ns 0.86 ns 0.4 ns 1.37 ns
This work 0.71 ns 0.9 ns 0.4 ns 0.65 ns
TABLE3.6
COMPARISON ON PROPAGATION DELAY OF THE SUPPLY VOLTAGE AMONG TWO PRIOR ARTS AND NEW PROPOSED I/OBUFFER IN STEADY STATE AT 85℃
Mixed-voltage I/O designs
Receive mode Transmit mode Tphl tplh tp tphl tplh tp
Prior art in Fig. 2.1 [7] 0.38 ns 0.45 ns 0.42 ns 0.65 ns 0.45 ns 0.55 ns Modified I/O buffer in Fig.2.5 0.42 ns 0.47 ns 0.45 ns 1.1 ns 0.46 ns 0.78 ns This work 0.39 ns 0.51 ns 0.45 ns 0.56 ns 0.48 ns 0.52 ns