PRIOR DESIGN IV: A MIX-VOLTAGE I/O BUFFER WITH

Chapter 2 Prior I/O Circuits with 2xVDD Tolerance

2.4 PRIOR DESIGN IV: A MIX-VOLTAGE I/O BUFFER WITH

2.4.1 Basic Operation

To realize the I/O buffer by only thin-oxide devices without reliability issues, a

2xVDD-tolerant I/O buffer with two-stacked transistors is proposed in [20] and the concept is shown in Fig. 2.11. This design uses an extra tracking circuit to decide whether the I/O PAD is conducted to VDD or not. The tracking circuit with switch SW0 is used to speed up the voltage drop from 2xVDD to VDD at the I/O PAD when the I/O buffer is in transient state from receiving 2xVDD signal to transmit 0-V or VDD signal. A delay element is inserted between the PD port and the gate terminal of MN1 to let MN1 receive a delayed PD signal from the pre-driver.

During transition from receiving 2xVDD input signal to transmitting 0-V output signal, with the change of the enable signal OE from 0 V to VDD, the control signal VCTRL will turn on the switch SW0 to pull down I/O PAD to VDD. If the inserted delay is long enough, the I/O PAD is pulled down to VDD before the MN1 is turned on.

Fig. 2.11 Design concept to overcome the hot-carrier issue in the 2xVDD-tolerant I/O buffer with only two-stacked transistors [20].

The hot-carrier-prevented circuits (including the tracking circuit and switch) and delay element in this prior buffer are shown in Fig. 2.12, where other non-modified parts are

omitted. All bulks of PMOS transistors in the hot-carrier-prevented circuits are connected to the dynamic-biased n-well to avoid leakage paths. The switch SW0 is realized by the PMOS transistor MP7 with a tracking circuit controlled by the OE signal. Inverter chain and an additional capacitance are used to implement the delay element. The tracking circuit includes MP8, MP9, MN5, and a level shifter which shifts the voltage level of its input signal from 0-to-VDD swing to VDD-to-2xVDD swing. The corresponding voltages in steady states (transmit and receive modes) of the prior I/O buffer in Fig. 2.12 are listed in TABLE 2-1.

Fig. 2.12 The implementation of the hot-carrier-prevented circuit for 2xVDD-tolerant I/O buffer with two-stacked transistors.

TABLE 2.1

OPERATIONS OF PRIOR I/OBUFFER WITH HOT-CARRIER-PREVENTED CIRCUIT IN FIG.2.12

Modes OE I/O PAD V

CTRL

Receive

0 V

0 V VDD

Receive 2xVDD 2xVDD

Transmit VDD X VDD

2.4.2 Prior Design IV with Reliability Concern

With drain voltage drops earlier and the source voltage drops later than the original design, the drain-to-source voltage of MN0 during such transition is within VDD. In the receive mode and transmit mode, the switch SW0 must be kept off in all states except the high-to-low transition to avoid interfering the steady state operation of the I/O buffer. Hence, this prior circuit in Fig. 2.11 does not suffer serious hot-carrier degradation.

When the I/O buffer in Fig. 2.12 is at the transition from receiving 2xVDD input signal to transmitting 0-V output signal, the gate voltage of MN1 is initially kept at 0 V while the PD signal is changing from 0 V to VDD. In the meantime, the VCTRL is set to VDD by turning on MN5 with 2xVDD gate voltage. Consequently, MP7 is turned on to discharge the initial voltage of 2xVDD at the I/O PAD until the voltage at I/O PAD is pulled down to ~VDD. The gate voltage of MN1 is also pulled up to VDD after the delay from the inverter chain and pulls down the I/O PAD voltage to 0 V. Thus, the drain-to-source voltage of MN0 can be kept less than VDD during the transient states.

(a)

(b)

(c)

Fig. 2.13 Hot-carrier-prevented circuits (a) for MN0, (b) for MN3, and (c) for MN2 and MP2.

Fig. 2.14. Whole mixed-voltage I/O buffer with the hot-carrier-prevented circuits [17].

The hot-carrier-prevented circuits are shown in Fig. 2.13.By applying the structure in Fig.

2.13 to the corresponding node in Figs. 2.12, the 2xVDD-tolerant I/O buffer without suffering serious reliability issues is shown in Fig. 2.14.

2.4.3 Discussion for Prior Design IV

Although prior design IV solves the serious hot-carrier degradation and gate-oxide overstress problems, it requires larger area to adopt the hot-carrier prevented circuits to the corresponding nodes. The VDDH voltage used in the level shifter also contributes to extra power and chip area. If the bulk voltage of each PMOS transistors in the hot-carrier prevented circuit is biased by the dynamic n-well circuit, the effective capacitance in the floating n-well point will be much larger which will increase the power consumption in the received mode since the VDD to 2xVDD swing in the n-well biasing circuit indicates that the effective large capacitor in the N-well is charged to 2xVDD or discharged to VDD by received signal continually. Tape buffers are usually inserted between the ideal pulse signal and the I/O PAD to provide a more practical input to I/O buffer. However, the HSPICE-simulated results of

power consumption for I/O buffer in the receive mode in HSPICE simulation is probably not so confident since merely inserting the tape buffer can not represent the real situation happens in I/O PAD in receive mode. This prior art is complex to realize reliability problem prevented circuit. When considering process-voltage-temperature (PVT) variation, the prior design IV may be affected more than prior art I, II and III. With the above concerns in prior design IV, a new 2xVDD tolerant mixed-voltage I/O buffer is proposed in the following chapter.

Chapter 3 Design of Mixed-Voltage I/O Buffer with Consideration of Hot-Carrier and Gate-Oxide Overstress

3.1 N

D

ESIGN

3.1.1 New Proposed Blocks

The new proposed 2xVDD-tolerant I/O buffer realized with only 1xVDD devices to prevent transistors against gate-oxide overstress and hot-carrier degradation is shown in Fig.

3.1, which keeps the significant design advantages of the prior arts with three additional new modifications. The design concepts of the major parts in this new proposed I/O buffer are introduced in the following.

Fig. 3.1 New proposed 2xVDD-tolerant I/O buffer realized with only 1xVDD devices to prevent transistors against gate-oxide overstress and hot-carrier degradation.

A. Circuit Operation

The basic structure for this mixed-voltage I/O buffer typically includes a pre-driver, a dynamic n-well bias circuit, two or three-stacked transistors, gate-tracking circuit, and an input stage unit, which is controlled by an enable signal OE. The circuit operating modes include a receive mode (for receiving input signal from I/O PAD) and a transmit mode (for transmitting output signal to I/O PAD). The corresponding steady-state circuit operating voltages in the proposed 2xVDD-tolerant I/O buffer circuit in Fig. 3.1 are listed in TABLE 2.1 in section 1.3.

B. Gate Control Circuit

Dynamic floating n-well technique is applied to the mixed-voltage I/O circuit to prevent the possible leakage current path in the PMOS transistors of the pull-up network. By surveying the voltage waveform of the floating n-well, the floating n-well voltage is kept at VDD on one hand in receiving 0-V input signal from I/O PAD and in transmit mode. On the other hand, it is kept at 2xVDD for receiving input signal of 2xVDD from the I/O PAD. Such a voltage level at the floating n-well presents a similar function to the gate control signal for the top transistor (MN5 and MN6) of the three-stacked NMOS structures in Fig. 2.5.

Therefore, the new gate control circuit of these transistors can be directly implemented by the dynamic floating n-well self-biased circuit to save silicon area.

C. Transmitting Circuit

The new transmitting circuit applies the “stacked” concept in both PMOS and NMOS transistors appropriately to create a new “stacked transmission gate.” As shown in Fig. 3.1, the gate terminal of MN2 is connected to VDD and the gate terminal of MN7 is connected to the floating n-well terminal, so are MN5 and MN6. Aside from NMOS transistors, the gate terminals of other two PMOS transistors, MP2 and MP7, are connected together to the drain

terminal of MN6. In the transmit mode, the transistors MN7 and MP7 serve as a transmission gate (similar to MN2 and MP2). When receiving an input signal of 2xVDD at I/O pad, transistors MP2 and MP7 are turned off and the transistors MN7 and MN2 prevent high drain-to-source voltage (Vds). During the transition from receiving an input signal of 2xVDD to transmitting an output signal of VDD, the drain voltage of transistor MN2 keeps at 2xVDD -ΔV initially due to the diode-connected transistor MN7 (where ΔV is the Vds of the diode-connected transistor MN7). Then, it keeps a lower Vds across MN2 and MP2 when the source voltage of MN2 starts to be pulled down to 0 V. Due to the lower Vds of the stacked structures, the mentioned hot-carrier degradation problem in the transmission gates of Fig. 2.1 and Fig. 2.5 does not happen in this new design. Moreover, since the gate voltage of MP2 and MP7, and the drain and source terminals of MN7 are pulled down to 0 V while the gate terminal of MP0 is pulled down to 0 V, the gate-to-source voltages and the gate-to-drain voltages of MN7, MP7, MN2 and MP2 keep in a safe region (around or lower than VDD).

Thus, the new transmitting circuit does not suffer hot-carrier degradation and gate-oxide overstress problems.

D. Modification to Prevent Gate-Oxide Overstress

In Fig. 2.1, the gate terminal and the source terminal of transistor MP5 are connected to the drain terminal and the source terminal of MN0, respectively. In Fig. 2.5, the gate terminal and the source terminal of the MP1 are connected to the source terminal of MN0 and the drain terminal of MN5, respectively. During the transition from receiving an input signal of 2xVDD to transmitting an output signal of 0 V, transistor MN0 in Fig. 2.1 suffers hot-carrier degradation and the voltage difference between the drain terminal of MN5 and the source terminal of MN0 in Fig. 2.5 is much larger than VDD, therefore transistor MP5 in Fig. 2.1 and transistor MP1 in Fig. 2.5 also suffer gate-oxide reliability problem.

To solve such a problem, the gate terminal of MOS transistor can be connected to an

appropriate node instead of the original one, which is the source terminal of MN0 in Fig. 2.1 and Fig. 2.5. In Fig. 3.1, the appropriate point is realized by the additional connection of a PMOS transistor and an NMOS transistor. Transistor MN8 provides similar function as transistor MN0 with smaller size, and transistor MP8 works similarly as transistor MP5. With the similar structure, the gate terminal of transistor MP1 receives similar voltage as that of transistor MP1 in previous design. In the receive mode, the gate voltage of transistor MP1 is conducted to VDD (for 2xVDD input signal from I/O PAD) or 0 V (for 0-V input signal from I/O PAD) by transistor MN8 and MP8, respectively. In the transmit mode, the gate voltage is conducted to 0 V or VDD as the drain terminal of transistor MN1 does. However, since the gate terminal of transistor MP1 does not drop to ground as immediately as the drain terminal of transistor MN1 does, large |Vgs| value does not occur in transistor MP1. The gate voltage of transistor MP1 is pulled down gradually by MN8 and the other NMOS transistors when transition from receiving 2xVDD input signal to transmitting 0-V output signal. Thus, the new proposed design does not suffer gate-oxide reliability problem in both steady state and transient state.

3.1.2 Simulation results

A. Simulated Waveform for Steady State Operation and Verification to New Modifications

The simulated results of the new proposed 2xVDD-tolerant I/O buffer to prevent hot-carrier degradation and gate-oxide reliability have been verified by the HSPICE simulation in a 0.13-μm CMOS model with VDD of 1.2 V. Fig. 3.2 and Fig. 3.3 show the simulated waveforms of the new proposed 2xVDD-tolerant I/O buffer well operating with speed of 150 MHz in the receive mode and transmit mode, respectively. As shown in Fig. 3.2, when new proposed mixed-voltage 2xVDD I/O buffer receives 0-V and 2.5-V signal from I/O PAD, it successively outputs 1.2-V and 0-V Din signal with N-well voltage biased at 1.2 V

and 2.5 V respectively. In Fig. 3.3, as Dout signal varies between 1.2 V and 0 V, new proposed I/O buffer transmits similar swing to I/O PAD accordingly and N-well voltage keeps near 1.2 V.

Fig. 3.4 shows the Vds of MN0 in the new proposed I/O buffer from receiving 2.5-V input signal to transmitting 0-V output signal. Fig. 3.5(a) and (b) shows the Vds of MN3 in the new proposed I/O buffer from receiving 2.5-V input signal to transmitting 0-V or VDD output signal, respectively. Comparing Fig. 3.4, Fig. 3.5(a) and (b) with previous figures (Fig.

2.2, Fig. 2.3(a), (b), Fig. 2.6, Fig. 2.8(a) and (b)) correspondingly, MN0 and MN3 in Fig. 2.1 suffer serious hot-carrier degradation problem due to the larger Vds. Since the drain-to-source voltage of MN0 and MN3 are nearly the same for the new buffer shown in Fig. 3.1 and the buffer shown in Fig. 2.5, the capabilities of preventing hot-carrier degradation when receiving 2.5-V input signal are almost the same between these two buffers (Fig. 2.5 and Fig. 3.1).

However, the new buffer is more efficient in area saving.

Fig. 3.2 Simulated waveforms of the proposed mixed I/O buffer (this invention) operating at 150 MHz when receiving 2.5-V to 0-V input signals at I/O PAD.

Fig. 3.3 Simulated waveforms of the proposed mixed I/O buffer (this invention) operating at 150 MHz when transmitting 1.2-V to 0-V output signals at I/O PAD.

Fig. 3.4 The drain-to-source voltage (Vds) of MN0 in the new proposed I/O buffer during the transition from receiving 2xVDD input signal to transmitting 0-V output signal.

(a)

(b)

Fig. 3.5 The drain-to-source voltage (Vds) of MN3 in the new proposed I/O buffer during the transition from receiving 2xVDD input signal (a) to transmitting 0-V output signal and (b) to transmitting VDD output signal.

Fig. 3.6 shows the Vds waveforms of the transistors in the transmitting circuit of the new proposed I/O buffer from receiving 2.5-V input signal to transmitting 1.2-V output signal.

As shown in Fig. 3.6, the transistors in the new proposed I/O buffer have lower drain-to-source voltage, which is more robust to prevent hot-carrier degradation.

Fig. 3.6 The drain-to-source voltage (Vds) of transistors in the new transmitting circuits of new proposed buffer during the transition from receiving 2xVDD input signal to transmitting VDD output signal.

Fig. 3.7 shows the gate-to-source voltages of transistor MP1 in the new proposed I/O buffer. The peak |Vgs| value of similar PMOS in the prior designs is larger than VDD of 1.2 V as shown in Fig. 2.2 and Fig. 2.8. However, the Vgs of MP1 in the proposed I/O buffer is close to VDD, which is confirmed more robust than the previous designs in both hot-carrier degradation and gate-oxide reliability.

Fig. 3.7 The gate-to-source (Vgs) voltage across transistor MP1 in the new proposed I/O buffer during the transition from receiving 2.5-V to transmitting 0-V output signals.

B. Power Performance of The New Proposed I/O Buffer and Prior Arts

The power consumption is compared as listed in TABLE 3.1 to TABLE 3.2 with 0.13-μm CMOS model and adopts average current of the supply voltage as reference. The temperature is set at 85℃, 25℃ and 50℃ under Typical Typical (TT) corner simulation. The output loading capacitor is 10 pF. According to the simulated results in transmit mode and in the listed two transient states, the average current of the supply voltage is near among the three buffers but the new buffer is slightly less than the other two prior arts in transmit mode.

In the receive mode, the power consumption without consideration the extra received power from I/O PAD of the new buffer is larger than the two prior arts. Another comparison is done by changing the temperature to 25℃ and 50℃ in the steady state as listed in TABLE 3.3 and TABLE 3.4, respectively. Thus, the new buffer has better power performance when operating in transmit mode and more robust in the transient states.

TABLE3.1

COMPARISON IN AVERAGE CURRENT OF THE SUPPLY VOLTAGE AMONG TWO PRIOR ARTS AND

NEW PROPOSED I/OBUFFER IN STEADY STATE AT 85℃

Mixed-voltage I/O designs Receive mode Transmit mode

Prior art in Fig. 2.1 [7] 0.68uA 2.98mA

Modified I/O buffer in Fig. 2.5 13.8uA 2.94mA

This work 95.6uA 2.7mA

TABLE3.2

COMPARISON IN AVERAGE CURRENT OF THE SUPPLY VOLTAGE AMONG TWO PRIOR ARTS AND

NEW PROPOSED I/OBUFFER IN CERTAIN TRANSIENT STATE AT 85℃

Mixed-voltage I/O designs From receive 2.5 V to transmit 0 V

From receive 2.5 V to transmit

1.2 V

Prior art in Fig. 2.1 [7] 24.4uA 0.136mA

Modified I/O buffer in Fig. 2.5 27.1uA 0.134mA

This work 26.37uA 0.135mA

TABLE3.3

COMPARISON IN AVERAGE CURRENT OF THE SUPPLY VOLTAGE AMONG TWO PRIOR ARTS AND

NEW PROPOSED I/OBUFFER IN STEADY STATE AT 25℃

Mixed-voltage I/O designs Receive mode Transmit mode

Prior art in Fig. 2.1 [7] 9.75uA 2.91mA

Modified I/O buffer in Fig. 2.5 22.55uA 2.89mA

This work 72.22uA 2.63mA

TABLE3.4

COMPARISON IN AVERAGE CURRENT OF THE SUPPLY VOLTAGE AMONG TWO PRIOR ARTS AND

NEW PROPOSED I/OBUFFER IN CERTAIN TRANSIENT STATE AT 50℃

Mixed-voltage I/O designs From receive 2.5 V to transmit 0 V

From receive 2.5 V to transmit

1.2 V

Prior art in Fig. 2.1 [7] 3.94uA 2.94mA

Modified I/O buffer in Fig. 2.5 19.85uA 2.92mA

This work 83.06.uA 2.66mA

C. Rise Time, Fall Time and Propagation Delay of The New Proposed I/O Buffer and Prior Arts

TABLE 3.5 and TABLE 3.6 show the comparison results of the rise time (tr), fall time (tf) and the propagation delay (from high to low: tphl, from low to high: tplh, and the half average of tphl and tplh: tp) of the new proposed I/O buffer and the two prior arts. The fall time and propagation delay of the modified I/O buffer in Fig. 2.5 are slightly longer than the new proposed design and the prior art in Fig. 2.1. The reason is attributed to the additional output loading due to MPT1 and MPT0 in Fig. 2.5. Since the prior art in Fig. 2.1 uses two-stacked NMOS transistors instead of tri-stacked NMOS transistors, the effected output loading of at I/O PAD is slightly smaller than the new proposed buffer and the modified I/O buffer in Fig. 2.5. However, since the capacitor at the I/O PAD in simulation for the effective output loading, 10 pf, is the dominant part, the transition performance including rise time, fall time, and propagation delay are not significant among the three circuits.

TABLE3.5

COMPARISON ON RISE AND FALL TIME OF THE POWER SUPPLY VOLTAGE (VDD) AMONG TWO

PRIOR ARTS AND NEW PROPOSED I/OBUFFER IN STEADY STATE AT 85℃

Mixed-voltage I/O designs

Receive mode Transmit mode

tr tf tr tf

Prior art in Fig. 2.1 [7] 0.71 ns 0.83 ns 0.4 ns 0.79 ns Modified I/O buffer in Fig. 2.5 0.71 ns 0.86 ns 0.4 ns 1.37 ns

This work 0.71 ns 0.9 ns 0.4 ns 0.65 ns

TABLE3.6

COMPARISON ON PROPAGATION DELAY OF THE SUPPLY VOLTAGE AMONG TWO PRIOR ARTS AND NEW PROPOSED I/OBUFFER IN STEADY STATE AT 85℃

Mixed-voltage I/O designs

Receive mode Transmit mode Tphl tplh tp tphl tplh tp

Prior art in Fig. 2.1 [7] 0.38 ns 0.45 ns 0.42 ns 0.65 ns 0.45 ns 0.55 ns Modified I/O buffer in Fig.

2.5 0.42 ns 0.47 ns 0.45 ns 1.1 ns 0.46 ns 0.78 ns This work 0.39 ns 0.51 ns 0.45 ns 0.56 ns 0.48 ns 0.52 ns

3.1.3 Experimental Results

The new proposed mixed-voltage 2xVDD-tolerant I/O buffer has been fabricated in a 0.13-μm 1.2-V CMOS process with only thin-oxide (1.2-V) devices. The layout -top- view and the die photograph of the test chip are shown in Fig. 3.8(a) and (b) with the corresponding circuit blocks, including VDD power cell, I/O circuit, Dout pad, EN pad, Din pad, and VSS power cell. Gated-ground NMOS and gate-VDD PMOS are used in the ESD protection scheme of the proposed I/O buffer.

Fig. 3.9 shows the measurement setup for the test chip with the PCB board. The rectangular pulse signal is generated by Agilent 81110A pulse generator to output 133 MHz or 1 MHz 2.5-V or 1.2-V rectangular wave. In receive mode, OE signal is connected to 0 V.

Dout is floating and the I/O PAD is connected to the pulse generator. Din PAD is connected to the oscilloscope to be observed. In transmit mode, OE signal is connected to VDD. Din PAD is floating and Dout is connected to the pulse generator. The I/O PAD is connected to the oscilloscope. Besides, to compare input and output signal of the test chip, the oscilloscope is connected to the pulse generator.

Fig. 3.10 shows the measured waveforms of the proposed 2xVDD-tolerant I/O buffer in

the receive mode to receive the 1-MHz input signals with voltage swing of 0-to-2.5 V at I/O PAD, where the input data has been successfully transmitted to Din with a voltage swing of 0-to-1.2 V. Fig. 3.11(a) and Fig. 3.11(b) show the measured waveforms at the I/O PAD in the

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