Experimental Results

The new proposed mixed-voltage 2xVDD-tolerant I/O buffer has been fabricated in a 0.13-μm 1.2-V CMOS process with only thin-oxide (1.2-V) devices. The layout -top- view and the die photograph of the test chip are shown in Fig. 3.8(a) and (b) with the corresponding circuit blocks, including VDD power cell, I/O circuit, Dout pad, EN pad, Din pad, and VSS power cell. Gated-ground NMOS and gate-VDD PMOS are used in the ESD protection scheme of the proposed I/O buffer.

Fig. 3.9 shows the measurement setup for the test chip with the PCB board. The rectangular pulse signal is generated by Agilent 81110A pulse generator to output 133 MHz or 1 MHz 2.5-V or 1.2-V rectangular wave. In receive mode, OE signal is connected to 0 V.

Dout is floating and the I/O PAD is connected to the pulse generator. Din PAD is connected to the oscilloscope to be observed. In transmit mode, OE signal is connected to VDD. Din PAD is floating and Dout is connected to the pulse generator. The I/O PAD is connected to the oscilloscope. Besides, to compare input and output signal of the test chip, the oscilloscope is connected to the pulse generator.

Fig. 3.10 shows the measured waveforms of the proposed 2xVDD-tolerant I/O buffer in

the receive mode to receive the 1-MHz input signals with voltage swing of 0-to-2.5 V at I/O PAD, where the input data has been successfully transmitted to Din with a voltage swing of 0-to-1.2 V. Fig. 3.11(a) and Fig. 3.11(b) show the measured waveforms at the I/O PAD in the transmit mode to transmit the 10-kHz and 133-MHz output signals with a voltage swing of 0-to-1.2 V given at Dout, respectively. Some imperfectness of the measured waveforms can be attributed to the buffer size in the I/O cell, parasitic and loading effect of the PCB board.

Cable line, inter-connections, impedance matching of the input and output of the PCB board, oscilloscope, and wave generator also cause effects such as ripples or delay at the signals.

(a)

(b)

Fig. 3.8 (a) Layout -top- view of test chip to verify the new proposed 2xVDD-tolerant I/O buffer in a 0.13-μm CMOS process. (b) Die photograph of the test chip for the new proposed I/O circuit fabricated with 0.13-μm 1.2-V CMOS process.

(a)

(b)

Fig. 3.9 Measurement setup for the mix-voltage I/O buffer in (a) receive mode and (b) transmit mode.

Fig. 3.10 Measured waveforms of the proposed 2xVDD-tolerant I/O buffer operating at VDD of 1.2 V when receiving 0-to-2.5 V input signals at I/O PAD.

(a)

(b)

Fig. 3.11 Measured waveforms at I/O pad of the proposed 2xVDD-tolerant I/O buffer operating at VDD of 1.2 V when transmitting 0-to-1.2 V output signals at (a) 10 kHz and (b) 133 MHz.

Chapter 4 Conclusion

4.1 C

ONCLUSION

A new 2xVDD-tolerant I/O buffer against gate-oxide overstress and hot-carrier degradation has been successfully verified in a 130-nm 1.2-V CMOS process with only thin-oxide devices. The gate-to-source, gate-to- drain, and drain-to-source voltages of the transistors in the new proposed 2xVDD-tolerant I/O buffer can be kept within the normal operating voltage (VDD). The new proposed 2xVDD-tolerant I/O buffer can receive 1.2-V/2.5-V input signals or transmit 1.2-V output signals up to 133 MHz, which is compatible to the I/O specifications of PCI-X in the mixed-voltage I/O interfaces.

4.2 F

UTURE

W

ORK

The estimation for the power consumption in receive mode by simulation should be improved since the results observed may be different with the measured results due to the received I/O PAD signal and related parasitic effect in reality. Measurement for the performance is required to be more complete with the layout and fabrication of other prior arts.

R EFERENCES

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IEEE Int. Reliability Physics Symp., 1997, pp. 169−173.

[2] G. P. Singh and R. B. Salem, “High-voltage-tolerant I/O buffers with low-voltage CMOS process,” IEEE J. Solid-State Circuits, vol. 34, no. 11, pp.1512-1525, Nov. 1999.

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2253−2258, Dec. 1988.

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Tech. Digest, 1983, pp. 186-189.

[5] Renesas Technology, Semiconductor Device Reliability Handbook, 5th Edition, Aug. 31, 2006.

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EOS/ESD Symp., 1994, pp. 125−134.

[7] H.-W. Tsai and M.-D. Ker, “Design of 2xVDD-tolerant I/O buffer with considerations of gate-oxide reliability and hot-carrier degradation,” in Proc. of IEEE Int. Conf.

Electronics, Circuits and Systems, 2007, pp. 1240-1243.

[8] H.-C. Chow, “Bidirectional buffer for mixed-voltage applications,” in Proc. IEEE Int.

Symp. Circuits Syst., 1999, pp. 270–273.

[9] R. D. Adams, R. C. Flaker, K. S. Gray, and H. L. Kalter, “CMOS offchip driver circuit,”

U.S. Patent 4782250, Nov. 1, 1988.

[10] M. Takahashi, T. Sakurai, K. Sawada, K. Nogami, M. Ichida, and K. Matsuda, “3.3 V–5 V compatible I/O circuit without thick gate oxide,” in Proc. IEEE Custom Integrated

Circuits Conf., 1992, pp.23. 3. 1–23. 3. 4.

[11] B. Razavi, Design of Analog CMOS Integrated Circuit, International edition, McGraw Hall, 2001.

[12] B.-G. Streetman, and S. Banerjee, Solid State Electronic Devices, 5th ed., Prentice Hall, 2000.

[13] E. Li and S. Prasad, “Channel Width Dependence of NMOSFET Hot Carrier Degradation,” IEEE Trans. on Electron Devices, vol. 50, No. 6, pp. 1545-1548, Jun. 2003.

[14] A.-J. Annema, G. J. G. M. Geelen, and P. C. de Jong, “5.5-V I/O in a 2.5-V 0.25-μm CMOS Technology,” IEEE J. Solid-State Circuits, vol. 36, no.3, pp. 528-538, Mar. 2001.

[15] E. R. Minami, S. B. Kuusinen, E. Rosenbaum, P. K. Ko, and C. Hu, “Circuit-level simulation of TDDB failure in digital CMOS circuits,” IEEE Trans. Semiconduct.

Manufact., vol. 8, no. 3, pp. 370−377, Aug. 1995.

[16] A. M. Yassine, H. E. Nariman, M. McBride, M. Uzer, and K. R. Olasupo, “Time dependent breakdown of ultrathin gate oxide,” IEEE Trans. Electron Devices, vol. 47, no.

7, pp. 1416−1420, Jul. 2000.

[17] Wikipedia : http://en.wikipedia.org/wiki/PCI-X

[18] J. Brewer and J. Sekel (2004, Jun.). White paper: PCI Express Technology. Dell Inc., US.

[Online].Avaliable:http://www.dell.com/content/topics/global.aspx/vectors/en/2004_pciex press?c=us&l=en&s=corp

[19] M.-D. Ker, S.-L. Chen, and C.-S. Tsai, “Overview and design of mixed-voltage I/O buffers with low-voltage thin-oxide CMOS transistors,” IEEE Trans. on Circuits and

Systems I, vol. 53, no. 9, pp. 1934-1945, Sep. 2006.

[20] M.-D. Ker and F.-L. Hu, “Design on mixed-voltage I/O buffers with consideration of hot-carrier reliability,” in Proc. 2007 IEEE Int. Symp. on VLSI Design, Automation and

Test, 2007, pp. 36-39.

[21] T.-J. Lee, T.-Y. Chang, and C.-C. Wang,, “Mixed-voltage-tolerant I/O buffer design,” in

Proc. Int. Symp. on Integrated Circuit, 2007, pp. 556-559.

[22] K. Bult, “Analog broadband communication circuits in pure digital deep sub-micron CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 1999, pp. 76-77.

[23] S. Poon, C. Atwell, C. Hart, D. Kolar, C. Lage, and B. Yeargain, “A versatile 0.25 micron CMOS technology,” in Int. Electron Devices Meeting (IEDM) Tech. Digest, 1998, pp. 751-754.

[24] M. Hargrove, S. Crowder, E. Nowak, R. Logan, L. K. Han, H. Ng, A. Ray, D. Sinitsky, P.

Smeys, F. Guarin, J. Oberschmidt, E. Crabbé, D. Yee, and L. Su, “High-performance sub-0.08μm CMOS with dual gate oxide and 9.7 ps inverter delay,” in Int. Electron

Devices Meeting (IEDM) Tech. Digest, 1998, pp. 627-630.

[25] S.-L. Chen and M.-D. Ker, “A new output buffer for 3.3-V PCI-X application in a 0.13-μm 1/2.5-V CMOS process,” in Proc .of IEEE Asia-Pacific conf. ASIC (AP-ASIC), 2004, pp. 112-155.

Publications:

(A) International Conference paper

[1] H.-W. Tsai and M.-D. Ker, “Design of 2xVDD-tolerant I/O buffer with considerations of gate-oxide reliability and hot-carrier degradation,” in Proc. of the 14^th

IEEE International Conference on Electronics, Circuits and Systems (ICECS 2007), Marrakech, Morocco,

Dec. 11-14, 2007, pp. 1240-1243.

(B) Regular Journal Papers paper

Submitted: H.-W. Tsai and M.-D. Ker, “Design for 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation,” IEEE Trans. Circuits

Syst. I

Appendix:

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-

Abstract—A new 2xVDD-tolerant mixed-voltage I/O buffer circuit, realized with only 1xVDD devices in nanoscale CMOS technology, to prevent transistors against gate-oxide reliability and hot-carrier degradation is proposed. The new proposed 2xVDD-tolerant I/O buffer has been designed and fabricated in a 0.13-μm CMOS process to serve a 2.5-V/1.2-V mixed-voltage interface without using the additional thick gate-oxide (2.5-V) devices. This 2xVDD-tolerant I/O buffer has been successfully confirmed by the experimental results with operating speed up to 133 MHz for PCI-X application.

Index Terms—mixed-voltage I/O buffer, hot-carrier degradation, gate-oxide reliability.

I. INTRODUCTION

ITH the rapid development of complementary metal oxide semiconductor (CMOS) techniques, the transistor dimension has been continually scaled down to reduce chip area and increase operating speed. As well as, the normal supply voltage (VDD) to drive the chip is also reduced to save power consumption correspondingly. The thickness of gate oxide becomes much thinner in order to reduce the core power supply voltage (VDD) for resulting in lower power consumption. In the meanwhile, the maximum tolerable voltages across the transistor terminals (drain, source, gate, and bulk) are correspondingly decreased to ensure lifetime.

However, some earlier standardized protocols or ICs designed and fabricated with previous CMOS processes which have higher VDD may communicate in a microelectronics system with the chips fabricated in advanced CMOS processes which has lower VDD. Therefore, the chips in advanced CMOS processes will face to the interface of input/output signals with voltage levels higher than their normal supply voltage (VDD).

Such mixed-voltage I/O interfaces must be designed to overcome several problems, such as gate-oxide reliability [1]-[2], hot-carrier degradation [3]-[5] and undesired

Manuscript received Sept. 21, 2008. This work was supported by National Science Council (NSC), Taiwan, under Contract of NSC 97-2221-E-009-170.

M.-D. Ker and H.-W. Tsai are with the Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, R.O.C. (e-mail: mdker@ieee.org). M.-D. Ker was rotated to the Dept. of Electronic Engineering, I-Shou University, Kaohsiung, Taiwan, since 2008.

Fig. 1. The conventional mixed-voltage I/O buffer designed with gate-tracking circuit and dynamic n-well bias circuit to solve gate-oxide reliability issue [7].

circuit leakage paths [6].

A conventional mixed-voltage I/O buffer with the gate-tracking circuit and the dynamic n-well bias circuit is shown in Fig. 1 [7]. This mixed-voltage I/O buffer can tolerate 2xVDD input signal from I/O PAD without suffering gate-oxide reliability, hot-carrier degradation, and the undesired circuit leakage in the steady state. However, during the transition from receiving 2xVDD input signal to transmitting 0-V output signal, the transistors MN0 and MN3 suffer hot-carrier degradation problem. The transistor MP5 also suffers gate-oxide reliability problem. Moreover, the transistors MN2, MP2, and MN3 also suffer hot-carrier degradation problem during the transition from receiving 2xVDD input signal to transmitting VDD output signal. The difficulties about hot-carrier degradation and gate-oxide overstress to prior I/O buffer design are briefed in the following section of this paper.

To realize an I/O buffer with 1.8/3.3/5-V mix-voltage tolerance but without reliability problems, 0.35-μm devices are used in [8] and the voltage differences are kept within supply voltage 3.3 V. Dual-oxide (thick-oxide and thin-oxide) process

Design for 2xVDD-Tolerant Mixed-Voltage I/O Buffer against Gate-Oxide Reliability and

Hot-Carrier Degradation

Hui-Wen Tsai, Student Member, IEEE, and Ming-Dou Ker, Fellow, IEEE

W

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 2 [9]-[11] are also provided by foundry and can be used to

prevent reliability anxiety in mixed-voltage interface as gate-oxide overstress and hot-carrier degradation. Using two kinds of devices (as 1-V and 2.5-V transistors) are also adopted in [12] to output 3.3-V signal without aforesaid anxiety. The tradeoff to use two masks in the fabrication of the circuit is the requirements for the cost and robustness.

In this work [13], to solve the aforementioned problems in Fig. 1, a 2xVDD-tolerant I/O buffer with novel transmitting circuit and new gate control circuit is proposed and verified in a 0.13-μm CMOS process with only 1xVDD devices.

II. HOT-CARRIER DEGRADATION ISSUE AND GATE-OXIDE

RELIABILITY PROBLEMS IN PRIOR I/OCIRCUIT DESIGN

When the MOSFET devices feature extremely short channel length and high electrical field in deep-submicron technologies, hot-carrier degradation problem becomes more important in reliability circuit design. The mechanism of hot-carrier effect can be illustrated by a typical enhancement-mode n-channel MOS transistor shown in Fig. 2 exemplarily. With positive stress on gate and drain terminals, the electronics traveling through source to drain terminals gain kinetic energy while expensing electrical potential energy. When high lateral electrical field appears across drain and source terminals, electronics continually increase instantaneous velocity and become “hot” while the average velocity saturates [14]. “Hot carriers,” including both hot electronics and hot holes but mainly hot electronics cause effect due to larger mobility and lower interface energy barrier, can create secondary electron-hole pairs by ion-impact ionization [15]. Collecting the secondary electrons on bulk terminals and hot electrons on drain terminals increases the value of substrate current (Isub)

Fig. 2. The mechanism of hot-carrier effect depicted of a typical enhancement-mode n-channel MOS transistor.

and drain current (Id).When high energetic electronics tunnel into the oxide, the effective gate resistance is reduced.

Generated hot carriers can also cause time dependent shift in characteristics of device as threshold voltage and conveyed conductance by rupturing such the Si-H bonds. Thus, the life time of devices, the correctness of expected operations and the performance of circuits are affected as deign parameters vary with time and it makes hot-carrier effect a non-ignorable issue especially in design of robust mixed-voltage interface circuit in deep submicron process.

The degradation caused by hot carrier deeply relies on the length and the biasing conditions of the device [16]. In the worse-case setting of the gate-to-source voltage (Vgs), which means the transistor is well in saturation with large drain current, the drain-to-source voltage (Vds) and life time (

τ

life⁾

has exponential relationship as follows [5]:

( )

life

A exp B V /

ds

τ ^{= −}

, where A and B are constants varying with deep submicron processes. Typically, to ensure a 5~10 year life time with gate-to-source voltage (Vgs) =0.5~1.0 times VDD, the drain-to-source voltage (Vds) must be kept within 1~1.1 times VDD. In addition to the consideration of gate-oxide breakdown, the absolute value of gate-to-source and gate-to-drain voltage should be kept within the supply voltage and the drain-to-source voltage in NMOS devices and source-to-drain voltage in PMOS devices must kept within VDD when devices work on “on” state.

The above limitations are met in some prior arts as Fig.1 in steady state. However, during the transition from receiving 2xVDD input signal to transmitting 0-V output signal, the drain-to-source voltage (Vds) of transistors MN0 and MN3 will be much higher than VDD. The reason is that the drain-to-source voltage starts to increase from VDD since the source terminal is pulled down faster than the drain terminal at the beginning of this transition time period. The transistor MP5 also has larger Vgs since its source and gate are connected to the drain and source of transistor MN0. Moreover, the transistors MN2, MP2, and MN3 also come across similar problem during the transition from receiving 2xVDD input signal to transmitting VDD output signal.

While PU signal is suddenly pulled down from VDD to 0, the drain terminal of MN2 are pulled down much slower since the transistors are turn on accordingly and it also takes time for the gate terminal of transistor MP2 to be pulled down from 2xVDD to turning on transistor MP2. The above mentioned transient situations for transistors MN0, MN3, MP5, MN2 and MP2 with high voltage across drain and source terminals are verified by the HSPICE simulation results in a 0.13-μm CMOS technology with VDD is 1.2 V and 2xVDD is 2.5 V. As shown in Fig. 3, Fig. 4(a), (b) and Fig. 5, Vds of transistor MN0 (also the Vsg of transistor MP1), MN3, MN2 and MP2 are much larger than VDD among a certain time. The peak values are 1.96 V, 2.11 V, 2.09 V and 2.07 V respectively. Thereby, it results in serious hot-carrier degradation or gate-oxide

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 3 overstress in the transition from receiving 2.5-V input signal to

transmitting 0-V or 1.2-V output signal.

Fig. 3. The drain-to-source voltage (Vds) of transistor MN0 and also the source-to-gate voltage (Vsg) of transistor MP5 in Fig. 1 during the transition from receiving 2xVDD input signal to transmitting 0-V output signal.

(a)

(b)

Fig. 4. The drain-to-source voltage (Vds) of transistor MN3 in Fig. 1 (a) during the transition from receiving 2xVDD input signal to transmitting 0-V output signal and (b) during the transition from receiving 2xVDD input signal to transmitting VDD output signal.

Fig. 5. The drain-to-source voltage (Vds) of transistor MN2/MP2 in Fig. 1 during the transition from receiving 2xVDD input signal to transmitting VDD output signal.

To solve the hot-carrier degradation problems happened in some prior arts as Fig. 1, a technique with three or more stacked NMOS transistors has been reported in [16]. A modified 2xVDD-tolerant I/O buffer circuit with this technique to eliminate hot-carrier issue is shown as Fig. 6. When the I/O buffer receives 2xVDD input signal, the gate terminal of transistor MN5 and MN6 are biased at 2xVDD through the transistor MPT1 and MPT3, respectively. On the other hand, the gate terminal of transistor MN5 and MN6 are biased at VDD if a VDD signal is transmitted or a 0-V signal appears on the output pad whether received or transmitted.

During the transition from receiving 2xVDD input signal to transmitting 0-V output signal, the source terminal of transistor MN5 and MN6 are biased at 2xVDD-ΔV initially (where ΔV is the Vds of the diode-connected transistors) since their diode connected structure due to same drain and gate voltage.

Fig. 6. The modified mixed-voltage I/O buffer designed with three-stacked transistors to prevent hot-carrier degradation [16].

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 4 In the meanwhile, the source terminal of transistor MN0 and

MN3 are pulled down by transistor MN1 and MN4 in a 0.13-μm technology, respectively. Comparing the transistor MN0 and MN3 in Fig. 1 with the same transistors in Fig. 6 during this transient time, the transistors in Fig. 6 have smaller Vds since the drain voltage is initially smaller by –ΔV. Fig. 7, Fig. 8(a), (b), Fig. 9 and Fig. 10 are the HSPICE simulation

Fig. 7. The drain-to-source voltage (Vds) of transistor MN0 in Fig. 6 during the transition from receiving 2xVDD input signal to transmitting 0-V output signal.

(a)

(b)

Fig. 8. The drain-to-source voltage (Vds) of transistor MN3 in Fig. 6 during the transition from receiving 2xVDD input signal (a) to transmitting 0-V output signal and (b) to transmitting VDD output signal.

results verified in a 0.13-μm CMOS technology when VDD is 1.2 V. With smaller maximum of Vds, the I/O buffer in Fig. 6 can almost eliminate serious hot-carrier degradation happened in previous arts as shown in Fig. 7, Fig. 8(a), and (b). However, the gate-oxide overstress still happens in the transistor MP1 in Fig. 6 during the transition from receiving 2xVDD to transmitting 0 V as shown in Fig.9. Also, the transmission circuit (with transistors MN2 and MP2 in Fig. 6) still suffers the hot-carrier degradation as shown in Fig. 10.

Fig. 9. The source-to-gate voltage (Vsg) of transistor MP1 in Fig. 6 during the transition from receiving 2xVDD input signal to transmitting 0 output signal

Fig. 10. The drain-to-source voltage (Vds) of transistor MN2/MP2 in Fig. 6 during the transition from receiving 2xVDD input signal to transmitting VDD output signal.

III. NEW PROPOSED MIXED-VOLTAGE I/OBUFFER

The new proposed 2xVDD-tolerant I/O buffer realized with only 1xVDD devices to prevent transistors against gate-oxide reliability and hot-carrier degradation is shown in Fig. 11, which keeps the significant design advantages of the prior arts with three additional new modifications. The design concepts of the major parts in this new proposed I/O buffer are introduced in the following.

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Fig. 11. The new proposed 2xVDD-tolerant I/O buffer realized with only 1xVDD devices to prevent transistors against gate-oxide overstress and hot-carrier degradation.

A. Circuit Operation

The basic structure for this mixed-voltage I/O buffer typically includes a pre-driver, a dynamic n-well bias circuit, two or three-stacked transistors, gate-tracking circuit, and an input stage unit, which is controlled by an enable signal OE.

The circuit operating modes include a receive mode (for receiving input signal from I/O PAD) and a transmit mode (for transmitting output signal to I/O PAD). The corresponding

The circuit operating modes include a receive mode (for receiving input signal from I/O PAD) and a transmit mode (for transmitting output signal to I/O PAD). The corresponding

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