General Background

Conventional scaling of the traditional bulk MOSFET is more and more difficult.

When the gate length scales down to 10-nm regime, a heavy channel doping will likely be required to adjust threshold voltage for improving short-channel effects. In a bulk device with a heavily doped channel (~ 2 x 10¹⁸ cm^-3 [1]), carrier mobility will be severely degraded due to impurity scattering and transverse electric field. In addition,the significant depletion charge in the channel will form, thus increasing the average vertical field experienced by a carrier in the inversion layer and increasing the effects of phonon scattering, interface scattering [2], a large depletion capacitance and subthreshold slope. Furthermore, when the channel with a lot of impurities will also inevitably enhance band-to-band tunneling leakage between the body and drain [3].

Therefore, as device scaling down to nano scale, the threshold voltage control will be a large issue of the device performance.

Future transistor scaling will require the incorporation of new device structures [4].The SOI (Silicon-On-Insulator) device will be the potential structure for the requirement of the high performance ULSI (Ultra Large Silicon Integrated) circuit

fabrication. Ultra-thin FDSOI (Fully Depleted Silicon-On-Insulator) devices and DG (Double-Gate) devices are promising candidates for ultrahigh-speed and low-power applications. They have many advantages compared with bulk devices [5]. Because thin-body devices can control short-channel effects with only intrinsic doping or still non-doping in the channel, thus allowing for gate-length scaling down to the 10-nm regime without adding channel implant procedure additionally [6].Therefore, Ultra- thin FDSOI devices and DG devices have negligible depletion charge and capacitance, which yields a steep subthreshold slope . On the other hand, lower transverse electric field and negligible impurity scattering contribute to increased mobility, so the drivability is enhanced [7]. They also have additional advantages: the reduction of the junction capacitance, the immunity for hot electron [8]~[10], the latch-free for CMOS, and so on. However, ultra-thin FDSOI device and DG device have severe problems:

the large source/drain parasitic resistance and the poor control of threshold voltage [11]. The former issue can be solved by SALICIDE (self-aligned-silicide) process which is aggressively investigated [12]. The threshold voltage control issue can be improved by work function engineering [13][14] which is substituted for channel doping adjustment. The appropriate threshold voltage requires the work function of gates ranging from 4.1-4.4eV for NMOS and 4.8-5.1eV for PMOS [15]. The conventional poly-silicon gate can not to achieve this goal by the heavy doping to form the n⁺ and p⁺ poly-silicon on the gate dielectrics. In order to realize this objective, it needs the mid-gap metals or metallic materials as the gate material.

In the work function engineering research, metal gates which are deposited on gate dielectrics by PVD facilities in high vacuum environment are the master stream.

The work function adjustment by several methods, such as: N2 implantation to a single metal [16], varied metals co-sputtering, and metal interdiffusion gate (MIG),

etc. In addition to work function tunable characteristics, metal gates also can eliminate the Poly Depletion Effect (PDE) and reduce the gate resistance. At present, TaN, TaSiN, TiN, Mo, and so on are the popular materials as the metal gate in the future.

Recently, the use of the transition metal silicide as the gate material that is FUll-SIlicide (FUSI) gate is investigated, such as TiSi2 [17], CoSi2 [18][19], NiSi [17][20]~[27], HfSi [28], PdSi [27], Co(x)Ni(x)Si2 [27], and so on. Among silicides as mentioned above, TiSi2, CoSi2, and NiSi were investigated widely in the SALICIDE process and the interconnect technology to reduce the series resistance problem between the S/D and gate and to raise circuits performance. Metal silicide gate has several benefits: First, compared with metal gate, metal silicide gate also has lower resistivity than that of poly-silicon gate, so it can improve PDE, too. Second, metals may produce sputtering damage when these are deposited on gate dielectrics, so it can show degraded electron and hole mobility [29]. On the other hand, when silicon is reacting with metals to form the silicides, because metals are deposited on silicon first (not on gate dielectrics). Thus, metal silicide gate will have no PVD damage. Third, the work function of the metal silicide can be tuned by doping the poly-silicon with different dopants and dosages before the silicide formation. It is easier to accomplish work function engineering than metal gates. Fourth, the metal silicide gate can form together with the S/D silicidation process. Therefore, in integration, the silicide gate is simpler than the metal gate process.

For TiSi2, it has been widely used in the IC industry. TiSi2 is a suggested candidate for the integrated circuit generations due to it’s low sheet resistance (13-15Ω/□) and high thermal stability. However, TiSi2 has the narrow lines effect. As the narrow lines are below 0.2µm, the high-resistivity phase, C49-TiSi2, is limited to transform the low-resistivity one, C54-TiSi2 [30][31]. It is because that the grain of

C54-TiSi2 structure is about 0.2 µm [30][32]. On the other hand, as a result of Ti can react with the oxide, or diffuse into the oxide to create traps even at temperature as low as 400^oC. Hence, the use of TiSi2 as the gate material degrades the oxide and the interface of the oxide and the substrate. Then, it generates the C-V distortion, increase of the gate leakage, and degradation of the mobility [17].

CoSi2 is an attractive replacement of TiSi2 due to it’s relatively linewidth-independent sheet resistance [33]~[35]. The formation of CoSi2 does not need phase transformation, so it has been extended to narrow lines using conventional processes. Therefore, when scaling down, totally silicided CoSi2 gate is more suitable than TiSi2 [18][19]. In addition, Co does not reacted with oxide, and Co is also the mid gap material. The CoSi2 gated-device has less DIBL, lower subthreshlod swing, higher on currents, and larger transconductance [18]. Nevertheless, the major drawback is that the high silicon consumption during the formation of silicidation than with TiSi2. For this reason, the use of CoSi2 to carry out the salicide process will produce deeply junctions and lead to large junction leakages.

Lately, there has been great interest in using NiSi for salicide application [36]~[38]. The resistivity of NiSi is comparable with that of TiSi2 and CoSi2. Like CoSi2, the sheet resistance of NiSi is relatively insensitive with the linewidth of the silicide. Then, the NiSi gate offers a number of merits. First, silicidation can be accomplished rapidly at low temperature (400-600℃) without agglomeration, hence it is suitable for low-temperature processes in the future MOSFET fabrication. Second, the work function of NiSi can be tuned by doping different dopants, such as boron, arsenic, phosphorous, and antimony [20][22][24][27]. Then, it is believed that the work function difference is caused by dopants pile-up at the NiSi/SiO2 interface. On the contrary, CoSi2 was shown a single mid-gap work function with n⁺ and p⁺

poly-silicon. Third, oxide is not reacted with nickel, so the NiSi gate is more suitable than the TiSi2 gate. Fourth, since Ni is the dominant diffusing species during Ni2Si and subsequent NiSi formation, a single step anneal is only needed. The last, for the salicide process, the main advantage of NiSi is the less silicon consumption compared to TiSi2 and CoSi2; hence, NiSi can form the shallower junction.