Comparison of AP, PA and IA

Thereafter, we will discuss the difference among of the sample AP,PA and IA.

Fig.4-16 shows the C-V characteristics of the AP, PA and IA samples, we can see that the flat band voltages of three structures shift with the temperature. Fig.4-17 shows the J-V characteristics treated by 800^oC annealing. Obviously, the sample IA3-800 has

the best J-V characteristics than AP3-800 and PA3-800. On the other hand, Fig.4-18 and Fig.4-19 are the weibull plot of the gate leakage current density at V = -1V and the electric breakdown field of the oxide at 800^oC. We can see that the IA sample has the best reliability among of three structures.

4-4 Summary

In this chapter, we investigated phosphorous-doped NiSi-gated MOS capacitors based on two types of stacked structures with different silicidation temperatures. The electric characteristics of samples with 35Å-thick oxide treated by 800^oC annealing are degraded, especially for n⁺ a-Si/poly-Si stacked structure. The result is different with the IA sample in chapter 3, but this is still better than the undoped NiSi gate as mentioned in chapter 2. This is maybe due to that the amount of the phosphorous in the gate is not equal to each other. There is less phosphorous in both of the stacked structures, so the retardation of nickel diffusion is decreased. In other words, nickel has high diffusibility at high temperature. On the other hand, because the amounts of nickel are large, the interface of the n⁺ a-Si/poly-Si (or poly-Si/n⁺ a-Si) does not trap so much nickel atoms like inhibiting boron penetration.

4.5 References

[1] S.L.Wu, C.L.Lee, and T.F.Lei,”Suppresion of boron penetration induced Si/SiO2

interface degradation by using a stacked-amorphous-silicon film as gate structure for pMOSFET,” IEEE, Electron device Lett.,vol.15,no.5, pp.160-162, May 1994.

[2] Y.Okazaki, S.Nakayama, M.Miyake, and T.Kobayashi,”Characteristics of sub-1/4-µm gate surface channel PMOSFET’s using a multiplayer gate structure of boron-doped poly-Si on thin nitrogen-doped poly-Si,” IEEE Trans. Electron

Devices, vol.41, no.12, pp.2369-2375, Dec. 1994.

[3] Y.H.Lin, C.S.Lai, C.L.Lee, T.F.Lei and T.S.Chao,”Nitridation of the Stacked Poly-Si gate to Suppress the Boron Penetration in pMOS,” IEEE Electron Device

Lett., vol.16, no.6, pp.248-249, June 1995.

[4] C.Y.Lin,C.Y.Chang,and Charles C.H. Hsu,”Suppression of boron penetration in BF2-implanted p-type gate MOSFET by trapping of fluorine in amorphous gate,”

IEEE, Trans. Electron Devices, vol.42, no.8, pp.1503-1509, Aug. 1995.

[5] Jam Wem Lee, Shen-Xiang Lin, Tan-Fu Lei, and Chung-Len Lee,”Improvements in Both Thermal Stability of Ni-Silicide and Electrical Reliability of Gate Oxides Using a Stacked Polysilicon Gate structure,” J.Electrochem. Soc., 148(9) G530-G533 (2001).

1. RCA cleaning

2. Growth of gate oxide (SiO2): 35 , 50 , 75Å 3. Deposition of silicon gate:

(A) 300Å n⁺ a-Si(top)/300Å undoped poly Si (B) 300Å undoped poly Si(top)/300Å n⁺ a-Si

4. Dip diluted HF

5. Deposition of metal: Ni, 450Å

6. Silicidation: RTA 500, 600, 700, 800^oC, 20s 7. Removing unreacted nickel:

H2SO4/H2O2 (3/1), 10 mins

8. Deposition of aluminum: Al, 5000Å (front) 9. Mask #1

10. Deposition of aluminum: Al, 5000Å (back)

Fig. 4-1 Process flow of the n⁺ NiSi-gated MOS capacitor formation.

p-Si <100>

p-Si <100>

p-Si <100>

p-Si <100>

Table.4-1

Gate RTA (

^o

C)

T

OX

(A) 500 600 700 800

35

AP3-500 AP3-600 AP3-700 AP3-800

50

AP5-500 AP5-600 AP5-700 AP5-800

n

⁺

a -Si /poly-Si

75

AP7-500 AP7-600 AP7-700 AP7-800

35

PA3-500 PA3-600 PA3-700 PA3-800

50

PA5-500 PA5-600 PA5-700 PA5-800

poly-Si/n

⁺

a -Si

75

PA7-500 PA7-600 PA7-700 PA7-800

Fig.4-2(a) Sheet resistance vs. RTA temperature. The plot shows the sheet resistance of the n⁺ a-Si/poly-Si/SiO2 structure with 500~800^oC RTA.

Fig.4-2(b) Sheet resistance vs. RTA temperature. The plot shows the sheet resistance of the poly-Si/n⁺ a-Si/SiO2 structure with 500~800^oC RTA.

RTA Temperature (oC)

500 600 700 800

R s (ohm/square)

1 2 3 4

5

AP3

AP7 AP5

RTA Temperature (oC)

500 600 700 800

R s (ohm/square)

1 2 3 4 5

PA3

PA7 PA5

Fig.4-3(a) The TEM image of the Ni/n⁺ a-Si/poly-Si/SiO2 structure with the oxide thickness ~ 39Å.

n

⁺

a-Si ~ 282Å poly-Si ~ 353Å

Si sub.

SiO ₂ ~ 39 Å

Ni ~ 447Å

20nm

Fig.4-3(b) The TEM image of the n⁺ a-Si/poly-Si/SiO2 structure with RTA 500^oC.

Fig.4-3(c) The TEM image of the n⁺ a-Si/poly-Si/SiO2 structure with RTA 800^oC.

20nm poly Si

Si sub.

SiO ₂

a-Si/poly-Si interface NiSi

Glue

~ 694 Å

NiSi ~ 883Å Glue

Si sub.

SiO ₂ 20nm

Fig.4-4(a) The TEM image of the Ni/poly-Si/n⁺ a-Si /SiO2 structurewith the oxide thickness ~ 41.6Å.

Si sub.

Glue

SiO ₂ ~ 41.6 Å poly-Si ~ 250Å

a-Si ~ 350Å

Ni ~ 450Å

20nm

Fig.4-4(b) The TEM image of the poly-Si/n⁺ a-Si/SiO2 structure with RTA 500^oC.

Fig.4-4(b) The TEM image of the poly-Si/n⁺ a-Si/SiO2 structure with RTA 800^oC.

20nm Si sub.

NiSi Glue

SiO ₂

~ 752 Å

Si sub.

NiSi ~ 787 Å Glue

SiO ₂

poly-Si /a-Si interface

20nm

poly-Si/a-Si interface

Fig.4-5(a) High frequency capacitance vs. gate voltage. The plot shows the C-V of the n⁺ a-Si/poly-Si/SiO2(35Å) structure with 500~800^oC RTA.

Fig.4-5(b) Gate leakage current density vs. gate voltage. The plot shows the J-V of the n⁺ a-Si/poly-Si/SiO2(35Å) structure with 500~800^oC RTA.

0

Fig.4-6(a) High frequency capacitance vs. gate voltage. The plot shows the C-V of the n⁺ a-Si/poly-Si/SiO2(50Å) structure with 500~800^oC RTA.

Fig.4-6(b) Gate leakage current density vs. gate voltage. The plot shows the J-V of the n⁺ a-Si/poly-Si/SiO2(50Å) structure with 500~800^oC RTA.

0

Fig.4-7(a) High frequency capacitance vs. gate voltage. The plot shows the C-V of the n⁺ a-Si/poly-Si/SiO2(75Å) structure with 500~800^oC RTA.

Fig.4-7(b) Gate leakage current density vs. gate voltage. The plot shows the J-V of the n⁺ a-Si/poly-Si/SiO2(75Å) structure with 500~800^oC RTA.

0

Fig.4-8(a) High frequency capacitance vs. gate voltage. The plot shows the C-V of the poly-Si/n⁺ a-Si/SiO2(35Å) structure with 500~800^oC RTA.

Fig.4-8(b) Gate leakage current density vs. gate voltage. The plot shows the J-V of the poly-Si/n⁺ a-Si/SiO2(35Å) structure with 500~800^oC RTA.

0

Fig.4-9(a) High frequency capacitance vs. gate voltage. The plot shows the C-V of the poly-Si/n⁺ a-Si/SiO2(50Å) structure with 500~800^oC RTA.

Fig.4-9(b) Gate leakage current density vs. gate voltage. The plot shows the J-V of the poly-Si/n⁺ a-Si/SiO2(50Å) structure with 500~800^oC RTA.

0

Fig.4-10(a) High frequency capacitance vs. gate voltage. The plot shows the C-V of the poly-Si/n⁺ a-Si/SiO2(75Å) structure with 500~800^oC RTA.

Fig.4-10(b) Gate leakage current density vs. gate voltage. The plot shows the J-V of the poly-Si/n⁺ a-Si/SiO2(75Å) structure with 500~800^oC RTA.

0

Fig.4-11(a) Oxide thickness vs. RTA temperature. The plot shows the EOT of the n⁺ a-Si/poly-Si/SiO2 structure with 500~800^oC RTA, and the physical oxide thickness measured by N&K analyzer.

Fig.4-11(b) Oxide thickness vs. RTA temperature. The plot shows the EOT of the poly-Si/n⁺ a-Si/SiO2 structure with 500~800^oC RTA, and the physical oxide thickness measured by N&K analyzer.

30

N&K 500 600 700 800

AP3 AP5 AP7

RTA Temperature (^oC) T OX (A)

N&K 500 600 700 800

PA3 PA5 PA7

RTA Temperature (^oC) T OX (A)

Fig.4-12(a) The Weibull plot shows the leakage current densities at Vg=-1V for the n⁺ a-Si/poly-Si/SiO2(35Å) structure with 500~800^oC RTA.

Fig.4-12(b) The Weibull plot shows the leakage current densities at Vg=-1V for the poly-Si/n⁺ a-Si/ SiO2(35Å) structure with 500~800^oC RTA.

Fig.4-13(a) The Weibull plot shows the electric breakdown field for the n⁺ a-Si/

poly-Si/SiO2(35Å) structure with 500~800^oC RTA.

Fig.4-13(b) The Weibull plot shows the electric breakdown field for the poly-Si/n⁺ a-Si/SiO2(35Å) structure with 500~800^oC RTA.

-3

Fig 4-14(a) Electron barrier height vs. RTA temperature. The plot shows the electron barrier height of the n⁺ a-Si/poly-Si/SiO2(75Å) structure with 500~800^oC RTA.

Fig.4-14(b) Electron barrier height vs. RTA temperature. The plot shows the electron barrier height of the n⁺ a-Si/poly-Si/SiO2(50Å) structure with 500~800^oC RTA.

0

RTA Temperature (^oC) e- Barrier Height (eV)

RTA Temperature (^oC)

2.91 3.09 3.10 3.05

Fig 4-15(a) Electron barrier height vs. RTA temperature. The plot shows the electron barrier height of the poly-Si/n⁺ a-Si/SiO2(75Å) structure with 500~800^oC RTA.

Fig 4-15(b) Electron barrier height vs. RTA temperature. The plot shows the electron barrier height of the poly-Si/n⁺ a-Si/SiO2(50Å) structure with 500~800^oC RTA.

0

RTA Temperature (^oC) e- Barrier Height (eV)

RTA Temperature (^oC) e- Barrier Height (eV)

Table. 4-2 (a)

AP3 AP3-500 AP3-600 AP3-700 AP3-800

C (pF)

67.4 70.8 70.8 73.1

AP5 AP5-500 AP5-600 AP5-700 AP5-800

C (pF)

49.7 51.7 51.3 51.0

(gate injection)

2.91 3.09 3.10 3.05

Φ

B

(eV)

(sub. injection)

2.09 2.45 2.34 2.41

Table. 4-2 (c)

AP7 AP7-500 AP7-600 AP7-700 AP7-800

C (pF)

32.7 33.3 33.4 34.0

Table. 4-3 (a)

PA3 PA3-500 PA3-600 PA3-700 PA3-800

C (pF)

64.5 65.8 67.0 66.2

PA5 PA5-500 PA5-600 PA5-700 PA5-800

C (pF)

48.1 48.6 50.2 50.1

(gate injection)

2.88 3.06 3.19 3.18

Φ

B

(eV)

(sub. injection)

2.30 2.39 2.32 2.41

Table. 4-3 (c)

PA7 PA7-500 PA7-600 PA7-700 PA7-800

C (pF)

33.3 33.7 34.1 33.2

(gate injection)

3.05 3.29 3.33 3.36

Φ

B

(sub. injection)

2.65 2.76 2.80 2.86

Fig.4-16(a) High frequency capacitance vs. gate voltage. The plot shows the C-V of the n⁺ a-Si/SiO2, n⁺ a-Si/poly-Si/SiO2, and poly-Si/n⁺ a-Si/SiO2 structure with 500^oC RTA.

Fig.4-16(b) High frequency capacitance vs. gate voltage. The plot shows the C-V of the n⁺ a-Si/SiO2, n⁺ a-Si/poly-Si/SiO2, and poly-Si/n⁺ a-Si/SiO2 structure with

Fig.4-16(c) High frequency capacitance vs. gate voltage. The plot shows the C-V of the n⁺ a-Si/SiO2, n⁺ a-Si/poly-Si/SiO2, and poly-Si/n⁺ a-Si/SiO2 structure with 700^oC RTA.

Fig.4-16(d) High frequency capacitance vs. gate voltage. The plot shows the C-V of the n⁺ a-Si/SiO2, n⁺ a-Si/poly-Si/SiO2, and poly-Si/n⁺ a-Si/SiO2 structure with

Fig.4-17 Gate leakage current density vs. gate voltage. The plot shows the J-V of the n⁺ a-Si/SiO2, n⁺ a-Si/poly-Si/SiO2, and poly-Si/n⁺ a-Si/SiO2 structure with 800^oC RTA.

10^-10 10^-8 10^-6 10^-4 10^-2 10⁰ 10²

-7 -6 -5 -4 -3 -2 -1 0

IA3-C EOT = 40.3 A IA3-800 EOT = 39.5 A AP3-800 EOT = 38.4 A PA3-800 EOT = 40.9 A

J g (-A/cm2 )

Gate Voltage (V)

Fig.4-18. The Weibull plot shows the leakage current densities at Vg=-1V for the n⁺ a-Si/SiO2, n⁺ a-Si/poly-Si/SiO2, and poly-Si/n⁺ a-Si/SiO2 structure with 800^oC RTA.

Fig.4-19. The Weibull plot shows the electric breakdown field for the n⁺ a-Si/SiO2, n⁺ a-Si/poly-Si/SiO2, and poly-Si/n⁺ a-Si/SiO2 structure with 800^oC RTA.

-3

Chapter 5

Conclusions

In this thesis, characteristics of the FUSI NiSi-gated MOS capacitor based on different structures with varied silicidation temperatures have been investigated. First, we fabricated the undoped FUSI NiSi-gated MOS capacitor by poly-Si and a-Si gate structure with different oxide thicknesses. Then, we investigated the characteristics of n⁺ NiSi-gate MOS capacitor by PH₃ in-situ doped a-Si. At the last, we used n⁺ a-Si/poly-Si stacked and poly-Si/n⁺ a-Si stacked structures to form the NiSi gate.

For the undoped NiSi-gated MOS capacitor, the diffusivity of nickel increases with temperature. Then, the FUSI NiSi gate was carried out after 600^oC silicidation or above, and the gate oxide reliability is not degraded. As temperature is raised up to 800^oC, there are large amounts of nickel which diffuse into the gate oxide, and the oxide is damaged drastically. Hence, the electric characteristics of the sample treated by 800^oC RTA are degraded severely. However, both of the poly-Si/SiO₂ and a-Si/SiO2 structures has the similar result. Therefore, the undoped FUSI gate is suitable applied in low temperature process.

On the other hand, there are some different phenomena shown in the n⁺ NiSi - gated MOS capacitor. We can see that, the sample still has good characteristics even

that treated by 800^oC RTA. During the silicidation process, phosphorous may react with nickel, and hence the nickel diffusion is retarded by phosphorous. Therefore, the gate oxide reliability is not affected by nickel obviously. Compared with the n⁺-NiSi gate based on the in-situ doped a-Si, dosages of the phosphorous in the both stacked structures are less and because of the content of the Ni is very large, the inhibition of nickel diffusion is not apparent as expected. In addition, the flat band voltage shift is caused by improving the uniformity of the NiSi film with the temperature. In brief, the work function of the n⁺ NiSi film is changed with temperature. In conclusion, the NiSi gate with tunable work function by dopants is promised for the nano-scale MOS device application.

簡歷

姓 名： 賴久盟

性 別： 男

出生日期： 中華民國六十九年一月四日

籍 貫： 台灣省 台中縣

地 址： 台中縣豐原市田心里大明路四十八號

學 歷： 國立成功大學 物理學系 (民國 91 年 6 月)

國立交通大學 電子研究所固態組 碩士班

（民國 93 年 7 月）

論文題目：鎳金屬矽化物與堆疊式結構對閘極氧化層可靠度之研究 The study of Gate Oxide Reliability with Nickel Silicides

and Stacked structures 電子郵件：duncans.ee91g@nctu.edu.tw

在文檔中 鎳金屬矽化物與堆疊式結構對閘極氧化層可靠度之研究 (頁 92-0)