Chapter 1 Introduction
1.2 Motivation
In order to investigate the suitability of the nickel silicide gate on the gate oxide, we carried out the FUSI NiSi gate with different temperature from 500oC to 800oC.
The diffusibility of nickel increases with temperature. Thus, when silicidation temperature is raised, the probability of that nickel diffuses through silicon into the oxide is enlarged. Then, nickel can react with dopants during the silicidation process, hence dopants maybe retard the nickel diffusion. In addition, stacked gate structures which were used to inhibit the boron penetration in past days could provide the silicide better thermal stability. Therefore, the nickel diffusion may be retarded by the interface of the stacked structure. We used different stacked gate structures of silicon to investigate this phenomenon.
1.3 Organization of the Thesis
In this thesis, we study the characteristics of the NiSi-gated MOS capacitors with various oxide thicknesses and based on different structures.
In Chapter 2, the characteristics of the undoped NiSi-gated MOS capacitors are presented.
In Chapter 3, the n+ NiSi-gated MOS capacitors are fabricated by PH3 in-situ doped.
In Chapter 4, the investigation of the NiSi-gated MOS capacitors based on stacked a-Si/poly-Si and poly-Si/a-Si structures are accomplished.
At the end of this thesis, conclusions are given in Chapter 5.
1.4 References
[1] T.Ghani, K.Mistry, P.Packan, S.Thompson, M.Stettler, S.Tyagi, and M.Bohr,
”Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors,” in Symp. VLSI Tech. Dig., pp.174-175, 2000.
[2] S.Takagi, M.Iwase, A.Toriumi, and H.Tango,”On the universality of inversion layer mobility in Si MOSFET’s : part I – effects of substrate impurity concentration,”IEEE Trans. Electron Devices,vol.41, pp.2357-2362, Dec. 1994.
[3] Y.Taur, C.H.Wann, and D.J.Frank,”25nm CMOS design considerations,” in IEDM
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IEEE, pp.537-569, April 1999.
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Kluwer, 1991.
[6] L.Chang, S.Tang, T.J.King, J.Bokor, and C.Hu,”Gate-length scaling and threshold voltage control of double-gate MOSFETs,” in IEDM Tech. Dig., pp.719-722, 2000.
[7] J.C. Sturm, K.Tokunaga, J.P. Colinge,”Increased drain saturation current in ultra-thin silicon-on-insulator (SOI) MOS transistors,” IEEE Electron Device Lett., vol.9, pp.460-463, Sept.1988.
[8] J.P. Colinge, presented at the 1987 SOS/SOI Technology Workshop, Durango, CO, Oct. 1987.
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[11] L.T.Su,“Sub-0.2µm silicon-on-insulator (SOI) CMOS : Opportunities and challenges,” in Proc. Ext. Abstr., 1995 Int. Conf. SSDM, Osaka,Japan, pp.542- 544, 1995.
[12] Y.Yamaguchi, T.Nishimura, Y.Akasaka, and K.Fujibayashi,”Self-aligned silicide technology for ultra-thin SIMOX MOSFETs,” IEEE Trans. Electron Devices, vol.39, pp.1179-1183, May 1992.
[13] H.Shimada, T.Ushiki, Y.Hirano, and T.Ohmi,”Tantalum-gate SOI MOSFET’s featuring threshold voltage control in low-power applications,” in Proc.1995
IEEE Int. SOI Conf. Proc., Tucson, AZ, 1995, pp.96 -97.
[14] H.Shimada, Y.Hirano, T.Ushiki, and T.Ohmi,”Threshold voltage adjustment in SOI MOSFET’s by employing tantalum for gate material,” in IEDM, Tech. Dig., pp.881-884, 1995.
[15] B.Cheng, B.Maiti, S.Samayedam, J.Grant, B.Taylor, P.Tobin, and J.Mogab,”
Metal Gates for Advanced sub-80-nm SOI CMOS technology,” in IEEE Intl. SOI.
Conf. Proc., 2001, pp.91-92.
[16] Q.Lu, R.Lin, P.Randae, T.J.King, and C.Hu,”Metal gate work function adjustment for future CMOS technology,” in Symp. VLSI Tech. Dig., pp.45-46, 2001.
[17] Peiqi Xuan and Jeffrey Bokor,”Investigation of NiSi and TiSi as CMOS Gate Materials,” IEEE Electron Device Lett., vol.24, no.10, pp.634-636, October 2003.
[18] B. Tavel, T. Skotnicki, G. Pares, N. Carriere, M. Rivoire, et al.,”Totally Silicided (CoSi2) polysilicon: a novel approach to very low-resistive gate (~2Ω/□) without metal CMP nor etching,” in IEDM Tech. Dig., pp.37.5.1-37.5.4, 2001.
[19] S. Monfray, T. Skotnicki, B. Tavel, Y. Morand, S. Descombes, et al.,“SON (silicon-On-Nothing) P-MOSFETs with totally silicide (CoSi2) Polysilicon on 5nm-thick Si-Films: The simplest way to integration of Metal Gates on thin FD channels,” in IEDM Tech. Dig., pp.263-266, 2002.
[20] Ming Oin, Vincent M. C. Poon and Stephen C. H. Ho,“Investigation of Polycrystalline Nickel Silicide Films as a Gate Material,” J. Electrochem. Soc., vol.148, no.5, pp.271-274, 2001.
[21] Z. Krivokapic, W. Masazara, K. Achutan, P. King, J. Gray,et al.,”Nickel Silicide Metal Gate FDSOI Devices with Improved Gate Oxide Leakage,” in IEDM Tech.
Dig., pp.271-274, 2002.
[22] J. H. Sim, H. C. Wen, J. P. Lu, and D. L. Kwong,”Dual Work Function Metal Gates Using Full Nickel Silicidation of Doped Poly-Si,” IEEE Electron Device
Lett., vol.24, no.10, pp.631-633, October 2003.
[23] W. P. Maszara, Z. Krivokapic, P. King, J. S. Goo, and M. R. Lin,”Transistors with Dual Work Function Metal Gates by Single Full Silicidation (FUSI) of Polysilicon Gates,” in IEDM Tech. Dig., pp.367-370, 2002.
[24] J. Kedzierski, D. Boyd, P. Ronsheim, S. Zafar, J. Newbury, et al.,”Threshold voltage control in NiSi-gated MOSFETs through silicidation induced impurity segregation (SIIS),” in IEDM Tech. Dig., pp.13.3.1-13.3.4, 2003.
[25] Z. Krivokapic, W. Masazara, F. Arasnia, E. Paton,Y. Kim, et al.,”High Performance 25nm FDSOI Devices with Extremely Thin Silicon Channel,” in
Symp. VLSI Tech. Dig., pp.131-132, 2003.
[26] Qi Xiang, Z. Krivokapic, W. Maszara, Ming-Ren Lin,“Extending the Life of N/O Stack Gate Dielectric with Gate Electrode Engineering,” in Gate Insulator, 2003.
IWGI 2003, Extended Abstracts of International Workshop on, 6-7 Nov. 2003
pp.134-139.
[27] J. Kedzierski, E. Nowak, T. Kanarsky, Y. Zhang, D. Boyd, et al.,”Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation,” in IEDM
Tech. Dig., pp.247-250, 2002.
[28] C. S. Park, B. J. Cho, and D. L. Kwong,“Thermally Stable Fully Silicided Hf-Silicide Metal-Gate Electrode,” in IEEE Electron Device Lett., vol.25, no.6, pp.372-374, June 2004.
[29] V. Misra, Zhong Huicai, H. Lazar, et al.,“Electrical properties of Ru-based alloy gate electrodes for dual metal gate Si-CMOS ,“ IEEE Electron Device Lett., vol.23, pp.354-356, June 2002.
[30] Jerome B. Lasky, James S. Nakos, Orison J. Cain, and P. J. Geiss,“Comparison of Transformation to Low-Resistivity Phase and Agglomeration of TiSi2 and CoSi2,” IEEE Trans. Electron Devices, vol. 38, pp.262-269, Feb. 1991.
[31] K.Maex,“Silicides for integrated circuits: TiSi2 and CoSi2,”Mater. Sci. Eng., R11 (1993) 53-153.
[32] N. S. Parekh, H. Roede, A. A. Bos, A. G. M. Jonkers, and R. D. J. Verhar,
“Characterization and implementation of self-aligned TiSi2 in submicrometer CMOS technology,” IEEE Trans. Electron Devices, vol.38, pp.88-94, Jan. 1991.
[33] T. Yamazaki, K. Goto, T. Fukano, Y. Nara, T. Sugii, T. Ito,”21 psec switching 0.1 µm-CMOS at room temperature using high performance Co salicide process,” in
IEDM Tech. Dig., pp.906-908, 1993.
[34] J. P. Gambino, E. G. Golgan and B. Cunningham, Abstract 216, The Electrochemical Society Extended Abstracts Meeting, Phoenix, AZ, October 1991, Eletrochem. Soc., Pennington, NJ, p.312, 1991.
[35] C. M. Osburn, Q. F. Wang, M. Kellam, C. A. Canovai, P. L. Smith, et al.,
”Incorporation of metal silicides and refractory metals in VLSI technology,”
Applied Surface Science, 53 (1991) 291-312.
[36] H. Jiang, C. M. Osburn, Z.-G. Xiao, G. McGuire and G. A. Rozgonyi,”Ultra Shallow Junction Formation Using Diffusion from silicides,” J. Electrochem.
Soc., 139 (1992) 211-218.
[37] T. Ohguro, S. Nakamura, M. Koike, T. Morimoto, A. Nishiyama, et al.,“Analysis of resistance behavior in Ti- and Ni-salicided polysilicon films” IEEE Trans.
Electron Devices, vol.41, pp.2305-2317, Dec. 1994.
[38] R. Mukai, S. Ozawa, H. Yagi and H. Tsuchikawa, VMIC Proc., 1994, p.343.
Chapter 2
Characteristics of NiSi gate structure based on undoped poly-Si and undoped a-Si
2.1 Introduction
In order to realize high performance sub-quarter-micrometer complementary metal-oxide-semiconductor (CMOS) devices, the reduction of the parasitic resistance of the source/drain and gate is essentially. The self-aligned silicide process has been widely used to satisfy this requirement. On the other hand, the metal silicide gate (FUSI gate) which is used to replace poly-silicon gate is investigated extensively such as TiSi2 [1], CoSi2 [2][3], HfSi [4], and NiSi [5] have been studied intensively.
Besides the characteristics of the small sheet resistance, the metal silicide gate can eliminate PDE effectively. Then, the Tox in the inversion region can be lowered and the device performance is improved. Moreover, when high-κ dielectrics are implemented to suppress the gate leakage, poly-silicon loses its thermal stability advantage over metals [6]. In addition, the metal silicide gate provides extra advantages over the metal gate. The metal dry etching can be avoided because silicides can be formed via a silicide reaction between silicon and metal [7].
However, the reliability of the gate oxide with silicide process is needed to take into consideration. The thermal stability of metal silicide is important, especially for higher temperature process after the silicidation. When carrying the silicide procedure out, the metal maybe diffuse through silicon into oxide. It once acts mobile ions or defects in the oxide, and the device performance will be degraded.
NiSi could be the optimum candidate for the future salicide application. It is because of its low resistivity, one-step annealing, less silicon consumption and non-linewidth effects. Furthermore, it is proved that oxide is a good barrier for nickel diffusion at low temperature. Hence, we want to search the FUSI NiSi gate accomplished by both low and high temperature and to observe the gate oxide reliability. In this work, FUSI NiSi gated-MOS capacitors based on undoped poly-Si and undoped a-Si with different silicidation temperature will be fabricated.
2.2 Experimental
In this Chapter, undoped-nickel-silicide (NiSi)-gated MOS capacitors on the
<100> p-type silicon substrate were fabricated. First, all 6-inch p-type silicon wafers were cleaned by standard RCA clean. Then, gate oxides (SiO2) with thickness of 35, 50, 75Å were grown in diluted O2 ambient (O2/N2 = 1/7) at 800oC by ASM A-400 Vertical Furnace system immediately. After that, two types of silicon gate were deposited in the same system. One is the undoped 600Å-thick poly-silicon (SP) gate deposited by silane gas (SiH4) at 623oC, and the other is the undoped 600Å-thick amorphous-silicon (SA) gate deposited by the same gas at 550oC. Prior to the nickel deposition, all wafers were dipped in a diluted HF solution (HF/H2O =1/100) to remove the native oxide on the silicon surface and then loaded into the metal
deposition chamber of Metal PVD system. A 450Å-thick nickel film was deposited at a pressure of 5x10-9 torr. In order to achieve the silicidation procedure, all samples were treated by rapid thermal annealed for 20 seconds in an N2 ambient at 500
~800oC by heatpulse 610 rapid thermal processing system. Thereafter, the unreacted nickel was removed by wet etching (H2SO4/H2O2= 3/1, 10mins) and a 5000Å-thick aluminum film was deposited on the silicide surface by sputter system. The gate electrode of the capacitor was patterned and defined by wet etching (H3PO4: HNO3:CH3COOH:H2O= 50:2:10:9 for aluminum etching; HNO3:NH4F:H2O=64:3:33 for silicide etching). Finally, a 5000Å-thick aluminum film was also deposited on the backside of the wafers to form the ohmic contact. The gate area is 7.85x10-5cm2.The cross-sectional view of the fabrication processes was shown in Fig. 2-1.Table 2-1 shows serial numbers of all samples.
The physical thicknesses of oxide, poly-Si, and a-Si were measured by N&K analyzer. The sheet resistance (Rs) of nickel silicide was obtained by four-point-probe analyzer. Electrical characteristics of all MOS capacitors were measured by using Hewlett-Packard 4156B (HP-4156B) semiconductor parameter analyzer. HP4284 LCR meter was used to extract the CV performance at high frequency (100K Hz).
2.3 Results and Discussion
In this section, some electrical and physical characteristics of undoped-NiSi -gated MOS capacitors will be discussed.
2.3.1. Sheet Resistance Versus RTA Temperature
The sheet resistance of the undoped-NiSi treated by different RTA temperature is
shown in Fig.2-2. We can see that the sheet resistance is still low after high temperature annealing. So, the sheet resistance of undoped-NiSi is still stable at both low and high silicidation temperature.
2.3.2 C-V and J-V Characteristics
The EOTs (Equivalent Oxide Thickness) were extracted from the equation shown as following :
C = εoεrA/d. (2-1) Where C is the capacitance value in the accumulation region (V = -2V) εo is the permittivity in vacuum (8.85418x10-14 F/cm)
εr is the dielectric constant of SiO2 (~ 3.9) A is the area of the capacitor
d is the effective oxide thickness
The current density (J) in J-V curve was obtained by using J=I/A, where A is the area of capacitor. The d is the effective oxide thickness (EOT) determined by the C-V measurement.
Fig.2-3 ~ Fig.2-8 show the C-V and J-V characteristics of MOS capacitors with different gate conditions. Undoped NiSi gates are based on poly-Si or a-Si, and are formed at different annealing temperatures. These figures are sorted by different oxide thicknesses of 35Å (Fig.2-3, Fig.2-6), 50Å (Fig.2-4, Fig.2-7), and 75Å (Fig.2-5, Fig.2-8). Fig.2-3~Fig.2-5 are capacitors with NiSi gates based on undoped poly-silicon; Fig.2-6~Fig.2-8 are those with NiSi gates based on undoped amorphous-silicon.
Fig.2-3(a) compares the high frequency (100K Hz) capacitance-voltage (C-V) characteristics for samples treated with different RTA temperatures. For these samples, the physical oxide thickness was targeted at 35Å for gate-oxide growth. In Fig.2-3(a), when the RTA peak temperature was raised from 500oC to 600oC, the measured capacitance in accumulation region (at V = -2V) increased by 14%. When the RTA temperature increased to 700oC, the capacitance value was slightly smaller than (but still close to) that of 600oC RTA-treated sample. However, when RTA temperature increased to 800oC, the capacitance value dropped dramatically.
Extracted from capacitances measured in accumulation region, the EOT values are also marked in Fig.2-3(a). For poly-Si samples, as the silicidation temperature was at 500oC, the EOT is larger than that at 600 and 700 oC slightly. This is because the poly-Si was not completely consumed by nickel in 20s annealing at 500oC. Hence, the capacitance is equal to the series of a thin poly-Si capacitor and an oxide capacitor, as eq. (2-2).
Ceq.=Cpoly-SiCox/(Cpoly-Si+Cox) (2-2).
On the other hand, the EOTs of 600 and 700oC (35.8Å and 36.7Å) are thinner, so the poly-Si films were totally transformed into NiSi, which is FUll-SIlicide (FUSI). And the EOT value can be attributed to the oxide capacitance only. The EOT of 600 and 700oC stayed close, which means the poly-Si was fully-silicided after the 600oC RTA, and stayed stable up to the 700oC RTA.
For the 800oC-annealed sample, the capacitance reduction was due to the largely increased leakage currents. As shown in Fig.2-3(b), when the annealing temperature is between 500~700oC, the J-V characteristics were similar. As the annealing temperature rising up to 800oC, the oxide leakage is very large, and the J-V curve exhibits a resistor’s behavior. The leakage is attributed to large amounts of nickel diffusing into the oxide at 800oC, which resulted in server damages on the oxide
integrity.
Fig.2-4 and Fig.2-5 are samples with gate-oxide thickness targeted at 50 Å and 75Å, respectively. With thicker gate-oxides, the capacitance value could remain stable with RTA temperature up to 800oC, which implies smaller leakage currents through the thicker oxide. However, the severe oxide-quality degradation still happened after 800oC RTA. In Fig.2-4(b) and Fig.2-5(b), the 800oC annealed sample exhibits distorted J-V curves and earlier breakdown.
Thicker gate-oxides provided tolerance for Ni diffusion at higher temperatures, and hence broaden the process window. However, because FUSI process is considered as a metal-gate process for advanced ultra-thin-oxide devices, the RTA temperature control will be very important.
Fig.2-6(a) and (b) demonstrate samples with NiSi-gates formed from amorphous-silicon. The gate-oxide thickness target was set at 35 Å. In Fig.2-6(a), the smallest EOT value (36.2Å) is extracted from the 700oC annealed sample. This result gives us a hint that using amorphous-silicon for FUSI process may improve the process window to higher RTA temperature without compromising the EOT value. In Fig.2-7 and Fig.2-8, large capacitance values and small EOTs were achieved right after 500oC RTA treatment. This means 500oC annealing is enough for FUSI process while using amorphous-silicon.
Fig.2-9(a) and (b) summarize the oxide thickness measured by an optical analyzer, and the EOT versus RTA-temperature plots for different conditions.
2.3.3 Characteristics of Gate-leakage Current Density
Fig.2-10 (a) and (b) show the Weibull plot of the leakage current density at Vg = -1V for 35Å-thick oxide treated by different silicidation temperatures. From Fig.2-10, distributions of the leakage current at temperature from 500 ~ 700oC are at the same
order and uniform. On the other hand, the characteristics of the sample treated by 800oC silicidation are degraded dramatically. The samples of 50Å- and 75Å-thick oxide have the same trend, so these are not shown.
2.3.4 Characteristics of Electric Breakdown Field
Fig.2-11(a) and (b) show the weibull plot of the electric breakdown field (EBD) for 35Å-thick oxide treated by different silicidation temperatures. The electric breakdown field of the sample treated by different silicidation temperatures is similar and uniform except the 800oC RTA. The samples of 50Å- and 75Å-thick oxide have the same trend. For samples treated by the 800oC RTA, the electric breakdown field is lowered obviously.
2.3.5 Measurement of Effective Barrier Height
The effective barrier height could be deduced from the Fowler-Nordheim tunneling equation. We use the J-E curve in the accumulation region to extract the electron barrier height from nickel silicide to the oxide and use the J-E curve in the inversion region by the illumination of light to extract the electron barrier height from the silicon substrate to the oxide. Based on the F-N tunneling model:
J=AEOX2exp(-B/EOX) (2-3) ln(J/EOX2) = lnA –B/EOX (2-4) Where J = gate current density (A/cm2)
E = electric field of oxide (MV/cm)
A = m0q3/(16π2ħm*ΦB) ~ 3.471x10-6ΦB-1 (for m* = 0.47m0) B = 4(2m*)1/2(ΦB)3/2/(3qħ) ~ 46.8ΦB3/2 (for m* = 0.47m0)
From the plot of J/EOX2 versus 1/EOX plot, the slope (B) gives the tunneling barrier height (ΦB).Fig.2-12 and Fig.2-13 are the F-N fitting extracted from the sample SP7-700 and SA7-700. Fig.2-12(a) and Fig.2-13(a) were extracted from the gate injection (NiSi→SiO2).Fig.2-12(b) and Fig.2-13(b) were extracted from the substrate injection (Si→SiO2).The ΦB(NiSi→SiO2) is about 3.54eV for SP7-700 and 3.60eV for SA7-700.The ΦB(Si→SiO2) is about 2.90eV for SP-700 and 3.15eV for SA7-700 Thereafter, the electron barrier height versus RTA temperature was shown in Fig.2-14 and Fig.2-15 . In Fig.2-14(a) and Fig.2-15(a), the ΦB (NiSi→SiO2) increases with the RTA temperature up to 700oC and decreases at 800oC (ΦB=2.78eV for SP7-800 and 3.42eV for SA7-800). This is due to J-V curves of the sample SP7-800 and SA7-800 (as shown in Fig.2-5(b) and Fig.2-8(b)) were destroyed and these were because that oxides were degraded by high silicidation temperature as mentioned above.
In summary, most of the electrical characteristics mentioned above are concluded in Table.2-2 and Table.2-3.
2.4 Summary
In this chapter, characteristics of the fabricated undoped-NiSi gated MOS capacitors based on poly-Si and a-Si with different silicidaion temperatures are presented. The sheet resistance of the NiSi gate is low enough, and it solves the issue of the series resistance. For the sample with silicidation at 500oC, 20s annealing is not enough to consume silicon completely. On the other hand, for the samples with the
800oC RTA, the temperature is too high, hence, much nickel diffuses into the oxide and induces large oxide leakages. Furthermore, the electron barrier height of the gate injection is higher than the poly-Si gate, it is because the work function of the NiSi is larger.
In a word, undoped NiSi gate with low temperature annealing is suited to low temperature process for the future.
2.5 References
[1] Peiqi Xuan and Jeffrey Bokor,”Investigation of NiSi and TiSi as CMOS Gate Materials,” IEEE Electron Device Lett., vol.24, no.10, pp.634-636, October 2003.
[2] B. Tavel, T. Skotnicki, G.. Pares, N. Carriere, M. Rivoire, et al,”Totally Silicided (CoSi2) polysilicon : a novel approach to very low-resistive gate (~2Ω/□) without metal CMP nor etching,” in IEDM Tech. Dig., pp.37.5.1-37.5.4, 2001.
[3] S. Monfray, T. Skotnicki, B. Tavel, Y. Morand, S. Descombes, et al., “SON (silicon-On-Nothing) P-MOSFETs with totally silicide (CoSi2) Polysilicon on 5nm-thick Si-Films: The simplest way to integration of Metal Gates on thin FD channels,” in IEDM Tech. Dig., pp.263-266, 2002.
[4] C. S. Park, B. J. Cho, and D. L. Kwong,“Thermally Stable Fully Silicided Hf-Silicide Metal-Gate Electrode,” in IEEE Electron Device Lett., vol.25, no.6, pp.372-374, June 2004.
[5] J. Kedzierski, E. Nowak, T. Kanarsky, Y. Zhang, D. Boyd, et al.,”Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation,” in IEDM
Tech. Dig., pp.247-250, 2002.
[6] I.Polishchuk, P.Ranade, T.-J.King, C.Hu,”Dual work function metal gate CMOS transistors by Ni-Ti interdiffusion,” IEEE Electron Deice Lett., vol.23, pp.200-202, Apr.2002.
[7] M.C.Poon, F.Deng, H.Wong, M.Wong, J.K.O.Sin, S.S.Lan, C.H.Ho, and P.G.Han,”Thermal Stability of cobalt and nickel silicides in amorphous and crystalline silicon,” in IEEE Proc. Hong Kong Electro Devices Meeting, pp.65-68, 1997.
1. RCA cleaning
2. Growth of gate oxide (SiO2): 35 , 50 , 75Å 3. Deposition of silicon gate :
(A) undoped polysilicon (SP), 600Å
(B) undoped amorphous silicon (SA), 600Å
4. Dip diluted HF
5. Deposition of metal : Ni, 450Å
6. Silicidation : RTA 500, 600, 700, 800oC, 20s 7. Removing unreacted nickel :
H2SO4/H2O2 (3/1), 10 mins
8. Deposition of aluminum : Al, 5000Å (front) 9. Mask #1
10. Deposition of aluminum : Al, 5000Å (back)
Fig. 2-1 Process flow of the undoped NiSi-gated MOS capacitor formation.
p-Si <100>
p-Si <100>
p-Si <100>
p-Si <100>
Table. 2-1
gate RTA(
oC)
T
OX(A) 500 600 700 800
35
SP3-500 SP3-600 SP3-700 SP3-80050
SP5-500 SP5-600 SP5-700 SP5-800poly-Si
75
SP7-500 SP7-600 SP7-700 SP7-80035
SA3-500 SA3-600 SA3-700 SA3-80050
SA5-500 SA5-600 SA5-700 SA5-800a-Si
75
SA7-500 SA7-600 SA7-700 SA7-800Fig.2-2(a) Sheet resistance vs. RTA temperature. The plot shows the sheet resistance of the poly-Si/SiO2 structure with 500~800oC RTA.
Fig.2-2(b) Sheet resistance vs. RTA temperature. The plot shows the sheet resistance of the a-Si/SiO2 structure with 500~800oC RTA.
RTA temperature (oC)
500 600 700 800
Rs (ohm/square)
1 2 3 4 5
SP3
SP7 SP5
RTA Temperature (oC)
500 600 700 800
R
s( ohm/square)
1 2 3 4 5
SA3
SA7 SA5
Fig.2-3(a) High frequency capacitance vs. gate voltage. The plot shows the C-V of the poly-Si/SiO2(35Å) structure with 500~800oC RTA.
Fig.2-3(a) High frequency capacitance vs. gate voltage. The plot shows the C-V of the poly-Si/SiO2(35Å) structure with 500~800oC RTA.