Chapter 2 Characteristics of NiSi gate structure based on undoped poly-Si and
2.3 Results and Discussion
In this section, some electrical and physical characteristics of undoped-NiSi -gated MOS capacitors will be discussed.
2.3.1. Sheet Resistance Versus RTA Temperature
The sheet resistance of the undoped-NiSi treated by different RTA temperature is
shown in Fig.2-2. We can see that the sheet resistance is still low after high temperature annealing. So, the sheet resistance of undoped-NiSi is still stable at both low and high silicidation temperature.
2.3.2 C-V and J-V Characteristics
The EOTs (Equivalent Oxide Thickness) were extracted from the equation shown as following :
C = εoεrA/d. (2-1) Where C is the capacitance value in the accumulation region (V = -2V) εo is the permittivity in vacuum (8.85418x10-14 F/cm)
εr is the dielectric constant of SiO2 (~ 3.9) A is the area of the capacitor
d is the effective oxide thickness
The current density (J) in J-V curve was obtained by using J=I/A, where A is the area of capacitor. The d is the effective oxide thickness (EOT) determined by the C-V measurement.
Fig.2-3 ~ Fig.2-8 show the C-V and J-V characteristics of MOS capacitors with different gate conditions. Undoped NiSi gates are based on poly-Si or a-Si, and are formed at different annealing temperatures. These figures are sorted by different oxide thicknesses of 35Å (Fig.2-3, Fig.2-6), 50Å (Fig.2-4, Fig.2-7), and 75Å (Fig.2-5, Fig.2-8). Fig.2-3~Fig.2-5 are capacitors with NiSi gates based on undoped poly-silicon; Fig.2-6~Fig.2-8 are those with NiSi gates based on undoped amorphous-silicon.
Fig.2-3(a) compares the high frequency (100K Hz) capacitance-voltage (C-V) characteristics for samples treated with different RTA temperatures. For these samples, the physical oxide thickness was targeted at 35Å for gate-oxide growth. In Fig.2-3(a), when the RTA peak temperature was raised from 500oC to 600oC, the measured capacitance in accumulation region (at V = -2V) increased by 14%. When the RTA temperature increased to 700oC, the capacitance value was slightly smaller than (but still close to) that of 600oC RTA-treated sample. However, when RTA temperature increased to 800oC, the capacitance value dropped dramatically.
Extracted from capacitances measured in accumulation region, the EOT values are also marked in Fig.2-3(a). For poly-Si samples, as the silicidation temperature was at 500oC, the EOT is larger than that at 600 and 700 oC slightly. This is because the poly-Si was not completely consumed by nickel in 20s annealing at 500oC. Hence, the capacitance is equal to the series of a thin poly-Si capacitor and an oxide capacitor, as eq. (2-2).
Ceq.=Cpoly-SiCox/(Cpoly-Si+Cox) (2-2).
On the other hand, the EOTs of 600 and 700oC (35.8Å and 36.7Å) are thinner, so the poly-Si films were totally transformed into NiSi, which is FUll-SIlicide (FUSI). And the EOT value can be attributed to the oxide capacitance only. The EOT of 600 and 700oC stayed close, which means the poly-Si was fully-silicided after the 600oC RTA, and stayed stable up to the 700oC RTA.
For the 800oC-annealed sample, the capacitance reduction was due to the largely increased leakage currents. As shown in Fig.2-3(b), when the annealing temperature is between 500~700oC, the J-V characteristics were similar. As the annealing temperature rising up to 800oC, the oxide leakage is very large, and the J-V curve exhibits a resistor’s behavior. The leakage is attributed to large amounts of nickel diffusing into the oxide at 800oC, which resulted in server damages on the oxide
integrity.
Fig.2-4 and Fig.2-5 are samples with gate-oxide thickness targeted at 50 Å and 75Å, respectively. With thicker gate-oxides, the capacitance value could remain stable with RTA temperature up to 800oC, which implies smaller leakage currents through the thicker oxide. However, the severe oxide-quality degradation still happened after 800oC RTA. In Fig.2-4(b) and Fig.2-5(b), the 800oC annealed sample exhibits distorted J-V curves and earlier breakdown.
Thicker gate-oxides provided tolerance for Ni diffusion at higher temperatures, and hence broaden the process window. However, because FUSI process is considered as a metal-gate process for advanced ultra-thin-oxide devices, the RTA temperature control will be very important.
Fig.2-6(a) and (b) demonstrate samples with NiSi-gates formed from amorphous-silicon. The gate-oxide thickness target was set at 35 Å. In Fig.2-6(a), the smallest EOT value (36.2Å) is extracted from the 700oC annealed sample. This result gives us a hint that using amorphous-silicon for FUSI process may improve the process window to higher RTA temperature without compromising the EOT value. In Fig.2-7 and Fig.2-8, large capacitance values and small EOTs were achieved right after 500oC RTA treatment. This means 500oC annealing is enough for FUSI process while using amorphous-silicon.
Fig.2-9(a) and (b) summarize the oxide thickness measured by an optical analyzer, and the EOT versus RTA-temperature plots for different conditions.
2.3.3 Characteristics of Gate-leakage Current Density
Fig.2-10 (a) and (b) show the Weibull plot of the leakage current density at Vg = -1V for 35Å-thick oxide treated by different silicidation temperatures. From Fig.2-10, distributions of the leakage current at temperature from 500 ~ 700oC are at the same
order and uniform. On the other hand, the characteristics of the sample treated by 800oC silicidation are degraded dramatically. The samples of 50Å- and 75Å-thick oxide have the same trend, so these are not shown.
2.3.4 Characteristics of Electric Breakdown Field
Fig.2-11(a) and (b) show the weibull plot of the electric breakdown field (EBD) for 35Å-thick oxide treated by different silicidation temperatures. The electric breakdown field of the sample treated by different silicidation temperatures is similar and uniform except the 800oC RTA. The samples of 50Å- and 75Å-thick oxide have the same trend. For samples treated by the 800oC RTA, the electric breakdown field is lowered obviously.
2.3.5 Measurement of Effective Barrier Height
The effective barrier height could be deduced from the Fowler-Nordheim tunneling equation. We use the J-E curve in the accumulation region to extract the electron barrier height from nickel silicide to the oxide and use the J-E curve in the inversion region by the illumination of light to extract the electron barrier height from the silicon substrate to the oxide. Based on the F-N tunneling model:
J=AEOX2exp(-B/EOX) (2-3) ln(J/EOX2) = lnA –B/EOX (2-4) Where J = gate current density (A/cm2)
E = electric field of oxide (MV/cm)
A = m0q3/(16π2ħm*ΦB) ~ 3.471x10-6ΦB-1 (for m* = 0.47m0) B = 4(2m*)1/2(ΦB)3/2/(3qħ) ~ 46.8ΦB3/2 (for m* = 0.47m0)
From the plot of J/EOX2 versus 1/EOX plot, the slope (B) gives the tunneling barrier height (ΦB).Fig.2-12 and Fig.2-13 are the F-N fitting extracted from the sample SP7-700 and SA7-700. Fig.2-12(a) and Fig.2-13(a) were extracted from the gate injection (NiSi→SiO2).Fig.2-12(b) and Fig.2-13(b) were extracted from the substrate injection (Si→SiO2).The ΦB(NiSi→SiO2) is about 3.54eV for SP7-700 and 3.60eV for SA7-700.The ΦB(Si→SiO2) is about 2.90eV for SP-700 and 3.15eV for SA7-700 Thereafter, the electron barrier height versus RTA temperature was shown in Fig.2-14 and Fig.2-15 . In Fig.2-14(a) and Fig.2-15(a), the ΦB (NiSi→SiO2) increases with the RTA temperature up to 700oC and decreases at 800oC (ΦB=2.78eV for SP7-800 and 3.42eV for SA7-800). This is due to J-V curves of the sample SP7-800 and SA7-800 (as shown in Fig.2-5(b) and Fig.2-8(b)) were destroyed and these were because that oxides were degraded by high silicidation temperature as mentioned above.
In summary, most of the electrical characteristics mentioned above are concluded in Table.2-2 and Table.2-3.