Chapter 2 Characteristics of NiSi gate structure based on undoped poly-Si and
2.4 Summary
In this chapter, characteristics of the fabricated undoped-NiSi gated MOS capacitors based on poly-Si and a-Si with different silicidaion temperatures are presented. The sheet resistance of the NiSi gate is low enough, and it solves the issue of the series resistance. For the sample with silicidation at 500oC, 20s annealing is not enough to consume silicon completely. On the other hand, for the samples with the
800oC RTA, the temperature is too high, hence, much nickel diffuses into the oxide and induces large oxide leakages. Furthermore, the electron barrier height of the gate injection is higher than the poly-Si gate, it is because the work function of the NiSi is larger.
In a word, undoped NiSi gate with low temperature annealing is suited to low temperature process for the future.
2.5 References
[1] Peiqi Xuan and Jeffrey Bokor,”Investigation of NiSi and TiSi as CMOS Gate Materials,” IEEE Electron Device Lett., vol.24, no.10, pp.634-636, October 2003.
[2] B. Tavel, T. Skotnicki, G.. Pares, N. Carriere, M. Rivoire, et al,”Totally Silicided (CoSi2) polysilicon : a novel approach to very low-resistive gate (~2Ω/□) without metal CMP nor etching,” in IEDM Tech. Dig., pp.37.5.1-37.5.4, 2001.
[3] S. Monfray, T. Skotnicki, B. Tavel, Y. Morand, S. Descombes, et al., “SON (silicon-On-Nothing) P-MOSFETs with totally silicide (CoSi2) Polysilicon on 5nm-thick Si-Films: The simplest way to integration of Metal Gates on thin FD channels,” in IEDM Tech. Dig., pp.263-266, 2002.
[4] C. S. Park, B. J. Cho, and D. L. Kwong,“Thermally Stable Fully Silicided Hf-Silicide Metal-Gate Electrode,” in IEEE Electron Device Lett., vol.25, no.6, pp.372-374, June 2004.
[5] J. Kedzierski, E. Nowak, T. Kanarsky, Y. Zhang, D. Boyd, et al.,”Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation,” in IEDM
Tech. Dig., pp.247-250, 2002.
[6] I.Polishchuk, P.Ranade, T.-J.King, C.Hu,”Dual work function metal gate CMOS transistors by Ni-Ti interdiffusion,” IEEE Electron Deice Lett., vol.23, pp.200-202, Apr.2002.
[7] M.C.Poon, F.Deng, H.Wong, M.Wong, J.K.O.Sin, S.S.Lan, C.H.Ho, and P.G.Han,”Thermal Stability of cobalt and nickel silicides in amorphous and crystalline silicon,” in IEEE Proc. Hong Kong Electro Devices Meeting, pp.65-68, 1997.
1. RCA cleaning
2. Growth of gate oxide (SiO2): 35 , 50 , 75Å 3. Deposition of silicon gate :
(A) undoped polysilicon (SP), 600Å
(B) undoped amorphous silicon (SA), 600Å
4. Dip diluted HF
5. Deposition of metal : Ni, 450Å
6. Silicidation : RTA 500, 600, 700, 800oC, 20s 7. Removing unreacted nickel :
H2SO4/H2O2 (3/1), 10 mins
8. Deposition of aluminum : Al, 5000Å (front) 9. Mask #1
10. Deposition of aluminum : Al, 5000Å (back)
Fig. 2-1 Process flow of the undoped NiSi-gated MOS capacitor formation.
p-Si <100>
p-Si <100>
p-Si <100>
p-Si <100>
Table. 2-1
gate RTA(
oC)
T
OX(A) 500 600 700 800
35
SP3-500 SP3-600 SP3-700 SP3-80050
SP5-500 SP5-600 SP5-700 SP5-800poly-Si
75
SP7-500 SP7-600 SP7-700 SP7-80035
SA3-500 SA3-600 SA3-700 SA3-80050
SA5-500 SA5-600 SA5-700 SA5-800a-Si
75
SA7-500 SA7-600 SA7-700 SA7-800Fig.2-2(a) Sheet resistance vs. RTA temperature. The plot shows the sheet resistance of the poly-Si/SiO2 structure with 500~800oC RTA.
Fig.2-2(b) Sheet resistance vs. RTA temperature. The plot shows the sheet resistance of the a-Si/SiO2 structure with 500~800oC RTA.
RTA temperature (oC)
500 600 700 800
Rs (ohm/square)
1 2 3 4 5
SP3
SP7 SP5
RTA Temperature (oC)
500 600 700 800
R
s( ohm/square)
1 2 3 4 5
SA3
SA7 SA5
Fig.2-3(a) High frequency capacitance vs. gate voltage. The plot shows the C-V of the poly-Si/SiO2(35Å) structure with 500~800oC RTA.
Fig.2-3(b) Gate leakage current density vs. gate voltage. The plot shows the J-V of the poly-Si/SiO2(35Å) structure with 500~800oC RTA.
0
Fig.2-4(a) High frequency capacitance vs. gate voltage. The plot shows the C-V of the poly-Si/SiO2(50Å) structure with 500~800oC RTA.
Fig.2-4(b) Gate leakage current density vs. gate voltage. The plot shows the J-V of the poly-Si/SiO2(50Å) structure with 500~800oC RTA.
0
Fig.2-5(a) High frequency capacitance vs. gate voltage. The plot shows the C-V of the poly-Si/SiO2(75Å) structure with 500~800oC RTA.
Fig.2-5(b) Gate leakage current density vs. gate voltage. The plot shows the J-V of the poly-Si/SiO2(75Å) structure with 500~800oC RTA.
0
Fig.2-6(a) High frequency capacitance vs. gate voltage. The plot shows the C-V of the a-Si/SiO2(35Å) structure with 500~800oC RTA.
Fig.2-6(b) Gate leakage current density vs. gate voltage. The plot shows the J-V of the a-Si/SiO2(35Å) structure with 500~800oC RTA.
0
Fig.2-7(a) High frequency capacitance vs. gate voltage. The plot shows the C-V of the a-Si/SiO2(50Å) structure with 500~800oC RTA.
Fig.2-7(b) Gate leakage current density vs. gate voltage. The plot shows the J-V of the a-Si/SiO2(50Å) structure with 500~800oC RTA.
0
Fig.2-8(a) High frequency capacitance vs. gate voltage. The plot shows the C-V of the a-Si/SiO2(75Å) structure with 500~800oC RTA.
Fig.2-8(b) Gate leakage current density vs. gate voltage. The plot shows the J-V of the a-Si/SiO2(75Å) structure with 500~800oC RTA.
0
Fig.2-9(a) Oxide thickness vs. RTA temperature. The plot shows the EOT of the poly-Si/SiO2 structure with 500~800oC RTA, and the physical oxide thickness measured by N&K analyzer.
Fig.2-9(b) Oxide thickness vs. RTA temperature. The plot shows the EOT of the a-Si/SiO2 structure with 500~800oC RTA, and the physical oxide thickness measured by N&K analyzer.
N&K 500 600 700 800
SP3 SP5 SP7
T OX (A)
RTA tempeature (oC)
81.7
N&K 500 600 700 800
SA3 SA5 SA7
RTA Temperature (oC) T OX (A)
Fig.2-10(a) The Weibull plot shows the leakage current densities at Vg=-1V for the poly-Si/SiO2(35Å) structure with 500~800oC RTA.
Fig.2-10(b) The Weibull plot shows the leakage current densities at Vg=-1V for the a-Si/SiO2(35Å) structure with 500~800oC RTA.
-3
Fig.2-11(a) The Weibull plot shows the electric breakdown field for the poly-Si/SiO2
(35Å) structure with 500~700oC RTA.
Fig.2-11(b) The Weibull plot shows the electric breakdown field for the a-Si/SiO2
(35Å) structure with 500~700oC RTA.
-3
Fig.2-12(a) The plot shows F-N fitting in the accumulation region of the poly-Si/SiO2
(75Å) structure with 700oC RTA.
Fig.2-12(b) The plot shows F-N fitting in the inversion region of the poly-Si/SiO2
(75Å) structure with 700oC RTA. fitting eq. : y = 5.7786e-06 * e^(311.15x) Barrier Height : 3.54 eV
1/EOX (cm/MV)
0.095 0.105 0.115 0.125 0.135
1/EOX (cm/MV)
SP 7-700 : poly-Si 600 A / SiO
2 76 A undoped
M-RTA 700 oC , 20 s fitting eq. : y = 3.8865e-07 * e^(-231.4x) Barrier Height : 2.90 eV
J/E OX 2 (A / V2 )
Fig.2-13(a) The plot shows F-N fitting in the accumulation region of the a-Si/SiO2
(75Å) structure with 700oC RTA.
Fig.2-13(b) The plot shows F-N fitting in the inversion region of the a-Si/SiO2(75Å) structure with 700oC RTA.
10-21 fitting eq. : y = 2.3193e-05 * e^(319.15x) Barrier Height : 3.60 eV
J/E OX fitting eq. : y = 1.0081e-06 * e^(-261.8x) Barrier Height : 3.15eV
J/E OX 2 (A / V2 )
1/EOX (cm/MV)
Fig.2-14(a) Electron barrier height vs. RTA temperature. The plot shows the electron barrier height of the poly-Si/SiO2(75Å) structure with 500~800oC RTA.
Fig.2-14(b) Electron barrier height vs. RTA temperature. The plot shows the electron barrier height of the poly-Si/SiO2(50Å) structure with 500~700oC RTA.
0
RTA Temperature (oC) e- Barrier Height (eV)
RTA Temperature (oC)
SP 5 : poly-Si 600 A / SiO
Fig.2-15(a) Electron barrier height vs. RTA temperature. The plot shows the electron barrier height of the a-Si/SiO2(75Å) structure with 500~800oC RTA.
Fig.2-15(b) Electron barrier height vs. RTA temperature. The plot shows the electron barrier height of the a-Si/SiO2 (50Å) structure with 500~700oC RTA.
0
RTA Temperature (oC) e- Barrier Height (eV)
RTA Temperature (oC)
e- Barrier Height (eV) 3.35 3.38 3.40
2.61 2.62
Table. 2-2 (a)
SP3 SP3-500 SP3-600 SP3-700 SP3-800
C (pF)
66.3 75.7 73.9 41.3SP5 SP5-500 SP5-600 SP5-700 SP5-800
C (pF)
45.6 52.5 53.3 54.3SP7 SP7-500 SP7-600 SP7-700 SP7-800
C (pF)
33.2 35.8 35.3 35.7(gate injection)
3.39 3.54 3.54 2.78Φ
B(eV)
(sub. injection)
2.83 2.84 2.78 2.58Table. 2-3 (a)
SA3 SA3-500 SA3-600 SA3-700 SA3-800
C (pF)
71.1 70.8 74.8 57.7SA5 SA5-500 SA5-600 SA5-700 SA5-800
C (pF)
55.3 54.8 54.3 54.4(gate injection)
3.35 3.38 3.40 ---Φ
B(eV)
(sub. injection)
2.61 2.62 2.63 ---Table. 2-3(c)
SA7 SA7-500 SA7-600 SA7-700 SA7-800
C (pF)
35.8 36.4 35.0 36.1(gate injection)
3.52 3.59 3.60 3.42Φ
B(eV)
(sub. injection)
2.83 2.86 3.15 2.79Chapter 3
Characteristics of NiSi gate structure based on in-situ doped
3.1 Introduction
As the gate length is aggressively scaled down to sub-80-nm, metal gates are promised to substitute for the poly-Si gate. Then, the appropriate threshold voltage requires the work function of metal gates ranging from 4.1-4.4eV for NMOS and 4.8-5.1eV for PMOS [1]. In order to optimize the threshold voltage, metal gates need the tunable work function. There are some of methods for this purpose like MIG (metal interdiffusion gate) and nitrogen implantation to a metal. For the simplification of process integration, the single metal is required to be used for both NMOS and PMOS. Besides metals, the NiSi gate is also suitable for work function engineering.
The work function of the NiSi is about 4.81 ~ 4.9eV [2]. Tuning the work function of NiSi is carried out by doping the impurity into the poly-Si before the silicidation [3]~[5]. Then, the pileup of dopants in the NiSi/SiO2 interface during silicidation is believed the reason to cause the change of the work function [5].
Therefore, the single NiSi gate with different dopants can be applied in the
deep-scaled bulk CMOS and FDSOI MOSFETs. Then, it does not need the channel doping additionally, and hence this will improve the electron and hole mobility immediately.
As scaling down, the thickness of the gate is decreased at the same time.
Therefore, it is needed the lower energy implantation for the gate doping. However, it will result in the non uniform distribution of dopants. Moreover, the in-situ dope is a useful solution for this issue. In silicon, the concentration of the impurity which is doped by in-situ doped is more uniform.
In this chapter, we will fabricate the n+ NiSi-gated MOS capacitors based on PH3
in-situ doped method. Then, we use the different silicidation temperature to research the flat band voltage difference with temperature and the gate oxide reliability.
3.2 Experimental
The n+ nickel-silicide (NiSi)-gated MOS capacitor is fabricated on the <100>
p-type silicon wafer. After standard RCA clean. Gate oxides (SiO2) of 35, 50, 75Å-thick were grown in diluted dry O2 (O2/N2 = 1/7) at 800oC by ASM A-400 Vertical Furnace system immediately. Thereafter, the 600Å-thick in-situ doped amorphous silicon gate (IA) was deposited by SiH4/PH3 mixture at 550oC in the same system. Then, dopants were activated for 30 seconds at 900oC by Heatpulse 610i rapid thermal processing system. Prior to nickel deposition, all wafers were dipped in a diluted HF solution (HF/H2O = 1/100) to remove the native oxide on the silicon surface and then loaded into the metal deposition chamber of Metal PVD system. A 450Å-thick nickel film was deposited on the doped silicon surface at a pressure of 5x10-9 torr. In order to achieve the silicidation procedure, all samples were treated by
rapid thermal annealed for 20 seconds in an N2 ambient at 500~800oC by heatpulse 610 rapid thermal processing system. After that, the unreacted nickel was removed by wet etching (H2SO4/H2O2 = 3/1,10mins) and a 5000Å-thick aluminum film was deposited on the silicide surface of all samples by sputter system. The gate electrode of the capacitor was patterned and defined by wet etching (H3PO4: HNO3: CH3COOH:H2O = 50:2:10:9 for aluminum etching; HNO3:NH4F:H2O=64:3:33 for silicide etching). Finally, A 5000Å-thick aluminum film was also deposited on the backside of the wafer to form the ohmic contact. For comparison, the control sample was fabricated with the same procedure except the nickel deposition and the silicidation process. The gate area is 7.85x10-5cm2. The cross-sectional view of the fabrication processes was shown in Fig. 3-1.Table 3-1 shows serial numbers of all samples.
The physical thicknesses of oxide and n+ a-Si were measured by N&K analyzer.
The Sheet resistance (Rs) of nickel silicide was obtained by four-point-probe analyzer.
Electrical characteristics of all MOS capacitors were measured by using Hewlett-Packard 4156B (HP-4156B) semiconductor parameter analyzer. HP4284 LCR meter was used to extract the CV performance at high frequency (100K Hz).
3.3 Results and Discussion
3.3.1 Sheet Resistance Versus RTA Temperature
Fig.3.2 is the sheet resistance of the n+-doped NiSi gate versus different silicidation temperatures for the 35Å-, 50Å-, 75Å-thick oxide. The sheet resistance increased slightly with the silicidation temperature, but all of them were smaller than 5Ω/□. However, the sheet resistance of the control samples (IA3-C, IA5-C, IA7-C)
only treated by dopant activated was about~140 Ω/□ which was very larger compared with that of the NiSi gate.
3.3.2 Transmission Electron Microscope Image
Fig.3-3(a) shows the TEM image of the 35Å-thick oxide with the n+ a-Si gate.
The thicknesses of the n+ a-Si and the oxide are about 619Å and 38.1Å. Fig.3-3(b) and Fig.3-3(c) show the TEM image of the 35Å-thick oxide with n+-NiSi gate treated by the 500oC and 800oC silicidation. In Fig.3-3(b), the thickness of NiSi is about 756Å and the NiSi film is not very uniform. There were few residues of silicon near the n+ a-Si/SiO2 interface which were not reacted with nickel. However, in Fig.3-3(c), the thickness of NiSi is about 750Å, and the NiSi film is more uniform.
3.3.3 C-V and J-V Characteristics of n
+-NiSi-gated MOS capacitors
First of all, the C-V curve was measured by sweeping the gate voltage from the inversion region to the accumulation region (1V→-2V) and the J-V curve was measured in the accumulation region.Fig.3-4 to Fig.3-6 are C-V and J-V curves of n+-NiSi-gated MOS capacitors for different oxide thickness. In Fig.3-4(a), compared with the sample IA3-C, the capacitance of the NiSi sample increased with the silicidation temperature approximately. Because of reducing the gate sheet resistance (140Ω/□→2~4Ω/□), and therefore we acquired smaller EOT from the NiSi sample. In addition, while the silicidation temperature is raised, the C-V curve shifts to the right side, hence the flat-band (VFB) increased. It may be due to the change of the gate work function by reacting between nickel and phosphorous in n+ a-Si with different
temperatures. So that, n+ NiSi has different work function with n+ a-Si. There may be some reasons for this phenomenon: First, As shown in the TEM image (Fig.3-3 (b)), we can see that the reaction of nickel and n+ a-Si is not uniform at 500oC. It means that there were few residues of silicon near the interface between n+ a-Si and the oxide did not transform to NiSi. As the temperature is increased, the formation of NiSi is more uniform. This may be one of reasons for VFB shift from 500 to 800oC. Second, the bonding of Ni, P and Si may be different with the temperature. In other words, the composition of the NiSi film may be different with the temperature and hence the work function of the n+-NiSi film is changed with the temperature. The VFB shift is shown in Table.3-2. Something is worthy to notice, it is that the C-V curve is not distortion at 800oC. This is different with the result of the undpoed-NiSi gate as mentioned in chapter 2. Fig.3-4(b) shows the J-V curve with different silicidation temperatures. The leakage current of the NiSi sample is larger than the sample IA3-C slightly at low electric field. Let us to notice the sample IA3-800, the J-V curve is similar to that of others. It may be due to phosphorous reacted with nickel during silidation. At high temperature, this reaction may be more obvious. Therefore, phosphorous retarded nickel to diffuse into oxide. Fig.3-5 and Fig.3-6 had the same trends of Fig.3-4.
Fig.3-7 summarizes the oxide thickness measured by an optical analyzer, and the EOT versus RTA temperature plots for different conditions.
3.3.4 Characteristics of Gate-leakage Current Density
Fig.3-8 shows the weibull plot of leakage current densities at Vg = -1V for the 35Å-thick oxide treated by different silicidation temperatures. The leakage
characteristics are uniform. Then, the leakage current densities are increased with the temperature, and leakages of the NiSi sample are larger than sample IA3-C a little.
Thereafter, the oxide quality was still affected slightly by the high silicidation temperature.
3.3.5 Characteristics of Electric Breakdown Field
The characteristics of electric breakdown filed (EBD) is shown in Fig.3-9.
Approximately, the EBD of NiSi samples did not be degraded obviously even after the 800oC annealing.
3.3.6 Measurement of Effective Barrier Height
The electron barrier height (ΦB) of the n+-NiSi-gated MOS capacitor was extracted by F-N tunneling model as shown in Fig.3-10. In Fig.3-10(a), the ΦB(n+-Si→SiO2) of the sample IA7-C is 2.92eV. Then, when the silicidation temperature is increasing, the ΦB(n+-NiSi→SiO2) of the NiSi samples is becoming larger. It is because the change of the work function after annealing, and this result is identical as mentioned in section 3.3.2. Fig.3-10(b) has the same trend similar to Fig.3-10(a).
In summary, most of the electrical characteristics mentioned above are concluded in Table.3-3.
3.3.7 undoped-NiSi gate versus n
+-NiSi gate
Thereafter, we will discuss the difference between the undoped-NiSi gate and the n+-NiSi gate. Fig.3-11 is the C-V characteristics of 35Å-thick oxide. When the silicidation temperature changes, all of them, only the n+-NiSi samples has the apparent VFB shift. The VFB of undoped-NiSi gate samples are almost the same. The flat band voltage shifts among NiSi samples and the sample IA3-C are shown in Table.3-4.
Fig.3-12 is the J-V curve at different silicidation temperatures. Obviously, n+-NiSi gate have the better J-V characteristics than undoped-NiSi gate especially at the high temperature annealing. Fig.3-13 and Fig.3-14 are the weibull plots of the gate leakage current at V = -1V and the electric breakdown field of the oxide. We can see that the n+-NiSi gate has the better oxide reliability than the undoped-NiSi gate.
3.4 Summary
In this chapter, we investigated the NiSi-gated MOS capacitor based on in-situ dioped a-Si with different silicidation temperatures. The electric characteristics of the sample treated by 800oC RTA are not degraded. This is due to phosphorous in the a-Si which retarded nickel diffusion. Therefore, the oxide damage which is caused by the silicide process is reduced. It is shown that the n+-NiSi has the large process window.
In addition, we found that the flat band voltages increased with silicidation temperature. This phenomenon is as a result of the uniformity of the nickel silicide formation as shown in the TEM image. For this reason, the work function of the nickel silicide is different with temperature. In a word, the dopant in the gate can tune the work function of NiSi. For FDSOI device, it is a useful method to adjust the
threshold voltage without additional channel doping. Hence, the mobility will not be degraded by dopants.
3.5 References
[1] B.Cheng, B.Maiti, S.Samayedam, J.Grant, B.Taylor, P.Tobin, and J.Mogab,”Metal Gates for Advanced sub-80-nm SOI CMOS technology,” in IEEE Intl. SOI. Conf.
Proc., pp.91-92, 2001.
[2] Ming Oin, Vincent M. C. Poon and Stephen C. H. Ho,“Investigation of Polycrystalline Nickel Silicide Films as a Gate Material,” J. Electrochem. Soc., vol.148, no.5, pp.271-274, 2001.
[3] J. H. Sim, H. C. Wen, J. P. Lu, and D. L. Kwong,”Dual Work Function Metal Gates Using Full Nickel Silicidation of Doped Poly-Si,” IEEE Electron Device
Lett., vol.24, no.10, pp.631-633, October 2003.
[4] J. Kedzierski, E. Nowak, T. Kanarsky, Y. Zhang, D. Boyd, et al.,”Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation,” in IEDM
Tech. Dig., pp.247-250, 2002.
[5] J. Kedzierski, D. Boyd, P. Ronsheim, S. Zafar, J. Newbury, et al.,”Threshold voltage control in NiSi-gated MOSFETs through silicidation induced impurity segregation (SIIS),” in IEDM Tech. Dig., pp.13.3.1-13.3.4, 2003.
1. RCA cleaning
2. Growth of gate oxide (SiO2): 35, 50, 75Å 3. Deposition of silicon gate:
PH3 in-situ doped a-Si, 600Å
4. Dip diluted HF
5. Deposition of metal: Ni, 450Å
6. Silicidation : RTA 500, 600, 700, 800oC, 20s 7. Removing unreacted nickel:
H2SO4/H2O2 (3/1), 10 mins
8. Deposition of aluminum: Al, 5000Å (front) 9. Mask #1
10. Deposition of aluminum : Al, 5000Å (back)
Fig. 3-1 Process flow of the n+ NiSi-gated MOS capacitor formation.
p-Si <100>
p-Si <100>
p-Si <100>
p-Si <100>
Table 3-1
RTA(
oC)
T
OX(A) Control 500 600 700 800
35
IA3-C IA3-500 IA3-600 IA3-700 IA3-80050
IA5-C IA5-500 IA5-600 IA5-700 IA5-80075
IA7-C IA7-500 IA7-600 IA7-700 IA7-800Fig.3-2 Sheet resistance vs. RTA temperature. The plot shows the sheet resistance of the n+ a-Si/SiO2 structure with 500 ~800oC RTA.
RTA Trmperature (oC)
500 600 700 800
R s (ohm/square)
1 2 3 4 5
IA3
IA7 IA5
Fig.3-3(a) The TEM image of the n+ a-Si/SiO2 structurewith the oxide thickness
~ 38.1Å.
20nm Glue
Si sub.
n + a-Si
~ 619 Å
SiO 2 ~38.1Å
Fig.3-3(b) The TEM image of the n+ a-Si/SiO2(38.1Å)structure with RTA 500oC.
Fig.3-3(c) The TEM image of the n+ a-Si/SiO2(38.1Å)structure with RTA 800oC.
Si sub.
SiO 2
NiSi Glue
~ 756 Å
20nm
20nm NiSi
Si sub.
SiO 2 Glue
~750 Å
Fig.3-4(a) High frequency capacitance vs. gate voltage. The plot shows the C-V of the n+ a-Si/SiO2(35Å) structure with 500~800oC RTA.
Fig.3-4(b) Gate leakage current density vs. gate voltage. The plot shows the J-V of the n+ a-Si/SiO2(35Å) structure with 500~800oC RTA.
Fig.3-5(a) High frequency capacitance vs. gate voltage. The plot shows the C-V of the n+ a-Si/SiO2(50Å) structure with 500~800oC RTA.
Fig.3-5(b) Gate leakage current density vs. gate voltage. The plot shows the J-V of the n+ a-Si/SiO2(50Å) structure with 500~800oC RTA.
Fig.3-6(a) High frequency capacitance vs. gate voltage. The plot shows the C-V of the n+ a-Si/SiO2(75Å) structure with 500~800oC RTA.
Fig.3-6(b) Gate leakage current density vs. gate voltage. The plot shows the J-V of the n+ a-Si/SiO2(75Å) structure with 500~800oC RTA.
Table 3-2
Fig.3-7 Oxide thickness vs. RTA temperature. The plot shows the EOT of the n+ a-Si/SiO2 structure with 500~800oC RTA, and the physical oxide thickness measured by N&K analyzer.
N&K C 500 600 700 800
IA3 IA5 IA7
RTA Temperature (oC) T OX (A)
78.0 84.8
80.6 80.0 80.5 79.9
53.0 54.8 53.6 52.9 53.6 53.2
40.3 39.8
38.7 38.3 39.5 39.0
Fig.3-8.The Weibull plot shows the leakage current densities at Vg=-1V for the n+ a-Si/SiO2(35Å) structure with 500~800oC RTA.
Fig.3-9 The Weibull plot shows the electric breakdown field for the n+ a-Si/SiO2(35Å) structure with 500~800oC RTA.
-3
Fig.3-10(a) Electron barrier height vs. RTA temperature. The plot shows the electron barrier height of the n+ a-Si/SiO2(75Å) structure with 500~800oC RTA.
Fig.3-10(a) Electron barrier height vs. RTA temperature. The plot shows the electron barrier height of the n+ a-Si/SiO2(75Å) structure with 500~800oC RTA.