Transmission Electron Microscope Image

Fig.3-3(a) shows the TEM image of the 35Å-thick oxide with the n⁺ a-Si gate.

The thicknesses of the n⁺ a-Si and the oxide are about 619Å and 38.1Å. Fig.3-3(b) and Fig.3-3(c) show the TEM image of the 35Å-thick oxide with n⁺-NiSi gate treated by the 500^oC and 800^oC silicidation. In Fig.3-3(b), the thickness of NiSi is about 756Å and the NiSi film is not very uniform. There were few residues of silicon near the n⁺ a-Si/SiO2 interface which were not reacted with nickel. However, in Fig.3-3(c), the thickness of NiSi is about 750Å, and the NiSi film is more uniform.

3.3.3 C-V and J-V Characteristics of n

⁺

-NiSi-gated MOS capacitors

First of all, the C-V curve was measured by sweeping the gate voltage from the inversion region to the accumulation region (1V→-2V) and the J-V curve was measured in the accumulation region.Fig.3-4 to Fig.3-6 are C-V and J-V curves of n⁺-NiSi-gated MOS capacitors for different oxide thickness. In Fig.3-4(a), compared with the sample IA3-C, the capacitance of the NiSi sample increased with the silicidation temperature approximately. Because of reducing the gate sheet resistance (140Ω/□→2~4Ω/□), and therefore we acquired smaller EOT from the NiSi sample. In addition, while the silicidation temperature is raised, the C-V curve shifts to the right side, hence the flat-band (VFB) increased. It may be due to the change of the gate work function by reacting between nickel and phosphorous in n⁺ a-Si with different

temperatures. So that, n⁺ NiSi has different work function with n⁺ a-Si. There may be some reasons for this phenomenon: First, As shown in the TEM image (Fig.3-3 (b)), we can see that the reaction of nickel and n⁺ a-Si is not uniform at 500^oC. It means that there were few residues of silicon near the interface between n⁺ a-Si and the oxide did not transform to NiSi. As the temperature is increased, the formation of NiSi is more uniform. This may be one of reasons for VFB shift from 500 to 800^oC. Second, the bonding of Ni, P and Si may be different with the temperature. In other words, the composition of the NiSi film may be different with the temperature and hence the work function of the n⁺-NiSi film is changed with the temperature. The VFB shift is shown in Table.3-2. Something is worthy to notice, it is that the C-V curve is not distortion at 800^oC. This is different with the result of the undpoed-NiSi gate as mentioned in chapter 2. Fig.3-4(b) shows the J-V curve with different silicidation temperatures. The leakage current of the NiSi sample is larger than the sample IA3-C slightly at low electric field. Let us to notice the sample IA3-800, the J-V curve is similar to that of others. It may be due to phosphorous reacted with nickel during silidation. At high temperature, this reaction may be more obvious. Therefore, phosphorous retarded nickel to diffuse into oxide. Fig.3-5 and Fig.3-6 had the same trends of Fig.3-4.

Fig.3-7 summarizes the oxide thickness measured by an optical analyzer, and the EOT versus RTA temperature plots for different conditions.

3.3.4 Characteristics of Gate-leakage Current Density

Fig.3-8 shows the weibull plot of leakage current densities at Vg = -1V for the 35Å-thick oxide treated by different silicidation temperatures. The leakage

characteristics are uniform. Then, the leakage current densities are increased with the temperature, and leakages of the NiSi sample are larger than sample IA3-C a little.

Thereafter, the oxide quality was still affected slightly by the high silicidation temperature.

3.3.5 Characteristics of Electric Breakdown Field

The characteristics of electric breakdown filed (EBD) is shown in Fig.3-9.

Approximately, the EBD of NiSi samples did not be degraded obviously even after the 800^oC annealing.

3.3.6 Measurement of Effective Barrier Height

The electron barrier height (ΦB) of the n⁺-NiSi-gated MOS capacitor was extracted by F-N tunneling model as shown in Fig.3-10. In Fig.3-10(a), the ΦB(n⁺-Si→SiO2) of the sample IA7-C is 2.92eV. Then, when the silicidation temperature is increasing, the ΦB(n⁺-NiSi→SiO2) of the NiSi samples is becoming larger. It is because the change of the work function after annealing, and this result is identical as mentioned in section 3.3.2. Fig.3-10(b) has the same trend similar to Fig.3-10(a).

In summary, most of the electrical characteristics mentioned above are concluded in Table.3-3.

3.3.7 undoped-NiSi gate versus n

⁺

-NiSi gate

Thereafter, we will discuss the difference between the undoped-NiSi gate and the n⁺-NiSi gate. Fig.3-11 is the C-V characteristics of 35Å-thick oxide. When the silicidation temperature changes, all of them, only the n⁺-NiSi samples has the apparent VFB shift. The VFB of undoped-NiSi gate samples are almost the same. The flat band voltage shifts among NiSi samples and the sample IA3-C are shown in Table.3-4.

Fig.3-12 is the J-V curve at different silicidation temperatures. Obviously, n⁺-NiSi gate have the better J-V characteristics than undoped-NiSi gate especially at the high temperature annealing. Fig.3-13 and Fig.3-14 are the weibull plots of the gate leakage current at V = -1V and the electric breakdown field of the oxide. We can see that the n⁺-NiSi gate has the better oxide reliability than the undoped-NiSi gate.

3.4 Summary

In this chapter, we investigated the NiSi-gated MOS capacitor based on in-situ dioped a-Si with different silicidation temperatures. The electric characteristics of the sample treated by 800^oC RTA are not degraded. This is due to phosphorous in the a-Si which retarded nickel diffusion. Therefore, the oxide damage which is caused by the silicide process is reduced. It is shown that the n⁺-NiSi has the large process window.

In addition, we found that the flat band voltages increased with silicidation temperature. This phenomenon is as a result of the uniformity of the nickel silicide formation as shown in the TEM image. For this reason, the work function of the nickel silicide is different with temperature. In a word, the dopant in the gate can tune the work function of NiSi. For FDSOI device, it is a useful method to adjust the

threshold voltage without additional channel doping. Hence, the mobility will not be degraded by dopants.

3.5 References

[1] B.Cheng, B.Maiti, S.Samayedam, J.Grant, B.Taylor, P.Tobin, and J.Mogab,”Metal Gates for Advanced sub-80-nm SOI CMOS technology,” in IEEE Intl. SOI. Conf.

Proc., pp.91-92, 2001.

[2] Ming Oin, Vincent M. C. Poon and Stephen C. H. Ho,“Investigation of Polycrystalline Nickel Silicide Films as a Gate Material,” J. Electrochem. Soc., vol.148, no.5, pp.271-274, 2001.

[3] J. H. Sim, H. C. Wen, J. P. Lu, and D. L. Kwong,”Dual Work Function Metal Gates Using Full Nickel Silicidation of Doped Poly-Si,” IEEE Electron Device

Lett., vol.24, no.10, pp.631-633, October 2003.

[4] J. Kedzierski, E. Nowak, T. Kanarsky, Y. Zhang, D. Boyd, et al.,”Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation,” in IEDM

Tech. Dig., pp.247-250, 2002.

[5] J. Kedzierski, D. Boyd, P. Ronsheim, S. Zafar, J. Newbury, et al.,”Threshold voltage control in NiSi-gated MOSFETs through silicidation induced impurity segregation (SIIS),” in IEDM Tech. Dig., pp.13.3.1-13.3.4, 2003.

1. RCA cleaning

2. Growth of gate oxide (SiO2): 35, 50, 75Å 3. Deposition of silicon gate:

PH3 in-situ doped a-Si, 600Å

4. Dip diluted HF

5. Deposition of metal: Ni, 450Å

6. Silicidation : RTA 500, 600, 700, 800^oC, 20s 7. Removing unreacted nickel:

H2SO4/H2O2 (3/1), 10 mins

8. Deposition of aluminum: Al, 5000Å (front) 9. Mask #1

10. Deposition of aluminum : Al, 5000Å (back)

Fig. 3-1 Process flow of the n⁺ NiSi-gated MOS capacitor formation.

p-Si <100>

p-Si <100>

p-Si <100>

p-Si <100>

Table 3-1

RTA(

^o

C)

T

OX

(A) Control 500 600 700 800

35

IA3-C IA3-500 IA3-600 IA3-700 IA3-800

50

IA5-C IA5-500 IA5-600 IA5-700 IA5-800

75

IA7-C IA7-500 IA7-600 IA7-700 IA7-800

Fig.3-2 Sheet resistance vs. RTA temperature. The plot shows the sheet resistance of the n⁺ a-Si/SiO2 structure with 500 ~800^oC RTA.

RTA Trmperature (oC)

500 600 700 800

R s (ohm/square)

1 2 3 4 5

IA3

IA7 IA5

Fig.3-3(a) The TEM image of the n⁺ a-Si/SiO2 structurewith the oxide thickness

~ 38.1Å.

20nm Glue

Si sub.

n ⁺ a-Si

~ 619 Å

SiO ₂ ~38.1Å

Fig.3-3(b) The TEM image of the n⁺ a-Si/SiO2(38.1Å)structure with RTA 500^oC.

Fig.3-3(c) The TEM image of the n⁺ a-Si/SiO2(38.1Å)structure with RTA 800^oC.

Si sub.

SiO ₂

NiSi Glue

~ 756 Å

20nm

20nm NiSi

Si sub.

SiO ₂ Glue

~750 Å

Fig.3-4(a) High frequency capacitance vs. gate voltage. The plot shows the C-V of the n⁺ a-Si/SiO2(35Å) structure with 500~800^oC RTA.

Fig.3-4(b) Gate leakage current density vs. gate voltage. The plot shows the J-V of the n⁺ a-Si/SiO2(35Å) structure with 500~800^oC RTA.

Fig.3-5(a) High frequency capacitance vs. gate voltage. The plot shows the C-V of the n⁺ a-Si/SiO2(50Å) structure with 500~800^oC RTA.

Fig.3-5(b) Gate leakage current density vs. gate voltage. The plot shows the J-V of the n⁺ a-Si/SiO2(50Å) structure with 500~800^oC RTA.

Fig.3-6(a) High frequency capacitance vs. gate voltage. The plot shows the C-V of the n⁺ a-Si/SiO2(75Å) structure with 500~800^oC RTA.

Fig.3-6(b) Gate leakage current density vs. gate voltage. The plot shows the J-V of the n⁺ a-Si/SiO2(75Å) structure with 500~800^oC RTA.

Table 3-2

Fig.3-7 Oxide thickness vs. RTA temperature. The plot shows the EOT of the n⁺ a-Si/SiO2 structure with 500~800^oC RTA, and the physical oxide thickness measured by N&K analyzer.

N&K C 500 600 700 800

IA3 IA5 IA7

RTA Temperature (^oC) T OX (A)

78.0 84.8

80.6 80.0 80.5 79.9

53.0 54.8 53.6 52.9 53.6 53.2

40.3 39.8

38.7 38.3 39.5 39.0

Fig.3-8.The Weibull plot shows the leakage current densities at Vg=-1V for the n⁺ a-Si/SiO2(35Å) structure with 500~800^oC RTA.

Fig.3-9 The Weibull plot shows the electric breakdown field for the n⁺ a-Si/SiO2(35Å) structure with 500~800^oC RTA.

-3

Fig.3-10(a) Electron barrier height vs. RTA temperature. The plot shows the electron barrier height of the n⁺ a-Si/SiO2(75Å) structure with 500~800^oC RTA.

Fig.3-10(b) Electron barrier height vs. RTA temperature. The plot shows the electron barrier height of the n⁺ a-Si/SiO2(50Å) structure with 500~800^oC RTA.

0

control 500 600 700 800

substrat injection

RTA Temperature (^oC)

0

control 500 600 700 800

substrate injection gate injection

e- Barrier Height (eV)

RTA Temperature (^oC)

2.93 3.08 3.15 3.25 3.30

1.94

Table.3-3 (a)

IA3 IA3-C IA3-500 IA3-600 IA3-700 IA3-800

C (pF)

67.3 68.1 70.1 70.7 68.7

IA5 IA5-C IA5-500 IA5-600 IA5-700 IA5-800

C (pF)

49.5 50.6 51.2 50.6 51.0

(gate injection)

2.93 3.08 3.15 3.25 3.30

Φ

B

(eV)

(sub. injection)

1.94 2.27 2.33 2.44 2.57

Table.3-3 (c)

IA7 IA7-C IA7-500 IA7-600 IA7-700 IA7-800

C (pF)

31.9 33.6 33.9 33.7 33.9

(gate injection)

2.92 3.15 3.29 3.37 3.35

Φ

B

(sub. injection)

2.47 2.54 2.75 2.79 2.79

Fig.3-11(a) High frequency capacitance vs. gate voltage. The plot shows the C-V of the n⁺ a-Si/SiO2, undoped poly-Si/SiO2, and undoped a-Si/SiO2 structure with 500^oC RTA.

Fig.3-11(b) High frequency capacitance vs. gate voltage. The plot shows the C-V of the n⁺ a-Si/SiO2, undoped poly-Si/SiO2, and undoped a-Si/SiO2 structure with

Fig.3-11(c) High frequency capacitance vs. gate voltage. The plot shows the C-V of the n⁺ a-Si/SiO2, undoped poly-Si/SiO2, and undoped a-Si/SiO2 structure with 700^oC RTA.

Table.3-4

∆V

FB

500

^o

C 600

^o

C 700

^o

C

IA3

0.225 V 0.3834 V 0.5334 V

SP3

0.642 V 0.67 V 0.68 V

SA3

0.665 V 0.665 V 0.675 V

ΔVFB

= V

FB

(NiSi) – V

FB

(n

⁺

a-Si)

0 0.2 0.4 0.6 0.8 1.0

-2 -1.5 -1 -0.5 0 0.5 1

IA3-C V

FB = -0.925 V IA3-700 V

FB = -0.3916 V SP3-700 V

FB = -0.245 V SA3-700 V

FB = -0.250 V

Gate Voltage (V)

A = 7.85 x 10^-5cm² f = 100k Hz

C H/C OX

Fig.3-12(a) Gate leakage current density vs. gate voltage. The plot shows the J-V of the n⁺ a-Si/SiO2, undoped poly-Si/SiO2, and undoped a-Si/SiO2 structure with 500^oC RTA.

Fig.3-12(b) Gate leakage current density vs. gate voltage. The plot shows the J-V of the n⁺ a-Si/SiO2, undoped poly-Si/SiO2, and undoped a-Si/SiO2 structure with

Fig.3-12(c) Gate leakage current density vs. gate voltage. The plot shows the J-V of the n⁺ a-Si/SiO2, undoped poly-Si/SiO2, and undoped a-Si/SiO2 structure with 700^oC RTA.

Fig.3-12(d) Gate leakage current density vs. gate voltage. The plot shows the J-V of the n⁺ a-Si/SiO2, undoped poly-Si/SiO2, and undoped a-Si/SiO2 structure with

Fig.3-13(a) The Weibull plot shows the leakage current densities at Vg=-1V for the n⁺ a-Si/SiO2, undoped poly-Si/SiO2, and undoped a-Si/SiO2 structure with 500^oC RTA.

.

Fig.3-13(b) The Weibull plot shows the leakage current densities at Vg=-1V for the n⁺ a-Si/SiO2, undoped poly-Si/SiO2, and undoped a-Si/SiO2 structure with 600^oC RTA.

-3

Fig.3-13(c) The Weibull plot shows the leakage current densities at Vg=-1V for the n⁺ a-Si/SiO2, undoped poly-Si/SiO2, and undoped a-Si/SiO2 structure with 700^oC RTA.

Fig.3-13(d) The Weibull plot shows the leakage current densities at Vg=-1V for the n⁺ a-Si/SiO2, undoped poly-Si/SiO2, and undoped a-Si/SiO2 structure with 800^oC RTA.

-3

Fig.3-14(a) The Weibull plot shows the electric breakdown field for the n⁺ a-Si/SiO2, undoped poly-Si/SiO2, and undoped a-Si/SiO2 structure with 500^oC RTA.

Fig.3-14(b) The Weibull plot shows the electric breakdown field for the n⁺ a-Si/SiO2, undoped poly-Si/SiO2, and undoped a-Si/SiO2 structure with 600^oC RTA.

-3

Fig.3-14(c) The Weibull plot shows the electric breakdown field for the n⁺ a-Si/SiO2, undoped poly-Si/SiO2, and undoped a-Si/SiO2 structure with 700^oC RTA.

-3 -2 -1 0 1 2 3 4

10 12 14 16 18 20

IA3-C IA3-700 SP3-700 SA3-700

ln(-ln(1-p))

EBD (-MV/cm)

Chapter 4

Characteristics of NiSi gate structure based on stacked a-Si/poly-Si and poly-Si/a-Si

4.1 Introduction

In chapter 1, we observed that the characteristics of the undoped NiSi-gated MOS capacitors treated by 800^oC silicidation were degraded. This is due to that nickel diffused into oxide and damaged it. Hence, in order to improve this issue of the nickel diffusion, we proposed different gate structure to form FUSI NiSi gate. In the past, there are several structures of the poly-Si had been proposed to suppress the boron penetration [1]~[4].The interface of the stacked silicon structures can suppress the boron and fluorine diffusion. In addition, the grain size and the relative thickness of underlying layer silicon affect the thermal reliability of the NiSi film intensely [5].Then, the stacked structure can inhibit nickel penetration to the gate oxide, too.

Therefore, the gate oxide reliability is improved.

In this chapter, we will use the n⁺ a-Si (top)/undoped poly-Si (AP) and the undoped poly-Si (top)/n⁺ a-Si (PA) stacked structure to form NiSi-gated MOS capacitors. Then, we will investigate the characteristics of the capacitor and the gate

oxide reliability compared with samples as mentioned in chapter 3.

4.2 Experimental

The stacked-NiSi-gated MOS capacitor on the <100> p-type silicon substrate was fabricated. All 6-inch p-type silicon wafers were first cleaned by standard RCA clean. Then, Gate oxides (SiO2) of 35 50 75Å-thick were grown in diluted dry O2

(O2/N2 = 1/7) at 800^oC by ASM A-400 Vertical Furnace system immediately. After that, two types of the silicon gate were deposited in the same system:

(1) 300Å n⁺ amorphous silicon (top)/300 Å undoped polysilicon (AP) stacked structure.

(2) 300Å undoped poly silicon (top)/300 Å n⁺ amorphous silicon (PA) stacked structure.

Dopant activation was accomplished by Heatpulse 610i rapid thermal processing system for 30 seconds in N2 ambient at 900^oC. Prior to the nickel deposition, all wafers were dipped in a diluted HF solution (HF/H2O =1/100) to remove the native oxide on the silicon surface and then loaded into the metal deposition chamber of Metal PVD system. A 450Å-thick nickel film was deposited on the stacked silicon surface at a pressure of 5x10^-9 torr. In order to achieve the silicidation procedure, all samples were treated by rapid thermal annealed for 20 seconds in an N2 ambient at 500~800^oC in the heatpulse 610 rapid thermal processing system. Thereafter, the unreacted nickel was removed by wet etching (H2SO4/H2O2= 3/1, 10mins) and a 5000Å-thick aluminum film was deposited on the silicide surface by sputter system.

The gate electrode of the capacitor was patterned and defined by wet etching (H3PO4:

HNO3:CH3COOH:H2O = 50:2:10:9 for aluminum etching; HNO3:NH4F:H2O=64:3:33 for silicide etching). Finally, a 5000Å-thick aluminum film was also deposited on the backside of the wafer to form the ohmic contact. The gate area is 7.85x10^-5cm². The cross-sectional view of the fabrication processes was shown in Fig. 4-1.Table 4-1 shows serial numbers of all samples.

The physical thicknesses of oxide and stacked structures were measured by N&K analyzer. The Sheet resistance (Rs) of nickel silicide was obtained by four-point-probe analyzer. Electrical characteristics of all MOS capacitors were measured by using Hewlett-Packard 4156B (HP-4156B) semiconductor parameter analyzer. HP4284 LCR meter was used to extract the CV performance at high frequency (100K Hz).

4.3 Results and Discussion

4.3.1 Sheet Resistance Versus RTA Temperature

Fig.4-2(a) (n⁺ a-Si/poly-Si, AP) and Fig.4-2(b) (poly-Si/n⁺ a-Si, PA) show the sheet resistance as the function of temperature. Sheet resistances of two structures are stable and have no obvious variation with temperature. Then, they distribute about at 2~3 Ω/□ and most of them are smaller than the IA samples (RS=2~5Ω/□). However, two structures are not different apparently at the sheet resistance.

4.3.2 Transmission Electron Microscope Image

Fig.4-3 shows the TEM image of the a-Si/poly-Si stacked structure with the 35Å-thick oxide. Fig.4-3(a) is the Ni/a-Si/poly-Si/SiO2 stacked structure with the

thickness about 447/282/353/39Å and there is an apparent interface between a-Si and poly-Si. In Fig.4-3(b), we can see that most of the silicon was reacted with nickel to form NiSi and there were few residues of silicon near the poly-Si/SiO2 interface.

However, after the 800^oC silicidation, the silicon film was consumed by nickel totally as shown in Fig.4-3(c), and the NiSi film is more uniform than that treated by 500^oC annealing.

Then, for the PA stacked structure, Fig.4-4(a) is the Ni/poly-Si/a-Si/SiO2 stacked structure with the thickness about 450/250/350/41.6Å. As shown in Fig.4-4(b), the NiSi film is also not uniform after 500^oC annealing. On the other hand, the sample treated by 800^oC annealing, there is a uniform NiSi film on the oxide surface.

Therefore, based on the same silicidation time, the higher annealing temperature, the nickel silicide film is more uniform.

4.3.3 C-V and J-V Characteristics of stacked MOS capacitors

Fig.4-5~ Fig.4-10 show the (a) C-V characteristics measured by sweeping the gate voltage from the inversion region to the accumulation region, (b) J-V characteristics measured in the accumulation region for the AP and PA stacked structure with different oxide thicknesses. As mentioned in chapter 3, for both of the AP and PA stacked structure, capacitances with 500^oC annealing are lower than these with 600~800^oC. Therefore, the nickel/a-Si/poly-Si (nickel/poly-Si/a-Si) film treated by silicidation for 20s at 500^oC is not enough to form nickel silicide completely. As the temperature is raised to 600^oC or higher, the gate on the oxide is the n⁺-NiSi gate.

The relation between EOT and RTA temperature is shown in Fig.4-11. Furthermore, as result of the PH3 doped, the phenomenon of the flat band voltage shift which

increases with the silicidation temperature is similar to the result of chapter 3.

On the other hand, Fig.4-5(b) and Fig.4-8(b) show the J-V characteristics of the 35Å-thick oxide. When temperature is up to 800^oC (AP3-800, PA3-800), the leakage current density goes up, and the breakdown voltage drops down. Moreover, the degradation of the AP stacked structure is severer than PA stacked structure.

Compared with the IA sample, the amounts of dopants in the both two stacked structures are less. Hence, It increases the opportunity of oxide degradation during silicidation process. On the contrary, for the thicker oxide, the J-V curve is not destroyed even at 800^oC. Therefore, the thicker oxide has larger process window than thinner oxide.

Fig.4-11(a) and (b) summarize the oxide thickness measured by an optical analyzer, and the EOT versus RTA-temperature plots for different conditions.

4.3.4 Characteristics of Gate-leakage Current Density

Fig.4-12 shows the weibull plot of the gate leakage current density at V = -1 V for the 35Å-thick oxide with different annealing temperatures. From Fig.4-12, the distribution of the sample with temperature less than 800^oC is uniform and has no apparent difference. Then, leakage current densities of the sample AP3-800 and PA3-800 increase obviously and this tend is compatible with Fig.4-5(b) and Fig.4-8(b) mentioned above.

4.3.5 Characteristics of Electric Breakdown Field

Fig.4-13 shows weibull plot of the electric breakdown field for the 35Å-thick

oxide with different annealing temperatures. The electric breakdown field of the sample with temperature less than 800^oC is about 13.5~15.0MV/cm. However, electric breakdown fields of the sample AP3-800 and PA3-800 drop down, especially for AP3-800. Hence, for the thinner oxide, it surely degrades the oxide by the 800^oC silicidation.

4.3.6 Measurement of Effective Barrier Height

Electron barrier heights (ΦB) of AP and PA stacked MOS capacitor were extracted by F-N tunneling model as shown in Fig.4-14 and Fig.4-15.In Fig.4-14(a), first, ΦB(n⁺-NiSi→SiO2) of the sample by 500^oC annealing is 2.96eV, and it is close to the ΦB(n⁺-Si→SiO2) of the sample IA7-C (2.92eV).Then, this result from that there is the silicon film on the oxide not the NiSi film as mentioned in Fig.4-3(a).

Furthermore, ΦB(n⁺-NiSi→SiO2) increases with temperature, and this trend coincides with the chapter 3. Similarly, the barrier height of the PA sample as shown in Fig.4-15 has the same result.

In summary, most of the electrical characteristics mentioned above are concluded in Table.4-2 and Table 4-3.

4.3.7 Comparison of AP, PA and IA

Thereafter, we will discuss the difference among of the sample AP,PA and IA.

Fig.4-16 shows the C-V characteristics of the AP, PA and IA samples, we can see that the flat band voltages of three structures shift with the temperature. Fig.4-17 shows the J-V characteristics treated by 800^oC annealing. Obviously, the sample IA3-800 has

the best J-V characteristics than AP3-800 and PA3-800. On the other hand, Fig.4-18 and Fig.4-19 are the weibull plot of the gate leakage current density at V = -1V and the electric breakdown field of the oxide at 800^oC. We can see that the IA sample has

the best J-V characteristics than AP3-800 and PA3-800. On the other hand, Fig.4-18 and Fig.4-19 are the weibull plot of the gate leakage current density at V = -1V and the electric breakdown field of the oxide at 800^oC. We can see that the IA sample has

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