Chapter 1 Introduction
1.2 Organization
Chapter 2 begins with the overview of a subthreshold MOSFET analytical model which is suitable for circuit design. Then an effective method to use this simple model is introduced and demonstrated on a deep-submicron technology. Finally, we discuss about the matching properties of MOS transistors.
Chapter 3 introduces the MOS PTAT reference prototypes. These circuits are thoroughly analyzed in this chapter. In addition, low-voltage PTAT generators which are applicable in deep-submicron technology are also investigated. The effects of leakage current are discussed and a compensation technique is then proposed.
In Chapter 4, the implementation issues of experimental PTAT references are described in detail. The test setup and measurement environment are also presented.
Experimental results for the PTAT references fabricated in a standard 0.25-µm COMS technology are reported and discussed in the end of this chapter.
The conclusions of this work are given in Chapter 5.
2
SUBTHRESHOLD OPERATION OF MOS TRANSISTORS
This chapter begins with the derivation of a subthreshold MOSFET model dedicated to the design and analysis of low-voltage, low-current analog circuits.
Following the brief review of both analytical and accurate models, an effective approach to link these two models is demonstrated on a deep-submicron technology.
The mismatch models for MOS transistors and matching properties in the weak inversion region are then discussed in the end of this chapter.
2.1 Introduction
It is well know that when the gate-to-source voltage of a MOS transistor is reduced below the threshold voltage defined by the usual strong inversion characteristics, the channel current decreases approximately exponentially. In this case, the transistor is in weak inversion and is said to be operating in the subthreshold region.
At the first, subthreshold MOSFET conduction attracted attention as the leakage current and should be eliminated if possible [14]. However, as the circuit density continuously increases in modern VLSI design, the weakly inverted MOSFET becomes a very attractive device for low-power low-voltage designs. There are many advantages for operating MOSFETs in subthreshold or weak inversion region: i) extremely low power consumption due to the inherently low currents in that region, ii) low voltage swing, and iii) the exponential natural of the I-V characteristic.
Before we can utilize the subthreshold MOS transistors in very low power
designs, we have to be familiar with the weakly inverted MOSFET in the aspects of circuit design. For this reason, we first investigate the analytical MOS transistor model in weak inversion region in the following section.
2.2 Analytical Model [15]
Subthreshold operation of MOS transistors has long been utilized to implement very low power, low voltage analog circuits. The performance of these analog circuits strongly depends on how the characteristics of the transistors are exploited and mastered. Designers therefore need a model of subthreshold MOS transistor that is suited not only to final numerical circuit simulation but also to the task of exploring new circuits. In this section, an analytical MOS transistor model in weak inversion region which is based on previous publications and suitable for circuit design is introduced.
The cross section of a typical enhancement- mode n-channel MOS transistor is depicted in Fig. 2.1. In order to exploit the intrinsic symmetry of the device in the model, the source voltage VS, the gate voltage VG, and the drain voltage VD are all referred to the local substrate. All the symbols adopted in the following paragraphs are reported for clarity in Table 2.1. The Fermi potential φf is defined as the quasi-Fermi potential of the majority carriers and the channel potential Vch, which depends on the position along the channel, as the difference between the quasi-Fermi potential of the carriers forming the channel φn and the quasi-Fermi potential of the majority carriers φp.Since the current densityof majoritycarriers(holes inan n-channeltransistor) is
Figure 2.1 Cross section of a typical enhancement- mode n-channel MOS transistor.
assumed to be negligible, the quasi-Fermi potential of majority carriers φp is equal to the Fermi potential φf and thus the channel potential is simply equal to the difference φn-φf.
Table 2.1 Definitions used in the model.
Symbols Description
Q Electron charge
µn Mobility of electrons in the channel Ut=(k·T)/q Thermal voltage
ni Intrinsic carrier concentration εs , εox Dielectric constant of Si and SiO2
Nsub Substrate doping concentration VFB Flat-band voltage
φf=Ut·ln(Nsub / ni) Substrate Fermi potential φs=φ(y=0) Surface potential
Vch=φn-φp=φn-φf Channel potential
C′ox Oxide capacitance per unit area Q′inv Mobile inversion charge per unit area
The different charges appearing across the MOS structure are represented in Fig.
2.2. The gate charge Q′G is balanced by the fixed charged Q′ox trapped at the Si-SiO2
interface, the inversion charge Q′inv, and the depletion charge Q′B. The derivation of the characteristics of MOS transistors operating in subthreshold region begins by investigating the inversion charge in strong inversion. By integrating Poisson’s
Figure 2.2 Charges appearing across the MOS structure.
equation, the mobile inversion charge density Q′inv can be expressed as a function of
A relation between gate voltage and φs is obtained by applying Gauss’ law:
ox where ? is the body effect coefficient defined as
ox
In strong inversion, the surface potential φs can be approximated by a constant φ0 + Vch where φ0 = 2φf + several Ut. Replacing φs by φ0 + Vch in Equation 2.2 leads to an expression of the inversion charge per unit area valid in strong inversion:
Q'inv=−C'ox⋅
[
VG−VtB]
(2.4) where VtB is the gate threshold voltage referred to the local substrate and defined asch ch
FB
tB V V V
V ≡ +φ0+ +γ⋅ φ0+ (2.5) When the channel is at equilibrium (Vch = 0), the gate threshold voltage becomes
0
The inversion charge Q′inv becomes zero for a particular value of the channel potential Vp defined as the pinch-off voltage. The relation between Vp and the gate voltage is obtained from Equation 2.4 to Equation 2.6:
[
0 0]
Each value of the gate voltage corresponds to a different value of the pinch-off voltage. By inverting Equation 2.7, the pinch-off voltage can be expressed in terms of the gate voltage:
The slope factor n is defined as the derivative of the gate voltage with respect to the pinch-off voltage and is given by
p p
Since Vp depends on VG, the slope factor can also be expressed directly as a function of VG:
This expression is useful for evaluating n at a certain operating point.
For the values of ? and φf used in practice, the pinch-off voltage is almost the linear function of the gate voltage and can be approximated by
n V
Vp ≈VG − t0 (2.11)
where n is evaluated from Equation 2.10. Fig. 2.3 shows the pinch-off voltage calculated using Equation 2.8 and Equation 2.11 respectively. Process parameter values used for calculation are extracted from TSMC 0.25-µm CMOS process. From Fig. 2.3 we can observe that Equation 2.11 gives a good approximation for Vp when the gate voltage is below 1.1 V.
The inversion charge Q′inv does not vanish abruptly when Vch reaches Vp, but decays smoothly as the channel leaves strong inversion. For Vch somewhat larger than Vp, the channel is in weak inversion and the inversion charge is much less than the charge in the depletion region. By neglecting the Q′inv term in Equation 2.2 and introducing the definition of Vt0, the relation between the surface potential and the gate voltage is obtained:
( 0)
(
0)
0+ φ −φ +γ⋅ φ − φ
= t S S
G V
V (2.12)
The pinch-off voltage, which is originally defined in strong inversion, can also be used in weak inversion to approximatethe surface potential.Comparing Equation 2.12
Figure 2.3 Pinch-off voltage versus gate voltage.
to Equation 2.7 gives
p S =φ0+V
φ (2.13)
The surface potential can finally be expressed as
In weak inversion, the surface potential is smaller than 2φf + Vch. The exponential term appearing in the general expression of the inversion charge given by Equation 2.1 is thus much smaller than φs／Ut. The square root term in Equation 2.1 can then
Thus the expression of the inversion charge is simplified to
t
t
Assuming that the mobility µn is constant along the y axis, a general expression for the drain current including both the diffusion and the drift mechanisms can be expressed as
dx The drain current is then obtained by integrating Equation 2.19 from the source, where Vch = VS to the drain, where Vch = VD:
where it has been assumed that the mobility is also independent of x. The above equation is valid in all regions of operation since no assumption has been made on the mode of operation of the transistor. The drain current in weak inversion is simply obtained by integrating Equation 2.17:
Substituting Equation 2.11 into Equation 2.21 gives
The slope factor n can be evaluated from the gate voltage by using Equation 2.10.
Figure 2.4 plots the drain current versus the drain-source voltage for three values of VG - Vt0, with β = 160 µA／V2, Kw = 3, and n = 1.5. Notice that the drain current is almost constant when VDS > 4Ut, because the last term in Equation 2.22 is negligible in this case. Therefore, unlike in strong inversion, the minimum drain-source voltage required to force the transistor to operate as a current source in weak inversion is independent of the overdrive. Table 2.2 summarizes all the expressions for the drain current in weak inversion. The current in reverse saturation is not shown, but can be obtained by simply replacing VS by VD in the expression valid in the forward saturation region.
Figure 2.4 Drain current versus drain-source voltage in weak inversion.
Table 2.2 Drain current in weak inversion.
Mode Conditions Drain Current
Equation 2.22 describes the general behavior of drain current in weak inversion.
This expression, which is a good compromise between accuracy and simplicity, supports creative synthesis and is suitable for circuit design. Considerations for using subthreshold MOSFETs in circuit design will be discussed in the later sections.
2.3 Efficient Design [16]
In very low power applications, the use of MOS transistors operating in the weak inversion region is very attractive. However, it is not easy to manipulate the weakly inverted MOSFETs in today’s CMOS technology. The derivation of the model
introduced in the previous section did not take higher order effects such as non-uniform doping and short-channel effects into account. On the other hand, the very accurate BSIM model is so complicated that hand calculation for an initial design is very difficult. In a design stage, we need analytical model to create a novel circuit. At the same time, we also rely on simulation results to confirm whether the circuit works. Hence, link both models together is essential in circuit design. In this section, an effective method is introduced to obtain an accurate model for initial hand calculations by extracting key parameters from simulation data.
According to the analytical model introduced in the previous section, the drain current in weak inversion saturation is
t
By examining Equation 2.23, it may be seen that that the equation is suitable for hand calculation in design stages. The parameter I0, which is a weak function of biases and thus can be regarded as a constant, comprises all process parameters of the drain current equation. The only two process parameters in Equation 2.23 are I0 and n. The remaining terms are design parameters W／L, VG, and VS set by designers.
Traditionally, parameters I0 and n are evaluated using the process parameters provided by the foundry. Although I0 and n are calculated from process parameters, the corresponding drain current ID do not match well to the ID resulting from simulation due to the inaccuracy of the simple model. Instead of evaluating the two parameters directly, we extract these values from simulation. The method to accurately obtain I0
and n will be presented later.
The Berkeley Short-Channel IGFET Model (BSIM) is an accurate short-channel MOS transistor model which added numerous empirical parameters to simplify physically meaningful equations. The complete model includes very accurate expressions for DC, capacitance characteristics, and extrinsic components. For channel lengths as low as 0.25 µm, BSIM3 provides reasonable accuracy for subthreshold operation. However, BSIM3 requires approximately 180 parameters which are not directly listed in the SPICE parameter file and thus is not suitable for hand calculation.
To match the analytical ID equation in Equation 2.23 to the accurate ID curves from SPICE simulation, parameter extraction for I0 and n is addressed here.
Performing DC analysis on SPICE for the circuit in Fig. 2.5(a) with a given value of W／L, we obtain the ln(ID)-VG characteristic as plotted in Fig 2.5(b). From Fig. 2.5(b) we can measure the slope of the ln(ID)-VG curve. The slope can be also determined from Equation 2.23 by differentiating the drain current:
t G
D
U n V
I slope ln
= ⋅
∂
=∂ 1
(2.25)
(a) (b)
Figure 2.5 (a) Tested circuit. (b) The ln(ID)-VG characteristic.
From the measured slope, the slope factor n can be calculated using Equation 2.25 and should have a value between 1.3 and 2. With W／L, VG, VS, ID, and n, the parameter I0
can be evaluated as follows:
t S t G
U V U n
V
D e e
L W
I0 = I ⋅ − ⋅ ⋅ (2.26)
The value of I0 is obtained by averaging the values of all I0 obtained from every simulated drain current in weak inversion. Finally, with the extracted parameters I0
and n, the ID equation in Equation 2.23 can be used as the accurate and simplified model for the weakly inverted MOSFETs.
Experiments have been done by making the comparisons of ID plots from the simplified equation and those from HSPICE with three different gate width to length
ratios of 400 µm／4 µm, 40 µm／4 µm, and 4 µm／4 µm in a 0.25-µm CMOS process. I0 and n were extracted from the ln(ID)-VG curve, where W／L was set to 400 µm／4 µm. Then we used the same I0 and n but changed W／L to 40 µm／4 µm and 4 µm／4 µm to make additional comparisons. Fig. 2.6 shows the results of the comparisons of ID from the equation and HSPICE with I0 = 532.16f and n = 1.48.
From Fig. 2.6(a) and (b), it is seen that the ID plots from the equation match well to those from HSPICE. The upper-end curves start splitting from each other since the MOSFET is changing from weak inversion to strong inversion. In Fig. 2.6(c), the ID
curves from the equation and HSPICE do not match well because the I0 and n were extracted when W／L was 400 µm／4 µm but in (c) they were used again with W／L
= 4 µm／4 µm. The gate width to length ratio has changed by a factor of 100. There is no problem between the plots in (a) and (b) even though the W／L ratio has changed by a factor of 10. Therefore, the changes of the W／L ratio should be less than a factor of 100 when we use the simplified equation.
(a) W／L = 400 µm／4 µm
(b) W／L = 40 µm／4 µm
(c) W／L = 4 µm／4 µm
Figure 2.6 Drain current versus gate voltage with different W／L ratios for L = 4 µm.
The same comparisons have also been done for short-channel devices with W／L ratios of 36 µm／0.36 µm, 3.6 µm／0.36 µm, and 0.36 µm／0.36 µm. With I0 = 874.53f and n = 1.53, extracted from the 36 µm／0.36 µm transistor, the ID curves are plotted in Fig. 2.7. From Fig. 2.7 we can observe that the simplified model fails to describe the drain current in weak inversion for short-channel devices if the change of the W／L ratio is larger than a factor of 10.
To further investigate the simple model, the drain current plots for different bias conditions have been compared. Fig. 2.8 shows the simulated and calculated ID curves
(a) W／L = 36 µm／0.36 µm
(b) W／L = 3.6 µm／0.36 µm
(c) W／L = 0.36 µm／0.36 µm
Figure 2.7 Drain current versus gate voltage with different W／L ratios for L = 0.36 µm.
versus gate voltage at VS = 50 mV for two different W／L ratios of 400 µm／4 µm and 36 µm／0.36 µm. In Fig. 2.8, deviations are observed between the ID curve calculated using previously extracted parameters and the simulated ID curve. By re-extracting I0 and n at VS = 50 mV, the curves from the equation and simulation become matched.
The technique described in this section maps the BSIM model to an analytical model. This gets accuracy from the accurate model and puts it into a simpler model.
The experimental results have confirmed that the technique is useful for low-power low-voltage designs using subthreshold MOSFETs.
(a) W／L = 400 µm／4 µm
(b) W／L = 36 µm／0.36 µm
Figure 2.8 Drain current versus gate voltage at VS = 50 mV with different W／L ratios.
2.4 Mismatch
Mismatch is the differential performance of two or more devices on a single integrated circuit (IC). It is widely recognized that mismatch is key to precision analog IC design. As stated above, subthreshold operation is attractive for low-power design. The exponential dependence of drain current on gate-to-source voltage provides a very useful property for many applications. However, one of the major disadvantages associated with weakly inverted MOSFETs is the current mismatch between identical drawn devices. Owing to exponential dependencies on the process
variations, devices in subthreshold usually exhibit larger mismatch in drain current as compared with that in above-threshold [14]. The effect of MOS transistor mismatch is therefore prominent for using subthreshold MOSFETs in circuit design. In the following paragraphs, the mismatch models for MOS transistors and matching properties in the weak inversion region are discussed.
MOSFET current mirrors and differential pairs, which are widely used in analog integrated circuits, are usually investigated for transistor mismatch characterization [17]-[24]. Assuming that the drain current is a function of the overdrive VG - Vt0
rather than a function of VG and Vt0 separately, the mismatch of drain currents in two identical transistors which have the same gate voltage can be modeled as
0 t D m D
D V
I g I
I ∆
β β
∆
∆ = − ⋅ (2.27)
where ∆Vt0 and ∆β／β are the threshold voltage mismatch and the current factor mismatch respectively. The current mismatch is maximum in weak inversion, for which gm／ID is maximum, and only comes down to ∆β／β when the transistors operate deeply in strong inversion.
The threshold voltage mismatch ∆Vt0 and the current factor mismatch ∆β／β are usually used as the two parameters to characterize the matching properties of MOS transistors. Pelgrom et al. [17] introduced a powerful spatial Fourier transform technique to build a general frame for mismatch parameters. Neglecting the separation-dependant mismatch effects, the standard deviations of the threshold voltage mismatch and the current factor mismatch are inversely proportional to the square root of the transistor area:
( )
( )
L W
A L W Vt AVt
= ⋅
= ⋅
β
β β
∆ σ
∆
σ 0 0
(2.28)
where AVt0 and Aβ are the size proportionality constants for s (∆Vt0) and s(∆β)／β respectively. Experimental results showed that Equation 2.28 could predict the threshold voltage mismatch and the current factor mismatch. The two proportionality constants, AVt0 and Aβ, could be derived from the measured mismatch in threshold voltage and current factor. It was also observed that the threshold voltage mismatch decreased with thinner gate oxides, whereas the current factor mismatch remained almost constant.
With respect to the mismatch in subthreshold MOSFETs, Forti and Wright [18]
measured the current mismatch in MOS differential pairs operated in the weak inversion region. They measured a total of about 1400 NMOS and PMOS transistors produced in four different processes with different oxide thickness and feature sizes.
Using the scaled current I = ID／(W/L), a fairly good uniformly response was found over a wide variety of sizes and VGS values. The measured weak inversion current mismatch was essentially independent of current density as expected and it was observed to be proportional to the inverse square root of device area except for the big transistors and for the PMOS transistors. Furthermore, the substrate bias was judged to be responsible for significant degradation in match.
Chen et al. [19], [20] measured and analyzed the current mismatch of weakly inverted MOS transistors with substrate-to-source junction forward and reverse biased.
The MOS transistor with substrate-to-source junction slightly forward biased acts as a high gain gated lateral bipolar transistor in low level injection. The measured mismatch data exhibited that i) subthreshold circuits should be carefully designed for suppression of mismatch arising from back- gate reverse bias, and ii) the current match in weak inversion can be substantially improved by the gated lateral action, especially for small size transistors. An analytical statistical model with back- gate forward bias and device size both as input parameters for optimizing the match can be found in [20].
The mismatch model of MOS transistors derived in [17] has been found in good agreement with experimental results for a device size above 2 µm. However, it was observed that the threshold voltage mismatch linear dependence on the inverse of the square root of the device area no longer holds for transistors with L = 0.7 µm [21].
The mismatch model of MOS transistors derived in [17] has been found in good agreement with experimental results for a device size above 2 µm. However, it was observed that the threshold voltage mismatch linear dependence on the inverse of the square root of the device area no longer holds for transistors with L = 0.7 µm [21].