Chapter 3 CMOS PTAT References
3.4 Leakage Currents and Proposed Compensation Technique
There are at least three essential requirements for the PTAT reference in an on-chip temperature sensor: i) the circuit must exhibit the best compatibility against process scaling, ii) the supply voltage should be compatible with the complete system-on-chip, and iii) the PTAT signal must be linear over a wide range of temperature. The low-voltage PTAT generators described in the previous section fulfill the first two requirements for a complete temperature sensor. However, these circuits suffer from the no nlinearity problem if the temperature is higher than 100°C. This nonlinear behavior mainly results from the junction leakage currents in MOS transistors at high temperature. In this section, we first discuss the effect of leakage currents and then a compensation technique is proposed to enhance the linearity of high temperature behavior.
In the CMOS structure, the source/drain implants and the substrate (or the n-well) form the pn junction diodes and may conduct leakage currents in the devices. Fig.
3.16 illustrates the leakage currents through the junction diodes in MOS transistors.
These leaky diodes are generally reverse-biased since the bulk of n-channel MOSFETs is tied to the ground and that of p-channel MOSFETs to the most positive supply voltage. The leakage current which is the reverse-bias saturation current of the diode is associated with the doing concentrations and is strongly dependent on temperature.
Figure 3.16 The leaky junction diodes in MOS transistors.
At room temperature, these leaky diodes conduct almost no current and do not influence the operation of transistors. However, the leakage current increases sharply in high temperature and degrades the performance of analog circuits. Fig. 3.17 shows the leakage current versus temperature in a 0.25-µm CMOS process. Leakage currents
in both n-channel and p-channel MOSFETs with different channel widths and lengths are plotted in this figure. The leakage current is found slightly dependent on the channel length and proportional to the gate wid th since the current in a diode is proportional to its area. Furthermore, n-channel MOSFETs have larger leakage current s due to the lower channel doping concentration.
Figure 3.17 Leakage current versus temperature.
Due to the extremely low current in weak inversion, the leakage current becomes comparable to the current level in a MOS PTAT generator. Fig. 3.18 shows the VPTAT curves of the circuit in Fig. 3.15(a) with different values of ID1. For smaller bias current level, the influence of leakage cur rents on the PTAT voltage is more severe.
Figure 3.18 VPTAT curves of the circuit in Fig. 3.15(a) with different ID1.
Consider the MOS PTAT reference shown in Fig. 3.15(a). As described before, the PTAT voltage VPTAT is determined by the product of transistor size ratio S1／S2 and current ratio ID2／ID1. Taking the leakage currents into account in high temperature, the expression of VPTAT becomes
( ) ( ) ( ) M8 respectively. Since the leakage currents in M3-M8 are balanced,
( ) ( )
The last term in the above equation is the non-PTAT term. If IDB1(T)／P·I1(T) << 1, this nonlinear term can be rewritten as
( ) ( ) ( )
Fig 3.19 shows the nonlinearity of PTAT voltage in the circuit shown in Fig. 3.15(a).
Figure 3.19 Nonlinearity of the PTAT voltage in the circuit show in Fig. 3.15(a).
From Fig. 3.19 we can observe that the nonlinear behavior in high temperature primarily results from the leakage currents and it can be described by Equation 3.53.
The nonlinearity behavior is a crucial effect to implement a complete thermal mana gement system within a digital circuit since such circuitry requires more effort and cost for after process calibration. As a result, solutions for improving the linearity of high temperature behavior are necessary. Fig. 3.20 depicts the schematic of all-MOS PTAT reference with leakage compensation. Compensation transistors Mc1
and Mc2 are attached to the drain terminals of M1 and M2 respectively. The effects of leakage currents in M3-M8 are eliminated since the leakage currents are proportional to device sizes and thus are all balanced in these transistors. At room temperature, the two compensation transistors Mc1 and Mc2 do not interfere with normal operation of the circuit since the gate of Mc1 is connected to VDD and that of Mc2 to the ground. In high temperature, additional leakage currents come from Mc1 and Mc2 will compensate the leakage currents in M1 and M2 as illustrated in Fig. 3.20.
Figure 3.20 All-MOS PTAT reference with leakage compensation.
Fig. 3.21 presents the simulated temperature characteristics of VPTAT for all- MOS and compensated PTAT references. The linearity at high temperature is improved significantly in the proposed compensated PTAT reference. From this figure we can observe that the PTAT circuit with compensation may extend the temperature range at least 30°C.
The MOS PTAT reference with leakage current compensation can exhibit the best compatibility against supply scaling in deep-submicron technology. The power consumption is also made minimum due to the inherently low currents in subthreshold
MOSFETs. Furthermore, the PTAT signal exhibits high linearity over a wide range of temperature. Hence, the proposed compensation technique allows the integration of PTAT references in deep-submicron technology for complete temperature sensors.
Figure 3.21 Simulated VPTAT versus temperature for all-MOS and compensated PTAT references.
4
IMPLEMENTATION OF CMOS PTAT REFERENCES
Experimental implementations of the MOS PTAT references including leakage-compensated circuit have been fabricated in TSMC 0.25-µm double-poly five-metal CMOS process. Design issues as well as layout considerations of the MOS PTAT references are thoroughly discussed in this chapter. Following the description of test setup, the experimental results are presented and discussed. The characteristics of experimental PTAT references are summarized in the end of this chapter.
4.1 Realization
In order to demonstrate the applicability of the proposed leakage compensation technique, so as to implement the competitive temperature sensors in deep-submicron technology, three MOS PTAT references are designed and implemented in a 0.25-µm CMOS technology. In this section, implementation issues of the experimental PTAT references are described in detail.
The first implemented circuit is the resistor-based MOS PTAT reference which has been discussed in Chapter 3. The schematic is redrawn in Fig. 4.1. The circuit is designed to exhibit an output voltage of about 60 mV at room temperature. Device sizes of M1 and M2 which operate in weak inversion are set to equal for matching consideration. As a result, the current ratio ID2／ID1 = 10 is chosen here to generate the required VPTAT. It is important for M1 and M2 to operate in weak inversion region.
Therefore, the current gain factors of the two transistors have to be larger than the value corresponding to the limit of weak inversio n region [12]:
Figure 4.1 The R-based MOS PTAT reference.
The minimum value of S1,2 ensuring subthreshold operation can thus be calculated from this relation. With µn·C′ox = 150 µA／V2 in this 0.25-µm technology, S1,2 > 100 is required for the drain currents of few microamperes. In the circuit, the gate voltage of M1-M2 pair is design to be well below the threshold voltage and the current ID1 is chosen as 300 nA. Using Equation 2.23 along with the extracted parameters, I0 and n, a value of about 140 for S1,2 can be obtained. In addition, a resistor R ≈ 200 kΩ is required for this bias current.
An important aspect of the performance of the PTAT reference is its accuracy. As discussed in Chapter 3, the variance of the relative variation in the PTAT voltage can be expressed as
( ) ( )
( )
( ) ( )Applying the Pelgrom model described in Equation 2.28 to the mismatch parameters, the above equation can be rewritten as
( )
Values of these proportionality constants in a 0.35-µm technology are: Aβn = 1.9
%·µm, Aβp = 2.25 %·µm, and AVt0 = 9 mV·µm [31]. In general, the accuracy of the
PTAT voltage is dominated by the threshold voltage mismatch. For relative deviations (∆VPTAT／VPTAT) ≤ 5%, which corresponds to σ(∆VPTAT／VPTAT) ≤ 2.5% when a 2σ law is used, the required device area for the M1-M2 pair (W·L)1,2 = 16 µm2 is obtained.
To minimize the current mismatch in current mirrors, transistors M3-M8 are designed to operate in deep strong inversion. Device sizes of M3 and M6 are designed identical to those of M4 and M7 respectively for matching consideration. Furthermore, the drain currents in M7 and M8 are also designed equal to reduce the power consumption. Designing the overdrive Vov = 150 mV for all transistors in strong inversion, the device sizes of M3-M8 can be roughly obtained from square law:
2 8 3 8
3
2
ov ' ox
D
V C S I
⋅
⋅
= ⋅ −
− µ (4.4) The values of µ·C′ox for NMOS and PMOS in this 0.25-µm technology are about 150 µA／V2 and 40 µA／V2 respectively.
The other two experimental circuits are all-MOS and compensated all- MOS PTAT references. The condensed scheme of these two circuits is shown in Fig. 4.2. In the all-MOS implementation, the PTAT core, M1-M2, and the ORA, M3-M8, are all designed identical to those in the R-based PTAT reference. The transistor sizes of M9-M11 are derived from Equation 3.49 and from power considerations: M = 1 and N
= 1.5. In the compensated version, an n-channel MOSFET is used for matching consideration.
Figure 4.2 All-MOS and compensated all-MOS PTAT references.
According to the discussions above, the transistor aspect ratios are summarized in Table 4.1 for the three experimental circuits.
Table 4.1 MOS PTAT references component values.
R-based All-MOS Compensated
Component Value Component Value Component Value
M1, M2 48／0.36 M1, M2 48／0.36 M1, M2 48／0.36
M3, M4 0.6／2.8 M3, M4 0.6／2.8 M3, M4 0.6／2.8
M5 6.4／0.6 M5 6.4／0.6 M5 6.4／0.6
M6-M8 0.64／0.6 M6-M8, M11 0.64／0.6 M6-M8, M11 0.64／0.6
R 245.6 kΩ M9 0.6／2 M9 0.6／2
M10 0.6／2.8 M10 0.6／2.82
Mc 432／0.36
Figs. 4.3-4.6 present the simulation results of these three experimental circuits.
Fig. 4.3 shows the PTAT vo ltage versus supply voltage at room temperature. In this figure, curves for all-MOS and compensated all-MOS PTAT references are the same.
Figure 4.3 Simulated VPTAT versus VDD at room temperature.
Fig. 4.4 presents the temperature characteristics of these PTAT references. The R-based and all- MOS versions have similar temperature behavior and they both encounter nonlinearity problem in high temperature.
Figure 4.4 Simulated VPTAT versus temperature.
The VPTAT histogram plots for R-based and all-MOS PTAT references are shown in Fig. 4.5 and Fig. 4.6 respectively. The result of the compensated circuit is quite similar to that of the all-MOS version and is not shown for simplicity.
Figure 4.5 VPTAT histogram at room temperature from 1000´ Monte Carlo runs for the R-based PTAT reference.
Figure 4.6 VPTAT histogram at room temperature from 1000´ Monte Carlo runs for the all-MOS PTAT reference.
Since the PTAT voltage is sensitive to the device mismatch, a good layout should group the transistors in the following manner:
Group N1: M1, M2, and Mc (weak inversion) Group N2: M3 and M4 (strong inversion) Group N3: M9 and M10 (strong inversion) Group P: M5-M8, M11 (strong inversion)
In each group, the transistors are in the same orientation and have the minimum separation allowed in design rule. The most important devices in the PTAT references are the subthreshold MOSFETs M1 and M2. They are decomposed into identical unit transistors of exactly the same geometry and these unit transistors are interleaved and have a common centroid.
The experimental chip is fabricated in TSMC 0.25-µm single-poly five-metal CMOS technology. The resistor in the R-based circuit is implemented by the p+ poly resistor for resistivity and temperature coefficient s considerations. Fig. 4.7 shows the microphotographs of the R-based and the compensated all-MOS circuits. The right side of the compensated circuit is the all-MOS PTAT reference. Surface areas for R-based, all-MOS, and compensated circuits are about 10,000 µm2, 900 µm2, and 2000 µm2 respectively.
(a)
(b)
Figure 4.7 Microphotographs of (a) R-based and (b) compensated all-MOS PTAT references.
4.2 Measurement Setup
Fig. 4.8 depicts the measurement setup used to access the performance of the experimental PTAT references. A PCB which combines a voltage regulator and the DUT is designed to measure the temperature characteristics of the chip in a thermal bath. The chip temperature is monitored by a thermocouple tied closed to the die and measured by the thermo meter. The output PTAT voltage of the DUT is fed to the Agilent 54622A oscilloscope.
The supply voltage is generated by LM317 adjustable regulator and a 9 V battery as shown in Fig. 4.9. We use the 9 Vbatteryforbetterpower supply noise.Moreover,
Figure 4.8 Measurement setup.
the voltage regulator output is connected to the parallel combination capacitors to provide decoupling of both low frequency noise with large amplitude and high frequency noise with small amplitude.
Figure 4.9 The voltage regulator with bypass filter.
Figs. 4.10 and 4.11 show the photographs of the PCB and the measurement environment respectively. The experimental results will be presented in the following section.
Figure 4.10 Photograph of the PCB.
Figure 4.11 The measurement environment.
4.3 Experimental Results
The output voltages of the experimental PTAT references are measured by an oscilloscope. Table 4.2 lists the measured PTAT voltages for each circuit at room temperature. A fairly large spread in voltage values of about 15% is observed. This is likely because the mismatches in subthreshold MOSFETs and small transistors are larger than the predicted value s from Pelgrom model.
Fig. 4.12 shows the PTAT voltage versus temperature for all-MOS and compensated PTAT references. The dashed lines are the regressions of measured data from 35°C to 95°C for each circuit. The VPTAT curve of the all-MOS version deviates from the straight line when temperature is above 95°C. The R-squares of all-MOS and compensated circuits are 0.994 and 0.868 respectively. The temperature behavior of the R-based PTAT generator is similar to the all-MOS version and is shown in Fig.
4.13. Its R-square is only 0.79.
Table 4.2 Measured PTAT voltage at room temperature.
Avg. Max. Min. Variation
R-based 70.01 74.65 61.12 12.64%
All-MOS 63.67 71.38 59.14 12.11%
VPTAT (mV)
Compensated 43.77 50.22 39.43 14.74%
Figure 4.12 Measured PTAT voltage versus temperature for all-MOS (crosses) and compensated (circles) PTAT references.
Figure 4.13 Measured PTAT voltage versus temperature for R-based (triangles) and compensated (circles) PTAT references.
Fig. 4.14 shows the spread of VPTAT for the compensated PTAT reference. The offset comes from the process variation and is dominated by the threshold voltage mismatch ∆Vt0 as described in section 4.1. Since ∆Vt0 is insensitive to temperature, the offset of PTAT voltages is almost a constant in the whole temperature range.
Therefore, the offset error can be easily calibrated by other circuits in the thermal management system.
Figure 4.14 The spread of measured PTAT voltages for the compensated PTAT reference.
4.4 Summary
This chapter described in detail the implementation of MOS PTAT references in a 0.25-µm CMOS process and presented the experimental results. The experimental results show that the PTAT reference without compensation has severe nonlinearity problem in high temperature. The linearity is improved significantly in the proposed compensated circuit and the operating temperature range of this circuit can be extended to at least 155°C. A large spread of VPTAT due to process variation is also observed. This is not a relevant problem for our application since the offset can be easily calibrated by digital circuits.
5
CONCLUSIONS
The utilization of subthreshold MOSFETs has been shown to be an attractive means of implementing low-voltage low-power PTAT references. This thesis has demonstrated the feasibility of using such approach in deep-submicron technology.
This work has focused on three major topics: the subthreshold operation of MOS transistors, the analysis and design of the MOS PTAT references, and a leakage compensation technique.
We introduced the analytical subthreshold MOSFET model and the effective approach to link both analytical and accurate models. The simple equation describes the simulated drain current in weak inversion well and the technique, which maps the accurate BSIM to a simple conventional model, makes designs using the weakly inverted MOSFET more efficient.
Analysis of the MOS PTAT references based on the analytical model identified the topology as suitable for low- voltage and low-power applications. Experimental PTAT references based on the analysis presented in this work were designed and integrated in TSMC 0.25-µm 1P5M standard CMOS technology. Experimental results confirmed the feasibility of the PTAT circuits in deep-submicron technology.
Precautions have to be taken against the large spread of the PTAT voltage.
A pure CMOS PTAT reference, which applied a compensation technique to enhance the linearity of high temperature behavior, has also been implemented in this 0.25-µm technology. Testing results showed that the linear range of the voltage output has been expanded to at least 155°C, which implies that the temperature sensor requires calibration only of its offset. Thus, the effort for after process calibration is minimized.
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