Chapter 2 Subthreshold Operation of MOS Transistors
2.4 Mismatch
Mismatch is the differential performance of two or more devices on a single integrated circuit (IC). It is widely recognized that mismatch is key to precision analog IC design. As stated above, subthreshold operation is attractive for low-power design. The exponential dependence of drain current on gate-to-source voltage provides a very useful property for many applications. However, one of the major disadvantages associated with weakly inverted MOSFETs is the current mismatch between identical drawn devices. Owing to exponential dependencies on the process
variations, devices in subthreshold usually exhibit larger mismatch in drain current as compared with that in above-threshold [14]. The effect of MOS transistor mismatch is therefore prominent for using subthreshold MOSFETs in circuit design. In the following paragraphs, the mismatch models for MOS transistors and matching properties in the weak inversion region are discussed.
MOSFET current mirrors and differential pairs, which are widely used in analog integrated circuits, are usually investigated for transistor mismatch characterization [17]-[24]. Assuming that the drain current is a function of the overdrive VG - Vt0
rather than a function of VG and Vt0 separately, the mismatch of drain currents in two identical transistors which have the same gate voltage can be modeled as
0 t D m D
D V
I g I
I ∆
β β
∆
∆ = − ⋅ (2.27)
where ∆Vt0 and ∆β／β are the threshold voltage mismatch and the current factor mismatch respectively. The current mismatch is maximum in weak inversion, for which gm／ID is maximum, and only comes down to ∆β／β when the transistors operate deeply in strong inversion.
The threshold voltage mismatch ∆Vt0 and the current factor mismatch ∆β／β are usually used as the two parameters to characterize the matching properties of MOS transistors. Pelgrom et al. [17] introduced a powerful spatial Fourier transform technique to build a general frame for mismatch parameters. Neglecting the separation-dependant mismatch effects, the standard deviations of the threshold voltage mismatch and the current factor mismatch are inversely proportional to the square root of the transistor area:
( )
( )
L W
A L W Vt AVt
= ⋅
= ⋅
β
β β
∆ σ
∆
σ 0 0
(2.28)
where AVt0 and Aβ are the size proportionality constants for s (∆Vt0) and s(∆β)／β respectively. Experimental results showed that Equation 2.28 could predict the threshold voltage mismatch and the current factor mismatch. The two proportionality constants, AVt0 and Aβ, could be derived from the measured mismatch in threshold voltage and current factor. It was also observed that the threshold voltage mismatch decreased with thinner gate oxides, whereas the current factor mismatch remained almost constant.
With respect to the mismatch in subthreshold MOSFETs, Forti and Wright [18]
measured the current mismatch in MOS differential pairs operated in the weak inversion region. They measured a total of about 1400 NMOS and PMOS transistors produced in four different processes with different oxide thickness and feature sizes.
Using the scaled current I = ID／(W/L), a fairly good uniformly response was found over a wide variety of sizes and VGS values. The measured weak inversion current mismatch was essentially independent of current density as expected and it was observed to be proportional to the inverse square root of device area except for the big transistors and for the PMOS transistors. Furthermore, the substrate bias was judged to be responsible for significant degradation in match.
Chen et al. [19], [20] measured and analyzed the current mismatch of weakly inverted MOS transistors with substrate-to-source junction forward and reverse biased.
The MOS transistor with substrate-to-source junction slightly forward biased acts as a high gain gated lateral bipolar transistor in low level injection. The measured mismatch data exhibited that i) subthreshold circuits should be carefully designed for suppression of mismatch arising from back- gate reverse bias, and ii) the current match in weak inversion can be substantially improved by the gated lateral action, especially for small size transistors. An analytical statistical model with back- gate forward bias and device size both as input parameters for optimizing the match can be found in [20].
The mismatch model of MOS transistors derived in [17] has been found in good agreement with experimental results for a device size above 2 µm. However, it was observed that the threshold voltage mismatch linear dependence on the inverse of the square root of the device area no longer holds for transistors with L = 0.7 µm [21].
Due to the strong dependence of the threshold voltage and of the effective mobility on channel length for short-channel transistors, the mismatch model described in Equation 2.28 is not applicable for submicron devices. The mismatch model proposed by Croon et al. [22], [23] is based on parametric extensions of [17] and is validated on a 0.18-µm technology. The mismatch model contains four parameters: one parameter (∆Vt0) to describe the mismatch in the threshold voltage, and three (∆β0, ∆ζsr, and
∆ζsat) to describe the mismatch in the current factor. The parameter ∆β0 is the low field current factor for long transistors while the other two parameters, ∆ζsr and ∆ζsat, are used to model the higher order effects such as surface roughness scattering, series resistance, and velocity saturation. These mismatch parameters are modeled by the complete Pelgrom model [17]:
( ) W L A L W
A L W
P AP, P,L P,W + ⋅ + ⋅
= 2⋅0 2 2 22
2 ∆
σ (2.29)
The first term of the right-hand side models the variance for a large device, while the second and third terms describe the variation in short and narrow channel effects. The correlation factors between mismatch parameters can also be modeled by
W A L
AP , AP ,L P ,W
P ,
P1 2 = 1 20+ 1 2 + 1 2
ρ (2.30)
The first term on the right-hand side gives the correlation for large transistors, while the second and third terms account for short and narrow channel effects. The detailed mismatch model in drain current and the procedure for extracting the mismatch parameters can be found in [23].
CHAPTER
3
CMOS PTAT REFERENCES
This chapter deals with the analysis and design of MOS PTAT references. We describe the operation principles of MOS PTAT prototypes and analyze these circuits in detail. In addition to this, low- voltage PTAT generators which are applicable in deep-submicron technology have been also investigated. In the end of this chapter, the effects of leakage current at high temperature are discussed and a compensation technique to enhance the linearity is proposed.
3.1 Introduction
The PTAT circuits generate an output voltage proportional to absolute temperature and have been widely used in temperature- insensitive voltage and current references.
In a thermal management system, the PTAT reference is also the best candidate for a fully- integrated temperature sensor. Traditionally, PTAT references are implemented using parasitic substrate bipolar transistors available in all standard CMOS processes.
A typical PTAT generator using parasitic BJTs is shown in Fig. 3.1. When both transistors are at the same temperature, the difference between emitter-to-base voltages, ∆VEB, of two diode- like bipolar transistors can be written as
⋅
=
−
=
1 2 2 1 2
1
S S t
EB EB
EB I
I I ln I U V V
∆V (3.1)
where Ut is the thermal voltage and IS1 as well as IS2 are the saturation current for Q1 and Q2 respectively. If the two transistors are matched, ∆VEB is directly proportional to absolute temperature, i.e., it is a PTAT signal.
Various on-chip PTAT references have been extensively implemented using
Figure 3.1 Typical PTAT generator.
parasitic BJTs because of the ease of design. In some CMOS process, however, obtaining reliable BJTs is very costly and the desirable performance from these parasitic devices is hard to expect. Also, the power consumption of the BJT based references is relatively high and an alternative approach is preferred, especially in low power applications.
Several PTAT references using the subthreshold MOS transistors have been studied and applied in low-power low-voltage designs [12], [13], [25]-[30]. These circuits take advantage of MOS devices operating in the weak inversion region in two respects: i) the exponential I-V characteristic is used to generate a PTAT voltage, and ii) the power consumption is made minimum due to the inherent low currents in that region. The properties of MOS PTAT references make them an excellent temperature sensor in a thermal management system. To implement the competitive temperature sensors in deep-submicron technology, we first analyze the prototype circuits of MOS PTAT references in the following section.
3.2 MOS PTAT Generator Prototypes
Several kinds of MOS PTAT generators have been reported for use in a wide range of applications. All of these PTAT circuits can be categorized into three types. In this section, the prototype circuits of MOS PTAT generators will be introduced and analyzed.
3.2.1 Prototype I: Diode Connection
The first MOS PTAT prototype [25] is shown in Fig. 3.2. If transistors M1 and M2 operate in weak inversion, the drain currents of M1 and M2 are given by
Figure 3.2 MOS PTAT generator prototype I: diode connection. If M1 and M2 are matched, the PTAT voltage can be obtained from the difference in V1 and V2: temperature characteristic of the prototype, we have simulated the circuit shown in Fig. 3.3(a) in a 0.25-µm CMOS process. In this circuit, p-channel MOSFETs M3 and M4 act as a current mirror and the minimum supply voltage for which M3 and M4 operate in the strong inversion saturation region is
p where VGS,w represents the gate-source voltage of the transistor in weak inversion and VSG,p is the source-gate voltage of PMOS transistors. In the simulation, the device sizes S1 and S2 areset to equal while the current ratio ID1／ID2 is 10. The PTAT voltage
(a) (b)
Figure 3.3 Simulation of MOS PTAT prototype I. (a) Simulation circuit. (b) PTAT voltage versus temperature.
versus temperature plot is shown in Fig. 3.3(b).
Equation 3.5 is based on the assumption that transistors M1 and M2 are perfectly matched. In reality, however, nominally identical devices suffer from a finite mismatch due to uncertainties in each step of the manufacturing process. To take into account the threshold voltage and the current factor mismatch in the circuit shown in Fig. 3.3(a), we now define average and mismatch quantities as follows:
2
These relations can be inverted to give the original parameters in terms of the average and the mismatch parameters. For example,
Applying this set of equations for the various parameters in Equation 3.3 and solving for V1- V2, we obtain
Substituting these approximations into Equation 3.11 gives
0
Equation 3.13 indicates that the accuracy of the PTAT signal is strongly dependent on the mismatch in transistors since the value of VPTAT is usually smaller than 100 mV at room temperature.
3.2.2 Prototype II: Cascode Configuration
The second MOS PTAT prototype [26], [27] is shown in Fig. 3.4. In the elementary cell, the two transistors M1 and M2 both operate in the subthreshold region. Because M2 is diode connected, it operates in the forward saturation mode and forces M1 to operate in the conduc tion mode. Since M2 operates in the saturation mode,
t Since M1 operates in the conduction mode,
(a)
(b)
Figure 3.4 MOS PTAT generator prototype II: cascode configuration. (a) Elementary cell. (b) Stack of elementary cells.
If M1 and M2 are matched, the PTAT voltage can be derived from Equation 3.14 and Equation 3.15:
practically obtainable from an elementary cell are limited to about 100 mV. Higher values may be obtained by stacking a certain number of cells as shown in Fig. 3.4(b).
In this circuit, the voltage VPTAT is composed of three sections. The mode of operation is still the same, except that the current supplied to each cell goes through the bottom transistor of all subsequent cells. For instance, the PTAT voltage formed by section
M1-M2 is given by
Fig. 3.5 shows the simulated circuit and the PTAT voltage plot of this prototype.
In Fig. 3.5(a), the transistor M3 which operate in strong inversion serves as a current source and the minimum supply voltage is given by
p straight line at high temperature due to the effect of leakage currents.
(a) (b)
Figure 3.5 Simulation of MOS PTAT prototype II. (a) Simulation circuit. (b) PTAT voltage versus temperature.
We now consider the effect of transistor mismatch in the circuit shown in Fig.
3.5(a). Applying the expressions in Equation 3.7 and Equation 3.8 and neglecting high-order terms, we obtain
If S2 >> S1, the PTAT voltage can be rewritten as the current mismatch in the PMOS current mirror. Since the voltage variations of the three cells are not statistically correlated, the standard deviation of the voltage variation is therefore multiplied by 3 and the spread of VPTAT is reduced.
3.2.3 Prototype III: Common Gate Connection
Fig. 3.6 shows the third MOS PTAT prototype [12], [13], [27]-[30]. If transistors M1 and M2 are in weak inversion and their drain-source voltages are both much larger then Ut, the drain currents can be expressed as
t
Assuming that M1 and M2 are matched, the PTAT signal can be obtained and is given by
Figure 3.6 MOS PTAT generator prototype III: common gate connection.
We also examine the temperature characteristic of this prototype circuit through simulation. The simulated circuit shown in Fig. 3.7(a) is derived from a circuit used with bipolar transistors and has been utilized in several designs. The p-channel MOSFETs M3 and M4 act as a current mirror and the minimum supply voltage is given by
p , SG w , DS PTAT min ,
DD V V V
V = + + (3.23)
where VDS,w is the drain-source voltage of the transistor in weak inversion. In the simulation, the device size ratios S1 and S2 are set to equal while the current ratio ID2／ID1 is 10. Fig. 3.7(b) shows the PTAT voltage VPTAT versus temperature. At high temperature, deviations from the ideal PTAT behavior due to leakage currents are also observed.
(a) (b)
Figure 3.7 Simulation of MOS PTAT prototype III. (a) Simulation circuit. (b) PTAT voltage versus temperature.
Consider the circuit shown in Fig. 3.7(a). The variation of VPTAT may come from threshold voltage and current factor mismatch in M1-M2 pair and the current mismatch in the current mirror formed by M3 and M4. Applying the mismatch parameters defined by Equation 3.7 to Equation 3.9 in the derivation of VPTAT, we obtain
n
Note that the mismatch terms in Equation 3.24 are almost the same as those in Equation 3.20. In this circuit, the mismatch of resistor does not affect the PTAT voltage as long as M1 and M2 both operate in weak inversion.
3.2.4 Summary
The temperature and mismatch characteristics of MOS PTAT prototypes have been addressed in the previous paragraphs. These results are summarized in Table 3.1. The
∆βp／βp terms are omitted in expressions of ∆VPTAT since the current factor mismatch in strong inversion is negligible compared to that in weak inversion.
The PTAT signal of prototype I is proportional to nUt while the other two prototype circuits generate output voltages proportional to Ut. The value of the slope factor n ranges usually from 1.3 to 2 and a larger VPTAT can be obtained in prototype I.
In a standard CMOS process, however, the slope factor is not a reliable parameter and its value depends slightly on the bias conditions. Furthermore, the higher supply voltage requirement due to diode-connected transistors makes prototype I incompatible with low-voltage operation.
Table 3.1 Characteristics of MOS PTAT prototypes.
Prototype VPTAT ∆VPTAT VDD,min
The characteristics of prototypes II and III are very similar. Prototype II provides a floating PTAT voltage and the elementary cells can be stacked to produce PTAT voltages of the order of a few hundreds of millivolts. As an additional advantage, the mismatch between transistors is averaged out in a stacked PTAT generator. The spread of VPTAT can be reduced at the expense of a larger supply voltage.
3.3 Low-Voltage PTAT References in Deep-Submicron Technology
Low- voltage implementations for PTAT references are necessary for the complete system-on-chip such as thermal management system. Such PTAT references must exhibit the best compatibility in deep-submicron technology. In the following paragraphs, we will investigate the low-voltage MOS PTAT references in detail.
3.3.1 Power-Supply Rejection Ratio (PSRR)
The MOS PTAT prototype circuit shown in Fig. 3.7(a) seems suitable for low-voltage designs. However, the power-supply rejection ratio (PSRR) of this circuit deteriorates sharply in deep-submicron technology. Fig. 3.8 shows the low- frequency small-signal model of the MOS PTAT generator shown in Fig. 3.7(a). From Fig. 3.8, the small-signal gain vptat／vdd can be derived to
( )
Figure 3.8 Low- frequency small-signal model of the MOS PTAT generator shown in Fig. 3.7(a).
( )
Since M1 and M2 are in weak inversion and M3 and M4 act as a current mirror,
g P
Substituting Equation 3.27 into Equation 3.26, we have
1
In deep-submicron technology, the ratio gm 1／go1 is typically smaller than 200 and the resulting static PSRR+ is usually smaller than 50 dB. Fig 3.9 shows the simulated VPTAT and static PSRR+ versus supply voltage at room temperature for the PTAT generator shown in Fig. 3.7(a). For PSRR(DC)+ > 40 dB, the minimum supply voltage is 1.5 V.
Figure 3.9 Simulated VPTAT and static PSRR+ versus supply voltage at room temperature for the PTAT generator shown in Fig. 3.7(a).
A low-voltage MOS PTAT reference based on the same prototype [13] is depicted in Fig. 3.10. The simple current mirror in Fig. 3.7(a) is replaced by the operational transresistance amplifier (ORA) composed of M3-M8. The role of the ORA is to ensure the current ratio ID2／ID1, as well as an almost equal voltage biasing for both drain voltages of M1 and M2. Thanks to the latter, the channel length modulation effects in M1-M2 can be minimized.
Figure 3.10 The low-voltage MOS PTAT reference.
The small-signal DC gain vptat／vdd of this circuit can be derived from the low- frequency small-signal model shown in Fig. 3.11. Assume go << gm for all transistors, then
( )
Figure 3.11 Low- frequency small- signal model of the MOS PTAT reference shown in Fig. 3.10.
Ideally, gm 1,2 and go1,2 are all proportional to their drain currents since M1 and M2 are both in weak inversion. As a result, gm 2·go1 = gm1·go2 and PSRR+ approximates to infinity for low frequencies. The finite static PSRR+ may arise from the higher order
effects in gm and go in reality. Fig. 3.12 shows the simulated VPTAT and PSRR(DC)+ versus supply voltage at room temperature for the low-voltage PTAT reference. From Fig. 3.12 we can observe that the static PSRR+ is improved significantly. For PSRR(DC)+ > 40 dB, the minimum supply voltage is 1.1 V and the PSRR+ is greater than 70 dB for VDD = 1.5 V.
Figure 3.12 Simulated VPTAT and static PSRR+ versus supply voltage at room temperature for the low-voltage PTAT reference shown in Fig. 3.10.
3.3.2 Accuracy
The use of ORA in the low-voltage PTAT reference may lead to a larger spread of VPTAT due to the extra current mirrors. Defining average and mismatch quantities, we have
8 2
Applying this set of equations in the derivation of VPTAT, we obtain
n
In this circuit, the VPTAT variation due to current factor mismatch in strong inversion is approximately three times as large as that in conventional MOS PTAT circuits.
3.3.3 Circuit Compensation
The low-voltage MOS PTAT reference has two feedback paths and may require proper compensation. Consider the open- loop circuit shown in Fig. 3.13. The first feedback path consists of a common-source stage with source degeneration and a current mirror. Therefore, the small-signal current i′1 can be expressed as
( )
The second path consists of a common-source stage and two current mirrors and the small-signal current i′2 is given by
3
Figure 3.13 Open- loop circuit of the low- voltage MOS PTAT reference.
The small-signal gain vo／vi is thus
The dominant pole is located at the output node and is given by (r ||r ) C
Therefore, the gain-bandwidth product can be expressed as
( )
Values of gm 1 and C must be designed so that the gain-bandwidth product is well below the other poles arising from parasitic capacitances. Fig. 3.14 shows the simulated frequency response of the open- loop circuit for three values of gm 1／C. The unit-gain frequency is found proportional to gm 1／C as described in Equation 3.42.
Figure 3.14 Frequency response of the open-loop circuit shown in Fig. 3.13.
3.3.4 All-MOS Implementations
The presence of the resistor may be a drawback in a low-voltage MOS PTAT reference. For an extremely low bias current, a high value resistance is required which
The presence of the resistor may be a drawback in a low-voltage MOS PTAT reference. For an extremely low bias current, a high value resistance is required which