Chapter 3 CMOS PTAT References
3.2 MOS PTAT Generator Prototypes
3.2.2 Prototype II: Cascode Configuration
Applying this set of equations for the various parameters in Equation 3.3 and solving for V1- V2, we obtain
Substituting these approximations into Equation 3.11 gives
0
Equation 3.13 indicates that the accuracy of the PTAT signal is strongly dependent on the mismatch in transistors since the value of VPTAT is usually smaller than 100 mV at room temperature.
3.2.2 Prototype II: Cascode Configuration
The second MOS PTAT prototype [26], [27] is shown in Fig. 3.4. In the elementary cell, the two transistors M1 and M2 both operate in the subthreshold region. Because M2 is diode connected, it operates in the forward saturation mode and forces M1 to operate in the conduc tion mode. Since M2 operates in the saturation mode,
t Since M1 operates in the conduction mode,
(a)
(b)
Figure 3.4 MOS PTAT generator prototype II: cascode configuration. (a) Elementary cell. (b) Stack of elementary cells.
If M1 and M2 are matched, the PTAT voltage can be derived from Equation 3.14 and Equation 3.15:
practically obtainable from an elementary cell are limited to about 100 mV. Higher values may be obtained by stacking a certain number of cells as shown in Fig. 3.4(b).
In this circuit, the voltage VPTAT is composed of three sections. The mode of operation is still the same, except that the current supplied to each cell goes through the bottom transistor of all subsequent cells. For instance, the PTAT voltage formed by section
M1-M2 is given by
Fig. 3.5 shows the simulated circuit and the PTAT voltage plot of this prototype.
In Fig. 3.5(a), the transistor M3 which operate in strong inversion serves as a current source and the minimum supply voltage is given by
p straight line at high temperature due to the effect of leakage currents.
(a) (b)
Figure 3.5 Simulation of MOS PTAT prototype II. (a) Simulation circuit. (b) PTAT voltage versus temperature.
We now consider the effect of transistor mismatch in the circuit shown in Fig.
3.5(a). Applying the expressions in Equation 3.7 and Equation 3.8 and neglecting high-order terms, we obtain
If S2 >> S1, the PTAT voltage can be rewritten as the current mismatch in the PMOS current mirror. Since the voltage variations of the three cells are not statistically correlated, the standard deviation of the voltage variation is therefore multiplied by 3 and the spread of VPTAT is reduced.
3.2.3 Prototype III: Common Gate Connection
Fig. 3.6 shows the third MOS PTAT prototype [12], [13], [27]-[30]. If transistors M1 and M2 are in weak inversion and their drain-source voltages are both much larger then Ut, the drain currents can be expressed as
t
Assuming that M1 and M2 are matched, the PTAT signal can be obtained and is given by
Figure 3.6 MOS PTAT generator prototype III: common gate connection.
We also examine the temperature characteristic of this prototype circuit through simulation. The simulated circuit shown in Fig. 3.7(a) is derived from a circuit used with bipolar transistors and has been utilized in several designs. The p-channel MOSFETs M3 and M4 act as a current mirror and the minimum supply voltage is given by
p , SG w , DS PTAT min ,
DD V V V
V = + + (3.23)
where VDS,w is the drain-source voltage of the transistor in weak inversion. In the simulation, the device size ratios S1 and S2 are set to equal while the current ratio ID2／ID1 is 10. Fig. 3.7(b) shows the PTAT voltage VPTAT versus temperature. At high temperature, deviations from the ideal PTAT behavior due to leakage currents are also observed.
(a) (b)
Figure 3.7 Simulation of MOS PTAT prototype III. (a) Simulation circuit. (b) PTAT voltage versus temperature.
Consider the circuit shown in Fig. 3.7(a). The variation of VPTAT may come from threshold voltage and current factor mismatch in M1-M2 pair and the current mismatch in the current mirror formed by M3 and M4. Applying the mismatch parameters defined by Equation 3.7 to Equation 3.9 in the derivation of VPTAT, we obtain
n
Note that the mismatch terms in Equation 3.24 are almost the same as those in Equation 3.20. In this circuit, the mismatch of resistor does not affect the PTAT voltage as long as M1 and M2 both operate in weak inversion.
3.2.4 Summary
The temperature and mismatch characteristics of MOS PTAT prototypes have been addressed in the previous paragraphs. These results are summarized in Table 3.1. The
∆βp／βp terms are omitted in expressions of ∆VPTAT since the current factor mismatch in strong inversion is negligible compared to that in weak inversion.
The PTAT signal of prototype I is proportional to nUt while the other two prototype circuits generate output voltages proportional to Ut. The value of the slope factor n ranges usually from 1.3 to 2 and a larger VPTAT can be obtained in prototype I.
In a standard CMOS process, however, the slope factor is not a reliable parameter and its value depends slightly on the bias conditions. Furthermore, the higher supply voltage requirement due to diode-connected transistors makes prototype I incompatible with low-voltage operation.
Table 3.1 Characteristics of MOS PTAT prototypes.
Prototype VPTAT ∆VPTAT VDD,min
The characteristics of prototypes II and III are very similar. Prototype II provides a floating PTAT voltage and the elementary cells can be stacked to produce PTAT voltages of the order of a few hundreds of millivolts. As an additional advantage, the mismatch between transistors is averaged out in a stacked PTAT generator. The spread of VPTAT can be reduced at the expense of a larger supply voltage.
3.3 Low-Voltage PTAT References in Deep-Submicron Technology
Low- voltage implementations for PTAT references are necessary for the complete system-on-chip such as thermal management system. Such PTAT references must exhibit the best compatibility in deep-submicron technology. In the following paragraphs, we will investigate the low-voltage MOS PTAT references in detail.
3.3.1 Power-Supply Rejection Ratio (PSRR)
The MOS PTAT prototype circuit shown in Fig. 3.7(a) seems suitable for low-voltage designs. However, the power-supply rejection ratio (PSRR) of this circuit deteriorates sharply in deep-submicron technology. Fig. 3.8 shows the low- frequency small-signal model of the MOS PTAT generator shown in Fig. 3.7(a). From Fig. 3.8, the small-signal gain vptat／vdd can be derived to
( )
Figure 3.8 Low- frequency small-signal model of the MOS PTAT generator shown in Fig. 3.7(a).
( )
Since M1 and M2 are in weak inversion and M3 and M4 act as a current mirror,
g P
Substituting Equation 3.27 into Equation 3.26, we have
1
In deep-submicron technology, the ratio gm 1／go1 is typically smaller than 200 and the resulting static PSRR+ is usually smaller than 50 dB. Fig 3.9 shows the simulated VPTAT and static PSRR+ versus supply voltage at room temperature for the PTAT generator shown in Fig. 3.7(a). For PSRR(DC)+ > 40 dB, the minimum supply voltage is 1.5 V.
Figure 3.9 Simulated VPTAT and static PSRR+ versus supply voltage at room temperature for the PTAT generator shown in Fig. 3.7(a).
A low-voltage MOS PTAT reference based on the same prototype [13] is depicted in Fig. 3.10. The simple current mirror in Fig. 3.7(a) is replaced by the operational transresistance amplifier (ORA) composed of M3-M8. The role of the ORA is to ensure the current ratio ID2／ID1, as well as an almost equal voltage biasing for both drain voltages of M1 and M2. Thanks to the latter, the channel length modulation effects in M1-M2 can be minimized.
Figure 3.10 The low-voltage MOS PTAT reference.
The small-signal DC gain vptat／vdd of this circuit can be derived from the low- frequency small-signal model shown in Fig. 3.11. Assume go << gm for all transistors, then
( )
Figure 3.11 Low- frequency small- signal model of the MOS PTAT reference shown in Fig. 3.10.
Ideally, gm 1,2 and go1,2 are all proportional to their drain currents since M1 and M2 are both in weak inversion. As a result, gm 2·go1 = gm1·go2 and PSRR+ approximates to infinity for low frequencies. The finite static PSRR+ may arise from the higher order
effects in gm and go in reality. Fig. 3.12 shows the simulated VPTAT and PSRR(DC)+ versus supply voltage at room temperature for the low-voltage PTAT reference. From Fig. 3.12 we can observe that the static PSRR+ is improved significantly. For PSRR(DC)+ > 40 dB, the minimum supply voltage is 1.1 V and the PSRR+ is greater than 70 dB for VDD = 1.5 V.
Figure 3.12 Simulated VPTAT and static PSRR+ versus supply voltage at room temperature for the low-voltage PTAT reference shown in Fig. 3.10.
3.3.2 Accuracy
The use of ORA in the low-voltage PTAT reference may lead to a larger spread of VPTAT due to the extra current mirrors. Defining average and mismatch quantities, we have
8 2
Applying this set of equations in the derivation of VPTAT, we obtain
n
In this circuit, the VPTAT variation due to current factor mismatch in strong inversion is approximately three times as large as that in conventional MOS PTAT circuits.
3.3.3 Circuit Compensation
The low-voltage MOS PTAT reference has two feedback paths and may require proper compensation. Consider the open- loop circuit shown in Fig. 3.13. The first feedback path consists of a common-source stage with source degeneration and a current mirror. Therefore, the small-signal current i′1 can be expressed as
( )
The second path consists of a common-source stage and two current mirrors and the small-signal current i′2 is given by
3
Figure 3.13 Open- loop circuit of the low- voltage MOS PTAT reference.
The small-signal gain vo／vi is thus
The dominant pole is located at the output node and is given by (r ||r ) C
Therefore, the gain-bandwidth product can be expressed as
( )
Values of gm 1 and C must be designed so that the gain-bandwidth product is well below the other poles arising from parasitic capacitances. Fig. 3.14 shows the simulated frequency response of the open- loop circuit for three values of gm 1／C. The unit-gain frequency is found proportional to gm 1／C as described in Equation 3.42.
Figure 3.14 Frequency response of the open-loop circuit shown in Fig. 3.13.
3.3.4 All-MOS Implementations
The presence of the resistor may be a drawback in a low-voltage MOS PTAT reference. For an extremely low bias current, a high value resistance is required which takes a large surface area. The resistivity is also not guaranteed by some foundries and may vary with technology. The resistor of the PTAT generator in Fig. 3.10 can be replaced by a MOSFET working below saturation [13], [29]. Fig. 3.15 depicts the all-MOS implementations for the low-voltage PTAT reference. In both circuits, transistor M9 operates in the strong inversion conduction mode while M10 and M11 are in the strong inversion saturation mode.
(a)
(b)
Figure 3.15 Low- voltage MOS PTAT references with all-MOS implementation.
The drain currents of M9 and M10 are given by [15]
For the circuit in Fig. 3.15(a),
11
Substituting Equation 3.43 into Equation 3.44 and solving for VG- Vt0, we obtain
( )
Therefore, the drain current of M9 in Fig. 3.15(a) is
( ) Equation 3.47.
Similarly, the drain current of M9 in Fig. 3.15(b) can also be obtained in the same way. Assume that S10 = N·S9 and S11 = M·S8, then
The drain current of M9 in Fig. 3.15(b) can therefore be derived to
( ) ( )
Also, for given values of the PTAT voltage and the bias current, the transistor size S9
can be determined.
3.4 Leakage Currents and Proposed Compensation Technique
There are at least three essential requirements for the PTAT reference in an on-chip temperature sensor: i) the circuit must exhibit the best compatibility against process scaling, ii) the supply voltage should be compatible with the complete system-on-chip, and iii) the PTAT signal must be linear over a wide range of temperature. The low-voltage PTAT generators described in the previous section fulfill the first two requirements for a complete temperature sensor. However, these circuits suffer from the no nlinearity problem if the temperature is higher than 100°C. This nonlinear behavior mainly results from the junction leakage currents in MOS transistors at high temperature. In this section, we first discuss the effect of leakage currents and then a compensation technique is proposed to enhance the linearity of high temperature behavior.
In the CMOS structure, the source/drain implants and the substrate (or the n-well) form the pn junction diodes and may conduct leakage currents in the devices. Fig.
3.16 illustrates the leakage currents through the junction diodes in MOS transistors.
These leaky diodes are generally reverse-biased since the bulk of n-channel MOSFETs is tied to the ground and that of p-channel MOSFETs to the most positive supply voltage. The leakage current which is the reverse-bias saturation current of the diode is associated with the doing concentrations and is strongly dependent on temperature.
Figure 3.16 The leaky junction diodes in MOS transistors.
At room temperature, these leaky diodes conduct almost no current and do not influence the operation of transistors. However, the leakage current increases sharply in high temperature and degrades the performance of analog circuits. Fig. 3.17 shows the leakage current versus temperature in a 0.25-µm CMOS process. Leakage currents
in both n-channel and p-channel MOSFETs with different channel widths and lengths are plotted in this figure. The leakage current is found slightly dependent on the channel length and proportional to the gate wid th since the current in a diode is proportional to its area. Furthermore, n-channel MOSFETs have larger leakage current s due to the lower channel doping concentration.
Figure 3.17 Leakage current versus temperature.
Due to the extremely low current in weak inversion, the leakage current becomes comparable to the current level in a MOS PTAT generator. Fig. 3.18 shows the VPTAT curves of the circuit in Fig. 3.15(a) with different values of ID1. For smaller bias current level, the influence of leakage cur rents on the PTAT voltage is more severe.
Figure 3.18 VPTAT curves of the circuit in Fig. 3.15(a) with different ID1.
Consider the MOS PTAT reference shown in Fig. 3.15(a). As described before, the PTAT voltage VPTAT is determined by the product of transistor size ratio S1／S2 and current ratio ID2／ID1. Taking the leakage currents into account in high temperature, the expression of VPTAT becomes
( ) ( ) ( ) M8 respectively. Since the leakage currents in M3-M8 are balanced,
( ) ( )
The last term in the above equation is the non-PTAT term. If IDB1(T)／P·I1(T) << 1, this nonlinear term can be rewritten as
( ) ( ) ( )
Fig 3.19 shows the nonlinearity of PTAT voltage in the circuit shown in Fig. 3.15(a).
Figure 3.19 Nonlinearity of the PTAT voltage in the circuit show in Fig. 3.15(a).
From Fig. 3.19 we can observe that the nonlinear behavior in high temperature primarily results from the leakage currents and it can be described by Equation 3.53.
The nonlinearity behavior is a crucial effect to implement a complete thermal mana gement system within a digital circuit since such circuitry requires more effort and cost for after process calibration. As a result, solutions for improving the linearity of high temperature behavior are necessary. Fig. 3.20 depicts the schematic of all-MOS PTAT reference with leakage compensation. Compensation transistors Mc1
and Mc2 are attached to the drain terminals of M1 and M2 respectively. The effects of leakage currents in M3-M8 are eliminated since the leakage currents are proportional to device sizes and thus are all balanced in these transistors. At room temperature, the two compensation transistors Mc1 and Mc2 do not interfere with normal operation of the circuit since the gate of Mc1 is connected to VDD and that of Mc2 to the ground. In high temperature, additional leakage currents come from Mc1 and Mc2 will compensate the leakage currents in M1 and M2 as illustrated in Fig. 3.20.
Figure 3.20 All-MOS PTAT reference with leakage compensation.
Fig. 3.21 presents the simulated temperature characteristics of VPTAT for all- MOS and compensated PTAT references. The linearity at high temperature is improved significantly in the proposed compensated PTAT reference. From this figure we can observe that the PTAT circuit with compensation may extend the temperature range at least 30°C.
The MOS PTAT reference with leakage current compensation can exhibit the best compatibility against supply scaling in deep-submicron technology. The power consumption is also made minimum due to the inherently low currents in subthreshold
MOSFETs. Furthermore, the PTAT signal exhibits high linearity over a wide range of temperature. Hence, the proposed compensation technique allows the integration of PTAT references in deep-submicron technology for complete temperature sensors.
Figure 3.21 Simulated VPTAT versus temperature for all-MOS and compensated PTAT references.
4
IMPLEMENTATION OF CMOS PTAT REFERENCES
Experimental implementations of the MOS PTAT references including leakage-compensated circuit have been fabricated in TSMC 0.25-µm double-poly five-metal CMOS process. Design issues as well as layout considerations of the MOS PTAT references are thoroughly discussed in this chapter. Following the description of test setup, the experimental results are presented and discussed. The characteristics of experimental PTAT references are summarized in the end of this chapter.
4.1 Realization
In order to demonstrate the applicability of the proposed leakage compensation technique, so as to implement the competitive temperature sensors in deep-submicron technology, three MOS PTAT references are designed and implemented in a 0.25-µm CMOS technology. In this section, implementation issues of the experimental PTAT references are described in detail.
The first implemented circuit is the resistor-based MOS PTAT reference which has been discussed in Chapter 3. The schematic is redrawn in Fig. 4.1. The circuit is designed to exhibit an output voltage of about 60 mV at room temperature. Device sizes of M1 and M2 which operate in weak inversion are set to equal for matching consideration. As a result, the current ratio ID2／ID1 = 10 is chosen here to generate the required VPTAT. It is important for M1 and M2 to operate in weak inversion region.
Therefore, the current gain factors of the two transistors have to be larger than the value corresponding to the limit of weak inversio n region [12]:
Figure 4.1 The R-based MOS PTAT reference.
The minimum value of S1,2 ensuring subthreshold operation can thus be calculated from this relation. With µn·C′ox = 150 µA／V2 in this 0.25-µm technology, S1,2 > 100 is required for the drain currents of few microamperes. In the circuit, the gate voltage of M1-M2 pair is design to be well below the threshold voltage and the current ID1 is chosen as 300 nA. Using Equation 2.23 along with the extracted parameters, I0 and n, a value of about 140 for S1,2 can be obtained. In addition, a resistor R ≈ 200 kΩ is required for this bias current.
An important aspect of the performance of the PTAT reference is its accuracy. As discussed in Chapter 3, the variance of the relative variation in the PTAT voltage can be expressed as
( ) ( )
( )
( ) ( )Applying the Pelgrom model described in Equation 2.28 to the mismatch parameters, the above equation can be rewritten as
( )
Values of these proportionality constants in a 0.35-µm technology are: Aβn = 1.9
%·µm, Aβp = 2.25 %·µm, and AVt0 = 9 mV·µm [31]. In general, the accuracy of the
PTAT voltage is dominated by the threshold voltage mismatch. For relative deviations (∆VPTAT／VPTAT) ≤ 5%, which corresponds to σ(∆VPTAT／VPTAT) ≤ 2.5% when a 2σ law is used, the required device area for the M1-M2 pair (W·L)1,2 = 16 µm2 is obtained.
To minimize the current mismatch in current mirrors, transistors M3-M8 are designed to operate in deep strong inversion. Device sizes of M3 and M6 are designed identical to those of M4 and M7 respectively for matching consideration. Furthermore, the drain currents in M7 and M8 are also designed equal to reduce the power consumption. Designing the overdrive Vov = 150 mV for all transistors in strong inversion, the device sizes of M3-M8 can be roughly obtained from square law:
2 8 3 8
3
2
ov ' ox
D
V C S I
⋅
⋅
= ⋅ −
− µ (4.4) The values of µ·C′ox for NMOS and PMOS in this 0.25-µm technology are about 150 µA／V2 and 40 µA／V2 respectively.
The other two experimental circuits are all-MOS and compensated all- MOS PTAT references. The condensed scheme of these two circuits is shown in Fig. 4.2. In the all-MOS implementation, the PTAT core, M1-M2, and the ORA, M3-M8, are all designed identical to those in the R-based PTAT reference. The transistor sizes of
The other two experimental circuits are all-MOS and compensated all- MOS PTAT references. The condensed scheme of these two circuits is shown in Fig. 4.2. In the all-MOS implementation, the PTAT core, M1-M2, and the ORA, M3-M8, are all designed identical to those in the R-based PTAT reference. The transistor sizes of