Experimental Results

The output voltages of the experimental PTAT references are measured by an oscilloscope. Table 4.2 lists the measured PTAT voltages for each circuit at room temperature. A fairly large spread in voltage values of about 15% is observed. This is likely because the mismatches in subthreshold MOSFETs and small transistors are larger than the predicted value s from Pelgrom model.

Fig. 4.12 shows the PTAT voltage versus temperature for all-MOS and compensated PTAT references. The dashed lines are the regressions of measured data from 35°C to 95°C for each circuit. The VPTAT curve of the all-MOS version deviates from the straight line when temperature is above 95°C. The R-squares of all-MOS and compensated circuits are 0.994 and 0.868 respectively. The temperature behavior of the R-based PTAT generator is similar to the all-MOS version and is shown in Fig.

4.13. Its R-square is only 0.79.

Table 4.2 Measured PTAT voltage at room temperature.

Avg. Max. Min. Variation

R-based 70.01 74.65 61.12 12.64%

All-MOS 63.67 71.38 59.14 12.11%

VPTAT (mV)

Compensated 43.77 50.22 39.43 14.74%

Figure 4.12 Measured PTAT voltage versus temperature for all-MOS (crosses) and compensated (circles) PTAT references.

Figure 4.13 Measured PTAT voltage versus temperature for R-based (triangles) and compensated (circles) PTAT references.

Fig. 4.14 shows the spread of VPTAT for the compensated PTAT reference. The offset comes from the process variation and is dominated by the threshold voltage mismatch ∆Vt0 as described in section 4.1. Since ∆Vt0 is insensitive to temperature, the offset of PTAT voltages is almost a constant in the whole temperature range.

Therefore, the offset error can be easily calibrated by other circuits in the thermal management system.

Figure 4.14 The spread of measured PTAT voltages for the compensated PTAT reference.

4.4 Summary

This chapter described in detail the implementation of MOS PTAT references in a 0.25-µm CMOS process and presented the experimental results. The experimental results show that the PTAT reference without compensation has severe nonlinearity problem in high temperature. The linearity is improved significantly in the proposed compensated circuit and the operating temperature range of this circuit can be extended to at least 155°C. A large spread of VPTAT due to process variation is also observed. This is not a relevant problem for our application since the offset can be easily calibrated by digital circuits.

5

CONCLUSIONS

The utilization of subthreshold MOSFETs has been shown to be an attractive means of implementing low-voltage low-power PTAT references. This thesis has demonstrated the feasibility of using such approach in deep-submicron technology.

This work has focused on three major topics: the subthreshold operation of MOS transistors, the analysis and design of the MOS PTAT references, and a leakage compensation technique.

We introduced the analytical subthreshold MOSFET model and the effective approach to link both analytical and accurate models. The simple equation describes the simulated drain current in weak inversion well and the technique, which maps the accurate BSIM to a simple conventional model, makes designs using the weakly inverted MOSFET more efficient.

Analysis of the MOS PTAT references based on the analytical model identified the topology as suitable for low- voltage and low-power applications. Experimental PTAT references based on the analysis presented in this work were designed and integrated in TSMC 0.25-µm 1P5M standard CMOS technology. Experimental results confirmed the feasibility of the PTAT circuits in deep-submicron technology.

Precautions have to be taken against the large spread of the PTAT voltage.

A pure CMOS PTAT reference, which applied a compensation technique to enhance the linearity of high temperature behavior, has also been implemented in this 0.25-µm technology. Testing results showed that the linear range of the voltage output has been expanded to at least 155°C, which implies that the temperature sensor requires calibration only of its offset. Thus, the effort for after process calibration is minimized.

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