Realization

IMPLEMENTATION OF CMOS PTAT REFERENCES

Experimental implementations of the MOS PTAT references including leakage-compensated circuit have been fabricated in TSMC 0.25-µm double-poly five-metal CMOS process. Design issues as well as layout considerations of the MOS PTAT references are thoroughly discussed in this chapter. Following the description of test setup, the experimental results are presented and discussed. The characteristics of experimental PTAT references are summarized in the end of this chapter.

4.1 Realization

In order to demonstrate the applicability of the proposed leakage compensation technique, so as to implement the competitive temperature sensors in deep-submicron technology, three MOS PTAT references are designed and implemented in a 0.25-µm CMOS technology. In this section, implementation issues of the experimental PTAT references are described in detail.

The first implemented circuit is the resistor-based MOS PTAT reference which has been discussed in Chapter 3. The schematic is redrawn in Fig. 4.1. The circuit is designed to exhibit an output voltage of about 60 mV at room temperature. Device sizes of M1 and M2 which operate in weak inversion are set to equal for matching consideration. As a result, the current ratio ID2／ID1 = 10 is chosen here to generate the required VPTAT. It is important for M1 and M2 to operate in weak inversion region.

Therefore, the current gain factors of the two transistors have to be larger than the value corresponding to the limit of weak inversio n region [12]:

Figure 4.1 The R-based MOS PTAT reference.

The minimum value of S1,2 ensuring subthreshold operation can thus be calculated from this relation. With µn·C′ox = 150 µA／V² in this 0.25-µm technology, S1,2 > 100 is required for the drain currents of few microamperes. In the circuit, the gate voltage of M1-M2 pair is design to be well below the threshold voltage and the current ID1 is chosen as 300 nA. Using Equation 2.23 along with the extracted parameters, I0 and n, a value of about 140 for S1,2 can be obtained. In addition, a resistor R ≈ 200 kΩ is required for this bias current.

An important aspect of the performance of the PTAT reference is its accuracy. As discussed in Chapter 3, the variance of the relative variation in the PTAT voltage can be expressed as

( ) ( )

( )

Applying the Pelgrom model described in Equation 2.28 to the mismatch parameters, the above equation can be rewritten as

( )

Values of these proportionality constants in a 0.35-µm technology are: Aβn = 1.9

%·µm, Aβp = 2.25 %·µm, and AVt0 = 9 mV·µm [31]. In general, the accuracy of the

PTAT voltage is dominated by the threshold voltage mismatch. For relative deviations (∆VPTAT／V_PTAT) ≤ 5%, which corresponds to σ(∆VPTAT／V_PTAT) ≤ 2.5% when a 2σ law is used, the required device area for the M1-M2 pair (W·L)1,2 = 16 µm² is obtained.

To minimize the current mismatch in current mirrors, transistors M3-M8 are designed to operate in deep strong inversion. Device sizes of M3 and M6 are designed identical to those of M4 and M7 respectively for matching consideration. Furthermore, the drain currents in M7 and M8 are also designed equal to reduce the power consumption. Designing the overdrive Vov = 150 mV for all transistors in strong inversion, the device sizes of M3-M8 can be roughly obtained from square law:

2 8 3 8

3

2

ov ' ox

D

V C S I

⋅

⋅

= ⋅ ⁻

− µ (4.4) The values of µ·C′ox for NMOS and PMOS in this 0.25-µm technology are about 150 µA／V² and 40 µA／V² respectively.

The other two experimental circuits are all-MOS and compensated all- MOS PTAT references. The condensed scheme of these two circuits is shown in Fig. 4.2. In the all-MOS implementation, the PTAT core, M1-M2, and the ORA, M3-M8, are all designed identical to those in the R-based PTAT reference. The transistor sizes of M9-M11 are derived from Equation 3.49 and from power considerations: M = 1 and N

= 1.5. In the compensated version, an n-channel MOSFET is used for matching consideration.

Figure 4.2 All-MOS and compensated all-MOS PTAT references.

According to the discussions above, the transistor aspect ratios are summarized in Table 4.1 for the three experimental circuits.

Table 4.1 MOS PTAT references component values.

R-based All-MOS Compensated

Component Value Component Value Component Value

M1, M2 48／0.36 M1, M2 48／0.36 M1, M2 48／0.36

M3, M4 0.6／2.8 M3, M4 0.6／2.8 M3, M4 0.6／2.8

M5 6.4／0.6 M5 6.4／0.6 M5 6.4／0.6

M6-M8 0.64／0.6 M6-M8, M11 0.64／0.6 M6-M8, M11 0.64／0.6

R 245.6 kΩ M9 0.6／2 M9 0.6／2

M10 0.6／2.8 M10 0.6／2.82

Mc 432／0.36

Figs. 4.3-4.6 present the simulation results of these three experimental circuits.

Fig. 4.3 shows the PTAT vo ltage versus supply voltage at room temperature. In this figure, curves for all-MOS and compensated all-MOS PTAT references are the same.

Figure 4.3 Simulated VPTAT versus VDD at room temperature.

Fig. 4.4 presents the temperature characteristics of these PTAT references. The R-based and all- MOS versions have similar temperature behavior and they both encounter nonlinearity problem in high temperature.

Figure 4.4 Simulated VPTAT versus temperature.

The VPTAT histogram plots for R-based and all-MOS PTAT references are shown in Fig. 4.5 and Fig. 4.6 respectively. The result of the compensated circuit is quite similar to that of the all-MOS version and is not shown for simplicity.

Figure 4.5 VPTAT histogram at room temperature from 1000´ Monte Carlo runs for the R-based PTAT reference.

Figure 4.6 VPTAT histogram at room temperature from 1000´ Monte Carlo runs for the all-MOS PTAT reference.

Since the PTAT voltage is sensitive to the device mismatch, a good layout should group the transistors in the following manner:

Group N1: M1, M2, and Mc (weak inversion) Group N2: M3 and M4 (strong inversion) Group N3: M9 and M10 (strong inversion) Group P: M5-M8, M11 (strong inversion)

In each group, the transistors are in the same orientation and have the minimum separation allowed in design rule. The most important devices in the PTAT references are the subthreshold MOSFETs M1 and M2. They are decomposed into identical unit transistors of exactly the same geometry and these unit transistors are interleaved and have a common centroid.

The experimental chip is fabricated in TSMC 0.25-µm single-poly five-metal CMOS technology. The resistor in the R-based circuit is implemented by the p+ poly resistor for resistivity and temperature coefficient s considerations. Fig. 4.7 shows the microphotographs of the R-based and the compensated all-MOS circuits. The right side of the compensated circuit is the all-MOS PTAT reference. Surface areas for R-based, all-MOS, and compensated circuits are about 10,000 µm², 900 µm², and 2000 µm² respectively.

(a)

(b)

Figure 4.7 Microphotographs of (a) R-based and (b) compensated all-MOS PTAT references.