CHAPTER 1 Introduction
1.3 Organization of the Thesis
In this thesis, the dielectric properties of high-κ dielectrics, some reliability issues such as breakdown field, charge trapping and temperature-dependence behaviors were extensively studied for both gate dielectric and DRAM applications. Chapter 1 showed the background and the motivation for the applications of the high-κ dielectrics.
In chapter 2, the effects of O3 post deposition annealing temperature on the properties of Ta2O5 were researched by COCOS non-contact metrology.
In chapter 3, the influences of surface treatments prior to hafnium oxide (HfO2) deposition were investigated. Comparisons between various surface treatments, including:
ozone water oxidation (Ozone), rapid thermal oxidation (RTO) and ammonia (NH3) nitridation were studied.
In chapter 4, the surface treatment effects on the charge trapping characteristics of the HfO2 gate dielectric were studied in terms of trapping efficiency, conductance peak shift, and SILC defect generation. The current transport mechanism was also investigated.
At the end of this thesis, the conclusions and the recommendations for the topics which could be further researched were given in chapter 5.
Fig. 1-1 Schematic cross section of stacked capacitor cell suitable for 0.15µm [Ref. 10].
Year of Production 2003 2004 2005 2006 2007 2008 2009
Technology Node hp90 hp65
DRAM 1/2 Pitch (nm) 100 90 80 70 65 57 50 DRAM cell size (µm2) 0.082 0.065 0.048 0.036 0.028 0.019 0.015 DRAM storage cell
dielectric: EOT (nm) 3.5 2.3 1.8 1.3 0.8 0.8 0.8 Generation at production 1G 1G 1G 2G 2G 4G 4G
Manufacturable solutions, and are being optimized Manufacturable solutions are known
Manufacturable solutions are NOT known
Table 1.1 DRAM technology requirements [Ref. 3]
High-κ Dielectrics
HfO2 ZrO2 Al2O3
Bandgap (eV) 6.02 5.82 8.3
Barrier Height to Si (eV) 1.6 1.5 2.9
Dielectric Constant ~30 ~25 9
Heat of Formation
(Kcal/mol) 271 261.9 399
∆G for Reduction
(MOx + Si → M + SiOx) 47.6 42.3 64.4
Thermal expansion coefficient
(10-6 K-1) 5.3 7.01 6.7
Lattice Constant (Å)
(5.43 Å for Si) 5.11 5.1 4.7 - 5.2
Oxide Diffusivity
@ 950oC (cm2/sec) 1x10-12 5x10-25
Table 1.2 Materials properties of high-κ dielectrics, Al2O3, ZrO2, and HfO2.
CHAPTER 2
Effects of O
3PDA Temperature on the Properties of Ta
2O
5Measured by COCOS Metrology
2.1 Introduction
MOS-oxide-semiconductor (MOS) devices are the most widely used devices in the semiconductor industry. For example, MOS capacitors are used as the storage elements in dynamic random access memory (DRAM) applications. While most properties are scaled down with successive generations, the DRAM bit cell capacitance must remain a relatively constant value determined by the sense amplifier operation and robustness against alpha-particle-induced soft errors. The shrinkage of bit cell area with each generation leaves us with three approaches for maintaining constant capacitance per bit: (1) reducing the thickness of the dielectric; (2) increasing the area by forming three-dimensional (3D) capacitor structures, and (3) increasing the dielectric constant through the introduction of new high-permittivity materials.
A conventional MOS device uses SiO2 as the material for the insulator layer. The characteristics of the MOS device are dominated by the characteristic of the insulator layer.
The development of high-density DRAM has been accomplished by reducing the thickness of the SiO2 storage capacitors to maintain the required charge storage level. One of the most important features for a material to be used as the insulating dielectric in DRAM is the low leakage current. However, as the insulator thickness decreases, the SiO2 insulator layer often fails due to electron tunneling and the leakage current problem becomes severe. Therefore,
various high dielectric constant (κ) materials have been recommended to replace SiO2 for solving the leakage problem. If the leakage current of the high-κ material is lower than that of the conventional SiO2 film under the same equivalent oxide thickness (EOT), it will be suitable candidate to replace the conventional oxide for DRAM application.
Currently, Ta2O5 thin films are considered as one of the most promising materials that can be used for high-density DRAM applications, but many electrical and physical properties of this high-κ material are still under research. Tantalum pentoxide is a potential film material because of its high dielectric constant (>22). Except to the advantage of high dielectric constant, Ta2O5 film also has some important advantages.
1. The dielectric constant is independent of the applied voltage.
2. Ta2O5 film can be easily removed by using CF4 [16].
Tantalum pentoxide has been extensively studied by many techniques: radio-frequency [23, 24], magnetron [25, 26] or ion-beam sputtering [27], thermal oxidation, pulsed laser deposition (PLD) [28], chemical vapor deposition (CVD) [29, 30], sol-gel processing [31, 32]
and anodization of thin Ta or TaN film [33].
One of the unresolved problems of Ta2O5 which is typical of many high-k dielectrics is the unavoidable formation of an interfacial SiO2 layer which minimizes the interface state density and reduces the intermixing of Si and Ta2O5, but at the same time it decreases the global dielectric constant of the film. As a result, the obtained dielectric constant is not adequate to reach an equivalent dielectric thickness of less than 2 nm with an acceptable leakage current level, the presence of 2-nm-thick interfacial SiO2 compromises the benefits of
Ta2O5 as a high-κ. Besides, as-deposited Ta2O5 films exhibit sufficient leakage current [18], [34]-[36] due to the organic impurities and/or oxygen vacancies. It has been known that the leakage current can be decreased by post-deposition treatment (650-800oC) [35, 36] and ozone annealing [18], [34]. In this chapter, the effect of ozone annealing on the properties of Ta2O5 films grown by metal-organic chemical vapor deposition (MOCVD) was investigated.
2.2 Experiment Details
12 inch p-type (100) silicon wafers were cleaned by standard RCA processes with HF-last for the removal of the particles and native oxides. Prior to high-κ dielectrics deposition, the samples were prepared by NH3 nitridation at 700oC for 1 minute to generate an ultra-thin oxynitride layer (~4.5 Å). After the surface treatment, 85Å Ta2O5 was then deposited at 430oC by TEL TriasTM Ta2O5 deposition system (Fig. 2-1). Each tantalum pentoxide film was subjected to two high temperature post deposition annealing (PDA) steps.
The first annealing was performed in the ozone gas ambient at temperatures ranging from 500oC to 700oC for 5 minutes and was called O3 annealing. The second was done in oxygen atmosphere at 800oC for 1 minute, and was called lamp annealing. The cross section, split conditions, and the total process flow were shown in Fig. 2-2. The physical gate oxide thickness was determined by Rudolph ellipsometer in two kinds of mode: refractive index (n)
& absorption index (k) fixed and n & k opened. The electrical properties and reliability characteristics of the Ta2O5 films measured using SDI FAaST series tools. The dielectric constant (κ value) was extracted by non-contact dielectric capacitance data from COCOS non-contact metrology. The flat band voltage, interface trap density, and the soft breakdown trends with O3 annealing temperature were also investigated in this chapter.
2.3 Results and Discussions
In this chapter, the effects of O3 post deposition annealing temperature on the properties of Ta2O5 were investigated by COCOS non-contact metrology. The measurement methodology of COCOS technique was introduced first.
2.3.1 COCOS Non-Contact Metrology [37, 38]
COCOS (Corona Oxide Characterization of Semiconductor) metrology enables gate dielectric to be quickly monitored in a non-contact manner for all wafer sizes including 300mm. The method uses corona charging in air to deposit an electric charge on a dielectric thus charging the electric field in the dielectric and in semiconductor.
Figure 2.3 shows the measurement cycle that incorporates corona charging, shifting of the sample under the probe and the contact potential difference (CPD) measurement. A blanket of corona charge is placed on SiO2 by passing the wafer under a corona wire. Charge uniformity and dose control is achieved with a combination of the wafer translation and rotation.
An energy band diagram of the silicon with SiO2 film is given in Fig. 2.4. The reference metal electrode is separated from the top SiO2 surface by about 1mm. The electric field between the electrode and the wafer is compensated by a bias opposite in sign but equal in value to VCPD. VCPD is determined by the work function difference between the reference electrode and the measured wafer; the potential drop across the oxide Vox, and also due to a modified value of semiconductor surface barrier, VSB.
VCPD = Φms + VSB + Vox (2-1)
The COCOS technique can also be used to determine dielectric capacitance. The corona charge deposited on the surface of an oxide changes the voltage drop across the oxide where the capacitance of the oxide is:
ox
The flat band voltage condition is obtained by placing the corona charge of appropriate polarity until all oxide charge becomes compensated and VSB=0. Illumination of silicon under the CPD probe reduces VSB, but it does not affect Vox. For depletion type surface barrier, it is relatively easy to flatten the surface barrier completely and to obtain VSB≈0. So the flat band voltage is considered to be the VCPD value when the difference between the VCPD curves in the dark and under illumination is zero.
VFB = VCPDdark =VCPDlight (2-3)
Another very important dielectric parameter determined by COCOS technique is QTOT. QTOT is the total charge state of the oxide/semiconductor system necessary to achieve the flat band condition. From QTOT measurement, the charges need to compensate the interface trapped charge at flat band QitFB and the oxide charge Qox could be determined.
QTOT = Qox + QitFB+ Qsurf (2-4)
The density of the interface traps, Dit, is calculated as a ratio ∆Qit/∆VSB where ∆VSB is the change in the surface barrier due to deposited quantum of corona charge. It can be seen from the relationship that the interface trap charges, ∆Qit, corresponding to a given quantum of corona charge: ∆Qit = ∆Qc − ∆Qsc. The interface trap was manifested by the plateau on the VSB vs. corona dose curve. A Dit spectrum across the band gap can be obtained by plotting Dit
versus VSB.
The last parameter that can be extracted from COCOS method is the soft breakdown
field. Positive corona charge on the top oxide surface is used to increase the electric field in the oxide, which lowers the oxide conduction band. Once the Fowler-Nordheim (F-N) tunneling takes place the electron tunneling current compensates the corona ionic current i.e .JF-N = Jcorona. Subsequent measurement of the oxide voltage (i.e. the CPD value) corrected for the surface barriergives the value of the (F-N) tunneling threshold and provides a measure of the oxide soft breakdown.
2.3.2 Investigation of O3 Annealing Effect on the Ta2O5 Films
Fig. 2-5(a) compared the physical Ta2O5 film thickness as a function of O3 annealing temperature determined by Rudolph ellipsometer in n & k opened mode. The dielectric thickness was increased as raising annealing temperature, which could be ascribed to the thick interfacial layer (IL) growth. The corresponding refractive index of the Ta2O5 films was shown in Fig. 2-5 (b). The decreasing of the refractive index was due to the increasing of the film thickness. It should be note that the n & k fixed mode results was the same for four times measurement while n & k opened mode had a little variation which could response for real thickness.
The dielectric capacitance of the Ta2O5 films as a function of PDA temperature was indicated in Fig. 2-6 (a). A lower κ-value interfacial layer in series would reduce the dielectric capacitance. Figure 2-6 (b) presented the effective dielectric constant (κ) calculated from the capacitance.
The decrease of the effective dielectric constant is essentially consistent with the increase of interfacial layer thickness caused by high temperature O3 annealing.
The VCPD in the dark and under illumination was systematically measured after incremental corona charging and a VCPD versus corona charge (Qc) plot was generated as shown in Fig. 2-7 for different O3 annealing conditions. The flat band voltage (VFB) was considered to the point of intersection between the VCPD curves in the dark and under illumination. Figure 2-8 illustrated the flat band voltage shift and the total charge to flat band (QTOT) as a function of arising annealing temperature. For the as-deposited condition, the VFB
shift toward positive direction indicated electron trapping occurred. After O3 annealing the flat band voltage shift changed to negative, this meant that the ozone annealing on Ta2O5
reduced the number of electron traps and increased the number of hole traps existing in the film. Furthermore, the QTOT decreased as rising the O3 annealing temperature. Previous studies [18], [34], [39] suggest that reactive oxygen species such as ozone effectively reduce the density of oxygen vacancies in non-treated Ta2O5 films and suppress the leakage current.
Furthermore, ozone treatment changes a structural parameter such as the Ta-O bonding length of Ta2O5 [40]. It is considered that the reduction of electron traps and the generation of hole traps by the ozone annealing is related to the change of stoichiometry of Ta2O5 from oxygen-deficient to oxygen-abundant, or to the change in the Ta-O bonding length. Figure 2-9 was the full mapping of the flat band voltage, it could be seen that the uniformity increased as arising annealing temperature.
The interface trap was manifested by the plateau on the VSB vs. corona dose curve as in Fig. 2-10. A Dit spectrum across the band gap can be obtained by plotting Dit versus VSB as shown in Fig. 2-11. Figures 2-12 and 2-13 compared the amount and the full mapping of interface trap densities as increasing the O3 annealing temperature, respectively. It had been supposed that high temperature ozone annealing could fix the dangling bond at the interface of Si/Ta2O5 proceed to minimize the interface trap density and improve the uniformity.
Figure 2-14 compared the soft breakdown field with and without corona temperature
stress (CTS) at 170oC for 5 minutes. The soft breakdown field was defined as the onset of the Fowler-Nordheim tunneling from the silicon to the dielectric. The difference of the field was due to sub-tunneling leakage current through the Ta2O5. The Weibull distributions of soft breakdown fields for the samples were shown in Fig. 2-15. Non-uniform interfacial layer oxidation after O3 annealing was supposed to cause the increasing of the field strength and break the distribution. This tendency could be seen in the full mapping of the soft breakdown field displayed in Figs. 2-16 and 2-17.
2.4 Summary
In this chapter, the effects of O3 post deposition annealing temperature on the properties of Ta2O5 were investigated by COCOS non-contact metrology. The dielectric thickness was increased as raising annealing temperature, which could be ascribed to the thick interfacial layer (IL) growth. A lower κ-value interfacial layer in series would reduce the dielectric capacitance after high temperature annealing. Moreover, the flat band voltage shift changed from positive to negative due to the electron traps elimination and partially hole traps generation in the film. It had been supposed that high temperature ozone annealing could compensate the dangling bond at the interface of Si/Ta2O5 proceed to minimize the interface trap density and improve the uniformity. Non-uniform interfacial layer oxidation after O3
annealing was supposed to cause the increasing of the field strength and break the the soft breakdown distribution.
Fig. 2-1 PSC TEL TriasTM Ta2O5 deposition system.
12 inch p-type (100) Si wafer
O3 Anneal Lamp Anneal Ta2O5 Deposition
Nitridation
RCA Clean with HF-last
NH : 10 sccm, 7003 °C, 1 min THK: 4.5±2Å
PET: 300 mg/min, O2: 2 slm, 430°C, THK: 85Å
O3 density: 200 g/m3, O2: 10 slm, Split Temperatures, 5 min,
O2: 10 slm, 800°C, 1 min
Interfacial layer SiOxNy
Ta2O5
Si
Fig. 2-2 Ta2O5 films process flow, device cross section and split conditions.
Fig. 2-3 Arrangement for corona charging and measurement used in SDI COCOS metrology [Ref. 37].
Fig. 2-4 Surface band diagram for Si/SiO2 system with a CPD reference electrode [Ref. 37].
n & k Opened Measure Mode
PDA Temperature (oC)
As-depo. 500 550 600 650 700
Dielectric Thickness (A)
90 95 100 105 110
(a)
n & k Open Measure Mode
PDA Temperature (oC)
As-depo. 500 550 600 650 700
Refractive Index
1.0 1.5 2.0 2.5 3.0 3.5 4.0
(b)
Fig. 2-5 (a) The physical Ta2O5 film thickness as a function of O3 annealing temperature determined by Rudolph ellipsometer in n & k opened mode. (b) The corresponding refractive index of the Ta2O5 films.
PDA Temperature (oC)
As-depo. 500 550 600 650 700 Capacitance (nF/cm2 )
0 500 1000 1500 2000
/
(a)
PDA Temperature (oC)
As-depo. 500 550 600 650 700
Effective Dielectric Constant
0 5 10 15 20 25
(b)
Fig. 2-6 (a) The dielectric capacitance (b) the effective dielectric constant (κ) of the Ta2O5
films as a function of PDA temperature.
(a) As-depo. (d) 600oC
(b) 500oC (e) 650oC
(c) 550oC (f) 700oC
Fig. 2-7 (a) ~ (f) Contact potential difference versus corona charge plot illustrating the determination of flat band voltage. Red line was the VCDP in the dark and the blue one showed the VCPD under illumination.
PDA Temperature (oC)
As-depo. 500 550 600 650 700
Flat Band Voltage Shift (V)
-1.0 -0.5 0.0 0.5 1.0
(a)
PDA Temperature (oC)
As-depo. 500 550 600 650 700 Q TOT (x1012 /cm2 )
-3 -2 -1 0 1 2 3
(b)
Fig. 2-8 (a) The flat band voltage shift (VFB) and (b) the total charge to flat band (QTOT) as a function of arising annealing temperature.
(a) As-depo. (d) 600oC
(b) 500oC (e) 650oC
(c) 550oC (f) 700oC
Fig. 2-9 The full mapping of the flat band voltage.
(a) As-depo. (d) 600oC
(b) 500oC (e) 650oC
(c) 550oC (f) 700oC
Fig. 2-10 The interface trap was manifested by the plateau on the VSB vs. corona dose curve.
(a) As-depo. (d) 600oC
(b) 500oC (e) 650oC
(c) 550oC (f) 700oC
Fig. 2-11 A Dit spectrum across the band gap obtained by plotting Dit versus VSB.
PDA Temperature (oC)
As-depo. 500 550 600 650 700 Interface Trap Density (x1012 cm-2 V-1 )
0 2 4 6 8 10 12 14 16
Fig. 2-12 Comparison the amount of interface trap densities as increasing the O3 annealing temperature.
(a) As-depo. (d) 600oC
(b) 500oC (e) 650oC
(c) 550oC (f) 700oC
Fig. 2-13 The full mapping of the interface trap density.
PDA Temperature (oC)
As-depo. 500 550 600 650 700
Soft Breakdown Field (MV/cm)
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Before CTS
CTS @ 170oC, 5min
Fig. 2-14 Soft breakdown field variation with and without corona temperature stress (CTS) at 170oC for 5 minutes.
Soft Breakdown Field (MV/cm)
Corona-Temperature-Stress @ 170oC, 5min
Soft Breakdown Field (MV/cm)
Fig. 2-15 The Weibull distributions of soft breakdown fields (a) without and (b) with corona temperature stress (CTS) at 170oC for 5 minutes.
(a) As-depo. (d) 600oC
(b) 500oC (e) 650oC
(c) 550oC (f) 700oC
Fig. 2-16 The full mapping of the soft breakdown field.
(a) As-depo. (d) 600oC
(b) 500oC (e) 650oC
(c) 550oC (f) 700oC
Fig. 2-17 The full mapping of the soft breakdown field during corona temperature stress (CTS) at 170oC for 5 minutes.
CHAPTER 3
Ozone Surface Treatment on the Characteristics and Reliabilities of HfO
2MOS Devices
3.1 Introduction
The shrinkage in metal-oxide-semiconductor field effect transistor dimensions is accompanied by a scaling of gate oxide thickness. It is well known that the scaling of conventional SiO2 is approaching the predicted limit due to large direct tunneling leakage current, thereby presenting a fundamental challenge to continual scaling [3]. Therefore, an alternative gate dielectric material is needed to replace SiO2. High-κ dielectrics, such as HfO2, are the potential candidates because a thicker film is utilized to reduce the direct tunneling leakage current while maintaining the same gate capacitance [41]-[44]. However, the control of SiO2-like interface between high-κ dielectrics and silicon substrate pays more and more important, since the device performances and reliability characteristics are strongly affected by the interface quality [44]. Nitridation of the Si surface using NH3 prior to the deposition of high-κ gate dielectrics has been shown to be effective in achieving the low EOT (equivalent oxide thickness) and preventing boron penetration [45, 46]. However this technique results in higher interface charges [47], which leads to higher hysteresis and reduced channel mobility.
Ozone-formed oxide (ozone oxide) has superior characteristics. Even when the formation temperature is less then 400°C, ozone oxide has a high film density comparable to that of the device-grade oxide film formed at higher temperature (e.g. 900°C) [48], a low interface trap density (Dit ~ 1010 cm2) [49], and a much thinner structural transition layer near the SiO2/Si
interface[48], [50]. The aim of this experiment was to investigate the interfacial issues at HfO2/silicon interface. The ozone surface treatment was employed to improve the interface quality between HfO2 and silicon substrate. Moreover, the rapid thermal oxidation (RTO) and the ammonia (NH3) surface treatment were also investigated as the reference in this thesis.
3.2 Experiment Details
3.2.1 Experiment Details of Ozone Oxide Growth
6 inch p-type (100) silicon wafers were cleaned by standard RCA processes with HF-last for the removal of the particles and native oxides. Figure 3-1 showed the schematic diagram of ozone water system. The ozone generator (AnserosPAP-2000) decomposed the oxygen molecular to generate ozone gas by high electrical field. The ozone gas was mixed with DI water in the dissolve unit and then pumped into the tank of wet bench. By changing the oxygen flow, DI water flux, and ozone generation power, the ozone concentration in the DI water could be adjusted. Ozone oxide was grown by immersing the Si wafer into the ozone water at room temperature. The relationship between the ozone concentration in the DI water and thickness change of ozone oxide was under investigation. Ellipsometer was utilized to measure the thickness and the etching rate in the hydrofluoboric acid (HF) of ozone oxide.
The micro-roughness of the wafer surface and the interface between ozone oxide/silicon were
The micro-roughness of the wafer surface and the interface between ozone oxide/silicon were