Conduction Mechanism of the Ozone Surface Treatment HfO 2 Dielectrics

The temperature dependence of the gate leakage current was studied to understand the current transport mechanisms. The leakage currents were measured from 25^oC to 150^oC for gate electron injection (negative VG). For the low electrical field case (<3.5 MV/cm), the experimental results fit the Schottky emission theory very well, as shown in Fig. 4-13. The leakage current governed by the Schottky emission yielded the following relationship:

⎥⎥

A Schottky barrier height of 0.95 eV between Al gate and HfO2 was extracted from these data.

The corresponding dynamic dielectric constant (εd=9.46) was in the range between the optical dielectric constant (εop=4 for HfO2) ant the static dielectric constant obtained from C-V (εs=9.5), which ensured the conduction mechanism. The band diagram of Al/HfO2/SiO2/Si capacitor simulated the low electrical field injection condition was illustrated in Fig. 4-14. It may be worth noting that, in the case of gate injection, because the Al/ HfO2 barrier height is smaller than the energy trap energy, Schottky emission mechanism dominates over the Frenkel-Poole (F-P) mechanism, therefore it is not possible to obtain the F-P trap energy from the above procedure.

Figure 4-15 showed the Fowler-Nordheim (F-N) tunneling fit in the high field range (>3.5 MV/cm). The slop of the fitted line followed the relationship:

2

barrier height value obtained from the FN tunneling characteristics (0.99 eV) was consistent with the Al/HfO2 barrier height (0.95 eV) we obtained earlier from Schottky emission analysis with an effective mass of 0.1 m0 [63]. The band diagram of Al/HfO2/SiO2/Si capacitor during the high electrical field carrier injection was illustrated in Fig. 4-16.

In section 4.3.1.1, we concluded that the hole current from substrate was considered the dominant conduction mechanism. However, in the temperature dependence measurement, the hole current term was masked by electron current, since electron current was more sensitive to temperature variation than hole current, which could be proved by carrier separation measurement demonstrated in Fig. 4-17 [64].

4.4 Summary

In this chapter, the surface treatment effects on the charge trapping characteristics the HfO2 gate dielectric were studied in terms of trapping efficiency, conductance peak shift, and SILC defect generation. Ozone oxide performed the lowest trapping efficiency, Dit

degradation and defect generation rate after 600^oC PDA than NH3 or RTO treatment partially due to the better interface properties. However, Ozone-samples without PDA expressed poor results, which might be caused by the incomplete oxidation and rougher interface owing to the low growth temperature. The low Dit generation and Pg value of NH3-treated dielectric was ascribed to the strong Si−N bonding at the Si/dielectric interface against the defects creation.

Unfortunately, higher interface charges for as-deposited NH3-treated dielectric would limit nitridation application. RTO also exhibited a poor defect generation resistance than Ozone-treated dielectric. The current transport mechanism was also investigated. When Eeff<3.5 MV/cm, the corresponding current transport mechanism was Schottky emission

under gate injection conditions. F-N tunneling dominated the conduction mechanism during 6>Eeff>3.5 MV/cm.

w/o PDA Samples

PDA 600^oC Samples CVS -3.8V

Fig. 4-1 Effects of surface treatment on transient charge trapping behaviors of HfO2

dielectrics (a) without PDA and (b) with 600^oC PDA under a constant voltage stress (CVS) of -3.8V.

w/o PDA Samples

PDA 600^oC Samples CVS -3.8V

Fig. 4-2 The corresponding flat band voltage shift of HfO2 dielectric (a) without PDA and (b) with 600^oC PDA for various surface treatments under a CVS of -3.8V.

w/o PDA Samples CVS -3.8V

Injected Charges (C/cm²)

10^-3 10^-2 10^-1

Trapped Charges ( x1011 cm-2 ) 0

PDA 600^oC Samples CVS -3.8V

Injected Charges (C/cm²)

10^-4 10^-3 10^-2 10^-1 10⁰

Trapped Charges ( x1011 cm-2 ) 0

Fig. 4-3 Trapped charges comparison of HfO2 dielectric (a) without PDA and (b) with 600^oC PDA for various surface treatments.

w/o Treatment NH3 RTO Ozone Trapping Efficiency ( x1011 /C)

0 2 4 6 8 10

w/o PDA PDA 600^oC

Fig. 4-4 Comparison of the trapping efficiency between several surface treatments.

Al HfO

₂ ^SiO2

p-Si

3.1 eV

4.7 eV

h

⁺

e

-1.28 eV

Al HfO

₂ ^SiO2

p-Si

3.1 eV

4.7 eV

h

⁺

e

-1.28 eV

Fig. 4-5 The band diagram of Al/HfO2/SiO2/Si capacitors included the two leakage current components under CVS condition.

Ozone Samples

Fig. 4-6 The C-V and G-V curves of Ozone-treated HfO2 dielectric (a) without PDA and (b) with 600^oC PDA under a CVS of -3.8V.

w/o PDA Samples

PDA 600^oC Samples CVS -3.8V

Fig. 4-7 The changes of the conductance peak value of HfO2 dielectric (a) without PDA and (b) with 600^oC PDA for various surface treatments under a CVS of -3.8V.

w/o Treatment NH3 RTO Ozone

w/o Treatment NH3 RTO Ozone Maximun ∆Gpeak (µS)

Fig. 4-8 Comparison of (a) the initial conductance peak value and (b) the change of the conductance peak value after CVS for several surface treatments.

(a)

(b)

Fig. 4-9 The HRTEM cross-sectional images of Ozone-treated HfO2 dielectric (a) without PDA and (b) with 600^oC PDA.

w/o PDA Samples CVS -3.8V

Injected Charges (C/cm²)

10^-3 10^-2 10^-1

Injected Charges (C/cm²)

10^-3 10^-2 10^-1

dielectric (a) without PDA and (b) with 600^oC PDA under a CVS of -3.8V.

NH3 RTO Ozone Defect Generation Rate (C/cm2 )

0 5 10 15 20 25

w/o PDA PDA 600^oC

Fig. 4-11 Comparison of the defect generation rates between several surface treatments.

Ozone Samples

Fig. 4-12 The SILC characteristics of Ozone-treated dielectric (a) without PDA and (b) with 600^oC PDA under a CVS of -3.8V.

Ozone + PDA 600^oC Samples

Fig. 4-13 The Schottky emission fitting in the low field range (<3.5 MV/cm) for Ozone-treated dielectric with 600^oC PDA.

Al HfO

₂ ^SiO2

p-Si

Fig. 4-14 The band diagram of Al/HfO2/SiO2/Si capacitor simulated the low electrical field injection condition.

F-N Plot Gate Injection Ozone + PDA 600^oC Samples

1/E (cm/MV)

0.14 0.16 0.18 0.20 0.22 0.24 0.26 0.28 ln (J/E2 )

Fig. 4-15 The Fowler-Nordheim (F-N) tunneling fitting in the high field range (>3.5 MV/cm) for Ozone with PDA 600^oC samples.

Al HfO

₂ ^SiO2

p-Si

Fig. 4-16 The band diagram of Al/HfO2/SiO2/Si capacitor simulated the high electrical field injection condition.

Gate Voltage (V)

-5 -4 -3 -2 -1

Current (A)

10

^-14

10

^-13

10

^-12

10

^-11

10

^-10

10

^-9

10

^-8

10

^-7

Ig Ids Ib

25^oc

125^oc

Fig. 4-17 Carrier separation in the temperature dependence measurement [Ref. 64].

CHAPTER 5

Conclusions and Recommendations for Future Works

5.1 Conclusions

Firstly, the effects of O3 post deposition annealing temperature on the properties of Ta2O5 were investigated by COCOS non-contact metrology. The dielectric thickness was increased as raising annealing temperature, which could be ascribed to the thick interfacial layer (IL) growth. A lower κ-value interfacial layer in series would reduce the dielectric capacitance after high temperature annealing. Moreover, the flat band voltage shift changed from positive to negative due to the electron traps elimination and partially hole traps generation in the film. It had been supposed that high temperature ozone annealing could compensate the dangling bond at the interface of Si/Ta2O5 proceed to minimize the interface trap density and improve the uniformity. Non-uniform interfacial layer oxidation after O3

annealing was supposed to cause the increasing of the field strength and break the the soft breakdown distribution.

The basic properties of the ozone oxide were studied first in chapter 3. The growth rate of ozone oxide was increased as raising the ozone quantity contained in DI water. A saturated oxidation was observed in the growth curves and the resultant self-limiting property could improve the thickness uniformity after furnace or/and rapid thermal oxidation. The formation of a more homogeneous structure at the Si/ozone oxide interface performed a higher etching rate for the denser transition layer. Ozone oxide could improve Si surface roughness by 41%, which was beneficial to suppress the leakage current density of the stacked gate dielectric.

Then the influences of surface treatment prior to HfO2 gate dielectric deposition were investigated. Significantly large fixed charges and hysteresis of NH3 nitridation would degrade device performance. Albeit RTO treatment exhibited comparable leakage current with Ozone treatment, the time-to-breakdown value was still also less than Ozone treatment. As a result, sample with Ozone treatment revealed small leakage current, negligible hysteresis and excellent dielectric reliability, which was considered to be one of the most potential alternative to improve the interface properties between high-κ dielectrics and silicon surface.

Finally, the surface treatment effects on the charge trapping characteristics the HfO2

gate dielectric were researched in terms of trapping efficiency, conductance peak shift, and SILC defect generation. Ozone oxide performed the lowest trapping efficiency, Dit

degradation and defect generation rate after 600^oC PDA than NH3 or RTO treatment partially due to the better interface properties. However, Ozone-samples without PDA expressed poor results, which might be caused by the incomplete oxidation and rougher interface owing to the low growth temperature. The low Dit generation and Pg value of NH3-treated dielectric was ascribed to the strong Si−N bonding at the Si/dielectric interface against the defects creation.

Unfortunately, higher interface charges for as-deposited NH3-treated dielectric would limit nitridation application. RTO also exhibited a poor defect generation resistance than Ozone-treated dielectric. The current transport mechanism was also investigated. When Eeff<3.5 MV/cm, the corresponding current transport mechanism was Schottky emission under gate injection conditions. F-N tunneling dominated the conduction mechanism during 6>Eeff>3.5 MV/cm.

5.2 Recommendations for Future Works

1. More HRTEM images to evidence thickness variation and interfacial layer reaction.

2. More physical analysis to understand the properties of the ozone oxide.

3. Fully fabricated MOSFET with high-κ dielectrics and various surface treatment to study the device characteristics.

References

[1] R. H. Dennard, “Field–Effect Transistor Memory,” U.S. Patent 3,387,286 (1968)

[2] E. Adler, J. K. DeBrosse, S. F. Geissler, S. J. Holmes, M. D. Jaffe, J. B. Johnson, C. W.

Koburger III, J. B. Lasky, B. Lloyd, G. L. Miles, J. S. Nakos, W. P. Noble, Jr., S. H.

Voldman, M. Armacost, and R. Ferguson, “The evolution of IBM CMOS DRAM technology,” IBM J. Res. & Dev., vol. 39, p. 167 (1995)

[3] International Technology Roadmap for Semiconductor, Semiconductor Industry Association (2004)

[4] Y. C. Yeo, T. J. King, and C. Hu, “Direct tunneling leakage current and scalability of alternative gate dielectrics,” Appl. Phys. Lett., vol. 81, no. 11, p. 2091 (2002)

[5] D. A. Buchanan, E. P. Gusev, E. Cartier, H. Okorn Schmidt, K. Rim, M. A. Gribelyuk, A. Mocuta, A. Ajmera, M. Copel, S. Guha, N. Bojarczuk, A. Callegari, C. D’Emic, P.

Kozlowski, K. Chan, R. J. Fleming, P. C. Jamison, J. Brown, and R. Amdt, “80nm poly–silicon gated n–FETs with ultra–thin Al2O3 gate dielectric for ULSI applications,”

IEDM Tech. Dig., p. 223 (2000)

[6] S. J. Ding, H. Hu, C. Zhu, M. F. Li, S. J. Kim, B. J. Cho, D. S. H. Chan, M. B. Yu, A. T.

Du, A. Chin, and D. L. Kwong, “Evidence and understanding of ALD HfO2–Al2O3

laminate MIM capacitors outperforming sandwich counterparts,” IEEE Electron Device Lett., vol. 24, no. 10, p. 681 (2004)

[7] J. C. Wang, S. H. Chiao, C. L. Lee, T. F. Lei, Y. M. Lin, M. F. Wang, S. C. Chen, C. H.

Yu, and M. S. Liang, “A physical model for the hysteresis phenomenon of the ultrathin ZrO2 film,” J. Appl. Phys., vol. 92, no. 7, p. 3936 (2002)

[8] B. Tavel, X. Garros, T. Skotnicki, F. Martin, C. Leroux, D. Bensahel, M. N. Séméria, Y.

Morand, J. F. Damlencourt, S. Descombes, F. Leverd, Y. Le Friec, P. Leduc, M. Rivoire, S. Jullian, and R. Pantel, “High performance 40nm nMOSFETs with HfO2 gate dielectric and polysilicon damascene gate,” IEDM Tech. Dig., p. 429 (2002)

[9] H. Sunami, T. Kure, N. Hashimoto, K. Itoh, T. Toyabe, and S. Asai, “A corrugated capacitor cell (CCC) for megabit dynamic MOS memories,” IEDM Tech. Dig., p. 806 (1982)

[10] H. Kang, K. Kim, Y. Shin, I. Park, K. Ko, C. Kim, K. Oh, S. Kim, C. Hong, K. Kwon, J.

Yoo, Y. Kim, C. Lee, W. Paick, D. Suh, C. Park, S. Lee, S. Ahn, C. Hwang, and M. Lee,

“Highly manufacturable process technology for reliable 256Mbit and 1Gbit DRAMs,”

IEDM Tech. Dig., p. 635 (1994)

[11] G. Bronner, H. Aochi, M. Gall, J. Gambino, S. Gernhardt, E. Hammerl, H. Ho, J. Iba, H.

Ishiuchi, M. Jaso, R. Kleinhenz, T. Mii, M. Narita, L. Nesbit, W. Neumueller, A.

Nitayama, T. Ohiwa, S. Parke, J. Ryan, T. Sato, H. Takato, and S. Yoshikawa, “A fully planarized 0.25µm CMOS technology for 256Mbit DRAM and beyond,” VLSI Tech.

Symp. Dig., p. 15 (1995)

[12] M. T. Bohr, “Technology development strategies for the 21st century,” Appl. Surf. Sci., vol. 100–101, p. 534 (1996)

[13] Y. Taur, D. Buchanan, W. Chen, D. J. Frank, K. I. Ismail, S. H. Lo, G. A. Sai Halasz, R.

G. Viswanathan, H. J. C. Wann, S. J. Wind, and H. S. Wong, “CMOS scaling into the nanometer regime,” Proc. IEEE, vol. 85, no. 4, p. 486 (1997)

[14] K. J. Hubbard, and D. G. Schlom, “Thermodynamic stability of binary oxides in contact with silicon,” J. Mater. Res., vol. 11, no. 11, p. 2757 (1996)

[15] M. Balog, M. Schieber, M. Michman, and S. Patai, “Chemical vapor deposition and characterization of HfO2 films from organo–hafnium compounds,” Thin Solid Films, vol.

41, p. 247 (1977)

[16] T. Aoyama, S. Saida, Y. Okayama, M. Fujisaki, K. Imai, and T. Arkado, “Leakage current mechanism of amorphous and crystalline Ta2O5 films grown by chemical vapor deposition,” J. Electrichem. Soc., vol. 143, no.3, p. 977 (1996)

[17] E. Atanassova, A. Paskaleva, N. Novkovski, and M. Georgieva, “Conduction mechanisms and reliability of thermal Ta2O5–Si structures and the effect of the gate electrode,” J. Appl. Phys., vol. 97, 094104 (2005)

[18] C. Isobe, and M. Saitoh, “Effect of ozone annealing on the dielectric properties of tantalum oxide thin films grown by chemical vapor deposition,” Appl. Phys. Lett., vol.

56, no. 10, p. 907 (1990)

[19] B. H. Lee, L. Kang, W. J. Qi, R. Nieh, Y. Jeon, K. Onishi, and J. C. Lee, “Ultrathin hafnium oxide with low leakage and excellent reliability for alternative gate dielectric application,” IEDM Tech. Dig., p. 133 (1999)

[20] S. J. Lee, H. F. Luan, T. S. Jeon, W. P. Bai, Y. Senzaki, D. Roberts, and D. L. Kwong,

“Performance and reliability of ultra thin CVD HfO2 gate dielectrics with dual poly–Si gate electrodes,” VLSI Tech. Symp. Dig., p. 133 (2001)

[21] H. Y. Yu, J. F. Kang, J. D. Chen, C. Ren, Y. T. Hou, S. J. Whang, M. F. Li, D. S. H.

Chan, K. L. Bera, C. H. Tung, A. Du, and D. L. Kwong, “Thermally robust high quality

HfN/HfO2 gate stack for advanced CMOS devices,” IEDM Tech. Dig., p. 99 (2003) [22] S. B. Samavedam, L. B. La, J. Smith, S. Dakshina Murthy, E. Luckowski, J. Schaeffer,

M. Zavala, R. Martin, V. Dhandapani, D. Triyoso, H. H. Tseng, P. J. Tobin, D. C.

Gilmer, C. Hobbs, W. J. Taylor, J. M. Grant, R. I. Hegde, J. Mogab, C. Thomas, P.

Abramowitz, M. Moosa, J. Conner, J. Jiang, V. Arunachalam, M. Sadd, Y. Nguyen, and B. White, “Dual–metal gate CMOS with HfO2 gate dielectric,” IEDM Tech. Dig., p. 433 (2002)

[23] C. H. Wang, R. D. Lin, S. F. Chen, and W. K. Lin, “Effects of O2 rapid thermal annealing on the microstuctural properties and reliablilty of RF–sputtered Ta2O5 films,”

IEEE Trans. on Dielectrics and Electrical Insulation, vol. 7, no. 3, p. 316 (2000)

[24] A. Paskaleva, E. Atanassova, and T. Dimitrova, “Leakage currents and conduction mechanisms of Ta2O5 layers on Si obtained by RF sputtering,” Vacuum, vol. 58, p. 470 (2000)

[25] J. Y. Kim, M. C. Nielsen, E. J. Rymaszewski, and T. M. Lu, “Electrical Characteristics of thin Ta2O5 films deposited by reactive pulsed direct–current magnetron sputtering,” J.

Appl. Phys., vol. 83, no. 3, p. 1448 (2000)

[26] S. Seki, T. Unagami, and O. Kogure, “Effects of suface oxide on leaksge current of magnetron sputtered Ta2O5 on Si,” J. Electrichem. Soc., vol. 132, no. 12, p. 3054 (1985) [27] K. S. Park, D. Y. Lee, K. J. Kim, and D. W. Moon, “Growth and characterization of

Ta2O5 thin films on Si by ion beam,” Thin Solid Films, vol. 281, p. 419 (1996)

[28] S. Boughaba, M. Islam, J. P. McCaffrey, G. I. Sproule, and M. J. Graham, “Ultrathin Ta2O5 films produced by large–area pulsed laser deposition,” Thin Solid Films, vol. 371, p. 119 (2000)

[29] H. Ono, and K. I. Koyanagi, “Infrared absorption peak dou to Ta–O bonds in Ta2O5 thin films,” Appl. Phys. Lett., vol. 77, no. 10, p. 1431 (2000)

[30] H. Shinriki, M. Sugiura, and K. Shimomure, “Ethanol–addition–enhanced, chemical vapor deposited tantalum oxide films from Ta(OC2H5)5 and oxygen precursors,” J.

Electrichem. Soc., vol. 145, no. 9, p. 3247 (1998)

[31] I. W. Boyd, and J. Y. Zhang, “Low temperature photoformation of tantalum oxide,”

Microelectronics Reliability, vol. 40, p. 649 (2000)

[32] G. Guiu, and P. Grange, “Synthesis and characterization of Ta2O5–SiO2 mixed oxides,”

Bull. Chem. Soc. Jpn., vol. 67, no. 10, p. 2716 (1994)

[33] S. Duenas, H. Castan, J. Barbolla, R. R. Kola, and P. A. Sullivan, “Electrical

characteristics of anode tantalum pentoxide thin films under thermal stress,”

Microelectronics Reliability, vol. 40, p. 659 (2000)

[34] H. Shinriki, and M. Nakata, “UV-O and dry-O : Two-step-annealed chemical vapor-deposited Ta O films for storage dielectrics of 64-Mb DRAMs,”

3 2

2 5 IEEE Trans.

Electron Devices, vol. 38, p. 455(1991)

[35] S. R. Jeon, S. W. Han, and J. W. Park, “Effect of rapid thermal annealing treatment on electrical properties and microstructure of tantalum oxide thin film deposited by plasma-enhanced chemical vapor deposition,” J. Appl. Phys., vol. 77, p. 5978 (1995) [36] Prakash A. Murawala, Mikio Sawai, Toshiaki Tatsuta, Osamu Tsuji, Shizuo Fujita, and

Shigeo Fujita, “Structural and electrical properties of Ta2O5 grown by the plasma-enhanced siquid Source CVD using penta ethoxy tantalum source,” Jpn. J. Appl.

Phys., vol. 32, p. 368 (1993)

[37] FAaST^TM 230 Operations, SDI (1998)

[38] Marshall Wilson, Jacek Lagowski, Lubek Jastrzebski, Alexandre Savtchouk, and Vladimir Faifer, “COCOS (corona oxide characterization of semiconductor) non-contact metrology for gate dielectrics,” NIST Conference on Characterization and Metrology for ULSI Technology (2000)

[39] Y. Ohji, Y. Matsui, T. Ttoga, M. Hirayama, Y. Sugawara, K. Torii, H. Miki, M. Nakata, I. Asano, S. Iijima, and Y. Kawamoto, “Ta O capacitors' dielectric material for giga-bit DRAMs,”

2 5

IEDM Tech. Dig., p. 111 (1995)

[40] H. Shinriki, M. Hiratami, A. Nakano, and S. Tachi, 23rd Conf. Solid State Devices and Materials, p. 198 (1991)

[41] Laegu Kang, Katsunori, and Jack C. Lee, “MOSFET devices with polysilicon on single-layer HfO2 high-κ dielectrics,” IEDM Tech. Dig., p. 35 (2000)

[42] C. Hobbs, H. Tseng, and P. Tobin, “80 nm Poly-Si gate CMOS with HfO2 gate dielectric,” IEDM Tech. Dig., p. 651 (2001)

[43] C.H. Lee, Y.H. Kim, and D.L. Kwong, “MOS devices with high quality ultra thin CVD ZrO2 gate dielectrics and self-aligned TaN and TaN/Poly-Si gate electrodes,” VLSI Tech.

Symp. Dig., p. 137 (2001)

[44] G.D. Wilk, R.M. Wallace, and J.M. Anthony, “High-κ gate dielectrics: current status and materials properties considerations,” J. Appl. Phys., vol. 89, no. 10, p. 5243 (2001) [45] A. Callegari, E. Cartier, M. Gribelyuk, H. F. Okorn-Schmidt, and T. Zabel, “Physical

and electrical characterization of hafnium oxide and hafnium silicate sputtered films,” J.

Appl. Phys., vol. 90, no. 12, p. 6466 (2001)

[46] E. P. Guseri, D. A. Buchanani, and E. Cartier, “Ultra thin high-κ gate stacks for advanced CMOS devices,” IEDM Tech. Dig., p.451 (2001)

[47] D. Buchanan, “80 nm poly-silicon gated n-FETs with ultra-thin Al2O3 gate dielectric for ULSI applications,” IEDM Tech. Dig., p. 223 (2000)

[48] K. Nakamura, A. Kurokawa, and S. Ichimura, “Hydrofluoric acid etching of ultra thin silicon oxide film fabricated by high purity ozone,” Thin Solid Films, vol. 343/344, p.

361 (1999)

[49] T. Nishiguchi, H. Nonaka, and S. Ichimura, “High-quality SiO2 film formation by highly concentrated ozone gas at below 600°C,” Appl. Phys. Lett., vol. 81, p. 2190 (2002) [50] K. Nakamura, S. Ichimura, A. Kurokawa, K. Koike, G. Inoue, and T. Fukuda,

“Ultrathin silicon oxide film on Si(100) fabricated by highly concentrated ozone at atmospheric pressure,” J. Vac. Sci. Technol. A, vol. 17, p. 1275 (1999)

[51] Hyo Sik Chang, Sangmoo Choi, Dae Won Moon, and Hyunsang Hwang, “Improved Reliability Characteristics of Ultrathin SiO2 Grown by Low Temperature Ozone Oxidation,” Jpn. J. Appl. Phys., vol. 41, no. 10, p. 5971 (2002)

[52] Katsunori Onishi, Chang Seok Kang, Rino Choi, Hag-Ju Cho, Sundar Gopalan, Renee E.

Nieh, Siddharth A. Krishnan, and Jack C. Lee, “Improvement of surface carrier mobility of HfO2 MOSFETs by high-temperature forming gas annealing,” IEEE Trans. Electron Devices, vol. 50, p. 384 (2003)

[53] I. Kingon, J. P. Maria, and S. K. Streiffer, “Alternative dielectrics to silicon dioxide for memory and logic devices,” Nature, vol. 406, p. 1032 (2000)

[54] E. Atanassova, and T. Dimitrova, in Handbook of Surfaces and Interfaces of Materials, edited by H. S. Nalwa, vol. 4, p. 439 (2001)

[55] MRS Bull. 27 (2002)

[56] E. H. Nicolian, and J. R. Brews, “MOS Physics and Technology,” (Wiley, New York) (1982)

[57] J. Maserjian, and N. Zamani, “Observation of positively charged state generation near the Si/SiO2 interface during Fowler-Nordheim tunneling,” J. Vac. Sci. Technol., vol.

20, no. 3, p. 743 (1982)

[58] T. N. Nguyen, P. Olivo, and B. Ricco, “A new failure mode of very thin (<50w) thermal SiO2 films,” Proceedings of the International Reliability Physics Symposium, p. 66

(1987)

[59] R. Moazzami, and C. Hu, “Stress-induced current in thin silicon dioxide films,” IEDM Tech. Dig., p.139 (1992)

[60] D. J. DiMaria, and E. Cartier, “Mechanism for stress-induced leakage currents in thin silicon dioxide films,” J. Appl. Phys., vol. 78, no. 6, p. 3883 (1995)

[61] J. H. Stathis, and D. J. DiMaria, “Reliability projection for ultra-thin oxides at low voltage,” IEDM Tech. Dig., p. 167 (1998)

[62] Paul E. Nicollian, Mark Rodder, Douglas T. Grider, Peijun Chen, Robert M. Wallace, and Sunil V. Hattangady, “Low voltage stress-induced-leakage-current in ultrathin gate oxides,” IEEE 37th Annual International Reliability Physics Symposium, p. 400 (1999) [63] W. J. Zhu, T. P. Ma, S. Zafar, and T. Tamagawa, “Charge trapping in ultrathin hafnium

oxide,” IEEE Electron Device Lett., vol. 23, no. 10, p. 597 (2002)

[64] 李 聰 杰 , “Electrical characteristics of pMOSFETs HfO2/SiON gate stacks after post-N2O plasma nitridation ,” 交通大學碩士論文 (2005)

Vita

姓 名 : 張祐慈 性 別 : 女

出生日期 : 民國 68 年 10 月 19 日 籍 貫 : 台灣省苗栗縣

住 址 : 苗栗縣苗栗市北苗里蕉嶺街 17 巷 12 號 2F 學 歷 :

中原大學電子工程學系學士 (88.9–92.6) 國立交通大學電子工程研究所碩士 (92.9–94.6)

論文題目 :

高介電常數介電層在金氧半元件及動態隨機存取記憶體上之特性研究 Investigation of High-κ Dielectrics on MOS Devices and DRAM

發表論文 :

Shih-Chang Chen, Yung-Yu Chen, Yu-Tzu Chang, “Effects of Surface Treatments on the HfO2

Gate Dielectric Characteristics,” The 12th Symposium on Nano Device Technology (SNDT 2005), NDL, May 4-5, Hsinchu, Taiwan, ROC, 2005

在文檔中 高介電常數介電層在金氧半元件及動態隨機存取記憶體上之特性研究 (頁 75-0)