CHAPTER 3 Ozone Surface Treatment on the Characteristics and Reliabilities of
3.3.2 Comparison of Surface Treatments Prior to HfO 2 Deposition with PDA Effect
Figure 3-10 showed the normalized capacitance-voltage (C-V) characteristics of HfO2
stacked gate dielectrics with various surface treatments for samples (a) without PDA and (b) with 600oC PDA. Post deposition annealing could reduce the interface trap density exhibited by less kink and more sharp C-V characteristics. Apparent C-V deterioration was observed in NH3-treated sample due to the excess nitrogen concentration compels more Si bonding constraints at the interface [52]. The C-V curve of Ozone-treated capacitors was kink free and exhibited good interface properties.
High-κ dielectric densification and interfacial oxidation mechanism were competed during high temperature annealing process which caused the little variations in equivalent oxide thickness (EOT) showed in Fig. 3-11. Ozone treatment slightly increased the EOT after 600oC PDA supposed to the incomplete oxidation in bulk ozone oxide owing to the low growth temperature.
The hysteresis of various surface treatments was compared in Fig. 3-12. The hysteresis
voltage was defined as the flat band voltage difference between the forward and backward swept C-V curves, which might be contributed from the trapped charges within high-κ bulk or interface. The samples without surface treatment revealed large hysteresis; even subsequently high temperature annealing would reduce C-V hysteresis. Similarly, NH3 nitridation also exhibited large hysteresis, regardless of the high temperature annealing. Fortunately, surface oxidation resulted in excellent hysteresis behavior, for both RTO and Ozone treatment.
Moreover, Ozone-treated sample exhibited almost hysteresis-free characteristics.
Figure 3-13 presented the dependence of VFB shift on surface treatment with and without PDA. NH3 nitridation exhibited large negative VFB shift compared to sample without treatment indicated positive charges accumulation after surface nitridation. After 600oC PDA, NH3-treated sample showed obvious VFB recovery due to interfacial N exchanged by O from annealing ambient. On the other hand, RTO- and Ozone-treated samples possessed less VFB
shift than NH3 nitridation which demonstrated superior interface than NH3-treated sample.
Negative VFB shift of Ozone-treated sample after PDA may indicate the increment of positive charges, which should be further investigated.
Leakage current density of HfO2 stacked gate dielectrics with various surface treatments as a function of effective electric field (Eeff) for samples (a) without PDA and (b) with 600oC PDA were demonstrates in Fig. 3-14. Both RTO and Ozone treatment could suppress the leakage current than sample without surface treatment, partially due to smoother interface roughness. As indicated in Fig. 3-15(a) for samples without PDA, surface treatments could lower the leakage current density at 6 MV/cm at least two orders. Figure 3-15(b) revealed that a suitable PDA can further improve the dielectric properties.
Synthesized above mentioned in Fig. 3-16, PDA and surface treatment could reduced current density at least 2 orders of magnitude with smaller than 3Å EOT increment. The calculated effective dielectric constant as a function of surface treatments was ranging from 8
to13, as observed in Fig. 3-17.
The time-zero dielectric breakdown (TZDB) and the time-dependent dielectric breakdown (TDDB) reliability investigation were shown in Figs. 3-18 and 3-19, respectively.
Surface treatments prior to high-κ dielectrics deposition and PDA can promote the reliability.
Sample without surface treatment was supposed to have poor interface between HfO2/Si, which will degrade the dielectric reliability. After surface treatments, the interface quality was improved, and the reliability therefore became superior. The ozone oxide treatment also revealed comparable results with RTO even under higher stressing voltage.
3.4 Summary
In this chapter, the basic properties of the ozone oxide were studied first. The growth rate of ozone oxide was increased as raising the ozone quantity contained in DI water. A saturated oxidation was observed in the growth curves and the resultant self-limiting property could improve the thickness uniformity after furnace or/and rapid thermal oxidation. The formation of a more homogeneous structure at the Si/ozone oxide interface performed a higher etching rate for the denser transition layer. Ozone oxide could improve Si surface roughness by 41%, which was beneficial to suppress the leakage current density of the stacked gate dielectric.
Then the influences of surface treatment prior to HfO2 gate dielectric deposition were investigated. Significantly large fixed charges and hysteresis of NH3 nitridation would degrade device performance. Albeit RTO treatment exhibited comparable leakage current with Ozone treatment, the time-to-breakdown value was still also less than Ozone treatment. As a result, sample with Ozone treatment revealed small leakage current, negligible hysteresis and
excellent dielectric reliability, which was considered to be one of the most potential alternative to improve the interface properties between high-κ dielectrics and silicon surface.
O2
N2
Buffer Tank
O3
Generator Dissolve Unit
PUMP O3
Destructor
O3 Analyzer Orbisphere
-3600
UV Lamp Tank
Bench DI Water
O3 Water
PUMP O3 Gas
O3 Water
Waste Water
Fig. 3-1 Schematic diagram of ozone oxide growth system.
Fig. 3-2 Schematic diagram of MOCVD system structure.
P P ro r oc ce es ss s F Fl lo ow w
RCA Clean with HF-last1. w/o Treatment
Al gate & backside contact formation by Thermal Evaporation System
Si
Fig. 3-3 HfO2 MOS devices process flow, device cross section and split conditions.
Growth Time (min)
0 1 2 3 4 5
Ozone Oxide Thickness (A)
0
Fig. 3-4 The growth curves of ozone oxide as a function of ozone water concentration.
HF:H2O=1:500
Fig. 3-5 Comparison the etching rate of ozone oxide at HF: H2O=1:500 to chemical oxide formed by RCA clean without HF-last.
(a) Bare-Si Roughness RMS Average =1.98 Å
(b) NH3 Nitridation Roughness RMS Average =1.85 Å
(c) HF-dipped Roughness RMS Average =1.81 Å
Fig. 3-6 AFM results of NH3 treatment for Si surface roughness improvement.
(a) Bare-Si Roughness RMS Average =2.13 Å
(b) RTO Roughness RMS Average =1.47 Å
(c) HF-dipped Roughness RMS Average =1.92 Å
Fig. 3-7 AFM results of RTO treatment for Si surface roughness improvement.
(a) Bare-Si Roughness RMS Average =1.37 Å
(b) Ozone oxide Roughness RMS Average =1.09 Å
(c) HF-dipped Roughness RMS Average =0.79 Å
Fig. 3-8 AFM results of ozone oxide treatment for Si surface roughness improvement.
NH3 RTO Ozone
Si Surface Roughness Improvement (%)
0 10 20 30 40 50
41.83%
8.60% 9.87%
Fig. 3-9 Comparison of the Si surface roughness improvement for three kinds of surface treatments.
w/o PDA Samples
PDA 600oC Samples
Gate Volatge (V)
Fig. 3-10 Normalized C-V characteristics of HfO2 stacked gate dielectrics with various surface treatments (a) without PDA and (b) with 600oC PDA.
w/o PDA Samples
PDA 600oC Samples
EOT(A)
Fig. 3-11 EOT Weibull distributions for samples (a) without PDA and (b) with 600oC PDA.
w/o Treatment NH3 RTO Ozone
Fig. 3-12 Hysteresis comparison between several surface treatments.
Extrated by CVC Program
w/o Treatment NH3 RTO Ozone
Flat Band Volatage ( V )
Fig. 3-13 Flat-band voltage variation as a function of surface treatments.
w/o PDA Samples
Effective Electric Field (MV/cm )
0 5 10 15 20 25
PDA 600oC Samples
Effective Electric Field (MV/cm )
0 5 10 15 20 25
Fig. 3-14 Leakage current density of HfO2 stacked gate dielectrics with various surface treatments as a function of effective electric field (a) without PDA and (b) with 600oC PDA.
w/o PDA Samples
PDA 600oC Samples
Current Density @ 6 MV/cm (A/cm2)
Fig. 3-15 Leakage current density Weibull distributions at 6 MV/cm for samples (a) without PDA and (b) with 600oC PDA.
w/o Treatment NH3 RTO Ozone
Current Density @ 6 MV/cm (A/cm2 ) 10-16
Fig. 3-16 Assembled the EOT and leakage current density at 6 MV/cm performances for different surface treatments.
w/o Treatment NH3 RTO Ozone
Effective Dielectric Constant
Fig. 3-17 Effective dielectric constant variation as a function of surface treatments.
w/o PDA Samples
PDA 600oC Samples
Effective Breakdown Field (MV/cm)
Fig. 3-18 TZDB reliabilities for samples (a) without PDA and (b) with 600oC PDA.
w/o PDA Samples
PDA 600oC Samples TDDB Weibull plots
Fig. 3-19 TDDB reliabilities for samples (a) without PDA and (b) with 600oC PDA.
CHAPTER 4
Trapping Characteristics and Current Transport Mechanism of the HfO
2Gate Dielectric
4.1 Introduction
According to the International Technology Roadmap for Semiconductors (ITRS), the further miniaturization of the integrated circuits in gigascale technology requires the use of high dielectric constants (high-κ) materials as charge storage insulators as well as alternative gate dielectrics in metal-oxide-semiconductor field-effect transistors (MOSFETs) [3].
Consequently, the high-κ oxides have been extensively studied to overcome the problems associated with the extremely thin conventional thermal SiO2. For example, these materials have to be introduced in integrated circuits to satisfy the increasing demands of the high-density capacitors for dynamic random access memory (DRAM) applications [54]-[55].
Recently many efforts have been devoted to understand the electrical properties including defects produced under various treatments of MOS structures with high permittivity insulators.
Very little is known about the reliability of the high-κ dielectrics. The degradation of the insulator in MOS devices is one of the most important issues for the ultralarge-scale integrated circuits and the reliability characteristics are greatly influenced by the bulk and interface traps. The problem with the high-κ dielectrics is that very often these traps exist in unacceptably high levels due to a nonstoichiometric composition and/or microstructure imperfections which usually are present in the as-fabricated films. These defects act as traps for the charge carriers injected into or generated in the dielectric. In order to meet the future
needs of the high-κ dielectrics reliability, a physical understanding of the conduction and degradation mechanisms is required for these materials. In this chapter, the surface treatment effects on the charge trapping characteristics and current transport mechanism of the HfO2
gate dielectric were studied.
4.2 Experiment Details
Mainly, the samples measured in this chapter were the same with those in chapter 3.
LOCOS isolated MOS capacitors were fabricated on 6 inch p-type (100) silicon wafers. After forming LOCOS isolation, wafers were cleaned by standard RCA processes with HF-last.
Prior to high-κ dielectrics deposition, the samples were prepared either by Ozone, NH3 or RTO. Diluted ozone water (2ppm) was used to grow an ultra-thin ozone oxide about 7~8Å (measured by ellipsometer). NH3 nitridation was performed in a high temperature furnace at 800oC for 1 hour to generate an ultra-thin oxynitride layer (~7Å). RTO was also intended to deposit a thin SiO2 layer (~8Å), at 800oC using a rapid thermal process system for 30 seconds.
After one of the surface treatments, 50Å HfO2 was then deposited at 500oC by MOCVD system, followed by a high temperature post deposition annealing (PDA) at 600oC in the nitrogen ambient for 30 seconds. Aluminum metal served as the gate electrode was created by a thermal evaporation system. After gate electrodes patterned and contact holes etched, backside contact was formed. Square capacitors of 1×10-4 cm2 areas with LOCOS isolation are used to evaluate the gate oxide integrity.
Hewlett-Packard (HP) 4284 LCR meter was utilized for capacitance-voltage (C-V) and conductance-voltage (G-V) data obtained. UCLA CVC simulation program was utilized to obtain the accurate flat band voltage (VFB). The tunneling leakage current density-electric
field (J-E) and the reliability characteristics of MOS capacitors were measured by semiconductor parameter analyzer HP 4156C. The temperature dependence of the gate leakage current was studied to understand the current transport mechanisms. The leakage currents were measured from 25oC to 150oC for gate electron injection (negative VG).
4.3 Results and Discussions
In this chapter, the surface treatment effects on the charge trapping characteristics the HfO2 gate dielectric were studied in terms of trapping efficiency, conductance peak shift, and SILC defect generation. The current transport mechanism was also investigated.
4.3.1 Surface Treatment Effects on the Charge Trapping Characteristics of HfO2 Dielectrics
4.3.1.1 Trapping Efficiency Characteristics
Figure 4-1 depicted the effects of surface treatment on transient charge trapping behaviors of HfO2 dielectrics with and without PDA under a constant voltage stress (CVS) of -3.8V. The decrease in the absolute gate current was obviously coming from hole trapping behavior. Figure 4-2 was the corresponding flat band voltage shift toward negative direction due to the positive charges trapped, i.e. hole trapping after stress. For going to details about reliability phenomenon, Fig. 4-3 demonstrated trapped charges under CVS with various injection charges and the slop was defined as the trapping efficiency (showed in Fig. 4-4) used to compare the dielectric quality.
In order to obtain low trapping efficiency, dielectrics with low bulk and interface trap
density should be deposited. However, the sample without surface treatment and PDA was not shown here because of significant degradation after CVS. Even though post deposition annealing could improve the dielectric quality, the trapping efficiency was still not as good as the samples with surface treatments. Ozone oxide exhibited the lowest trapping efficiency after 600oC PDA than NH3 or RTO treatment partially due to the better interface properties.
On the other hand, the inferior trapping characteristics of Ozone-samples without PDA might be caused by the incomplete oxidation owing to the low growth temperature, which could be evidenced on lower etching rate shown in Fig. 3-5.
The corresponding band diagram including the two leakage current components under CVS condition was drawn in Fig. 4-5. Hole current from substrate was considered to be the dominant terms owing to the negative VFB shift and the decreasing of absolute gate current which consisted with that the interface layer quality influence the carriers injection.
4.3.1.2 Interface Trap Properties Information from Conductance Measurements
The conductance-voltage (G-V) measurement [56] is a useful and sensitive tool for investigating interface characters between Si and dielectrics. In the conductance method, interface trap levels are detected through the energy loss resulting from changes in interface traps occupancy produced by small variation of gate voltage. The small-signal equivalent parallel conductance of MOS capacitor Gp displays different behavior depending on the dominant loss mechanism. For a chosen ac frequency, vary the gate bias from accumulation to midgap. In accumulation, majority carrier density is very large near the Si/dielectric interface, so those interface trap capture rates are very rapid compared to the ac frequency. Interface trap levels respond immediately to the ac voltage, and no loss occurs. In depletion, majority carrier density at the Si/dielectric interface is reduced. Capture rates slow down, and interface
trap levels cannot keep in phase with the ac voltage. A loss therefore occurs. Still further in depletion, near midgap, majority carrier density becomes insufficient that almost no carriers are exchanged between interface trap levels and the silicon. Hence the loss is also low. In short, interface trap loss goes through a peak as a function of gate bias. Maximum loss occurs for the gate bias where majority carrier density makes the interface trap capture rate compare to the ac frequency.
Figure 4-6 illustrated the C-V and G-V curves variation after CVS for Ozone-treated samples with and without PDA. The conductance peak shift and the value increase were corresponding to the flat band voltage shift and the degraded Dit, respectively. Figure 4-7 compared the variation of conductance peak value after CVS for several surface treatments.
Two components should be noted: first is the initial conductance peak value and the second one is the change of the conductance peak value after CVS. Figure 4-8(a) compared the initial conductance peak values corresponding to the initial amount of Dit for various surface treatments. The sample without surface treatment and PDA was not shown because of the dielectric degradation after CVS. Post deposition annealing could reduce the conductance peak value as well as the interface trap density. NH3 nitridation exhibited large conductance peak value compared to sample without treatment indicated higher interface charges after surface nitridation. Ozone oxide performed the lowest Dit values than NH3 or RTO treatment due to the better interface properties.
The comparison of the peak value change after CVS was displayed in Fig. 4-8(b). Both surface treatments and PDA could suppress the Dit generation. However, Ozone-samples without PDA expressed poor results might cause by the rougher interface than 600oC PDA samples shown in the HRTEM cross-sectional images in Fig.4-9.
4.3.1.3 SILC Reliabilities and Defect Generation Rate Properties
Stress-Induced-Leakage-Current (SILC) is an increase in gate oxide leakage current resulting from the application of a stress voltage or current [57]-[60]. It is an important concern in scaling gate oxide thickness because it can decrease DRAM refresh times, degrade EEPROM data retention, and increase MOSFET off-state power dissipation. During constant negative voltage stress, hole current from the substrate was injected through the interfacial layer and HfO2 gate dielectric of the MOS capacitor. Then, positive charge defects can be repeatedly generated in the gate dielectric.
To further investigate the degradation of reliability induced by defect generation in HfO2 dielectrics with various surface treatments, the SILC (∆J/J0) at the low electrical field of Eeff = 1.5 MV/cm as a function of injected charge is shown in Fig. 4-10. Figure 4-11 extracted the defect generation rate (Pg) from the linear portion of the relationship between (∆J/J0) and Qinj [61]. PDA could generally improve the films quality and further lowering the defect generation rate. The samples without surface treatment were not shown because of the leakage current after CVS exhibited a soft breakdown phenomena. It could be seen that the values of Pg for NH3 and Ozone treatment samples was relative low. For NH3-treated dielectric, strong Si−N bonding at the Si/dielectric interface against the defects generated, while for Ozone-treated dielectric, the robust interface properties would contribute to less Pg. RTO exhibited a poor defect generation resistance limited its applications.
Figure 4-12 presented the SILC for Ozone surface treatment with and without PDA.
Dielectric without PDA performed a serious leakage current during −|VFB|<VG<0 while others happened at VG<−|VFB|. The corresponding mechanism might be due to the low voltage SILC (LV-SILC) [62] caused by tunneling via a large amount of interfacial traps created from stress, rather than through bulk oxide traps. The difference in the SILC mechanism for Ozone oxide treatment caused by PDA should carefully investigate by eliminating other process
temperature effect such as implant activation.
4.3.2 Conduction Mechanism of the Ozone Surface Treatment HfO2 Dielectrics
The temperature dependence of the gate leakage current was studied to understand the current transport mechanisms. The leakage currents were measured from 25oC to 150oC for gate electron injection (negative VG). For the low electrical field case (<3.5 MV/cm), the experimental results fit the Schottky emission theory very well, as shown in Fig. 4-13. The leakage current governed by the Schottky emission yielded the following relationship:
⎥⎥
A Schottky barrier height of 0.95 eV between Al gate and HfO2 was extracted from these data.
The corresponding dynamic dielectric constant (εd=9.46) was in the range between the optical dielectric constant (εop=4 for HfO2) ant the static dielectric constant obtained from C-V (εs=9.5), which ensured the conduction mechanism. The band diagram of Al/HfO2/SiO2/Si capacitor simulated the low electrical field injection condition was illustrated in Fig. 4-14. It may be worth noting that, in the case of gate injection, because the Al/ HfO2 barrier height is smaller than the energy trap energy, Schottky emission mechanism dominates over the Frenkel-Poole (F-P) mechanism, therefore it is not possible to obtain the F-P trap energy from the above procedure.
Figure 4-15 showed the Fowler-Nordheim (F-N) tunneling fit in the high field range (>3.5 MV/cm). The slop of the fitted line followed the relationship:
2
barrier height value obtained from the FN tunneling characteristics (0.99 eV) was consistent with the Al/HfO2 barrier height (0.95 eV) we obtained earlier from Schottky emission analysis with an effective mass of 0.1 m0 [63]. The band diagram of Al/HfO2/SiO2/Si capacitor during the high electrical field carrier injection was illustrated in Fig. 4-16.
In section 4.3.1.1, we concluded that the hole current from substrate was considered the dominant conduction mechanism. However, in the temperature dependence measurement, the hole current term was masked by electron current, since electron current was more sensitive to temperature variation than hole current, which could be proved by carrier separation measurement demonstrated in Fig. 4-17 [64].
4.4 Summary
In this chapter, the surface treatment effects on the charge trapping characteristics the HfO2 gate dielectric were studied in terms of trapping efficiency, conductance peak shift, and SILC defect generation. Ozone oxide performed the lowest trapping efficiency, Dit
degradation and defect generation rate after 600oC PDA than NH3 or RTO treatment partially due to the better interface properties. However, Ozone-samples without PDA expressed poor
degradation and defect generation rate after 600oC PDA than NH3 or RTO treatment partially due to the better interface properties. However, Ozone-samples without PDA expressed poor