In this chapter, the effects of O3 post deposition annealing temperature on the properties of Ta2O5 were investigated by COCOS non-contact metrology. The dielectric thickness was increased as raising annealing temperature, which could be ascribed to the thick interfacial layer (IL) growth. A lower κ-value interfacial layer in series would reduce the dielectric capacitance after high temperature annealing. Moreover, the flat band voltage shift changed from positive to negative due to the electron traps elimination and partially hole traps generation in the film. It had been supposed that high temperature ozone annealing could compensate the dangling bond at the interface of Si/Ta2O5 proceed to minimize the interface trap density and improve the uniformity. Non-uniform interfacial layer oxidation after O3
annealing was supposed to cause the increasing of the field strength and break the the soft breakdown distribution.
Fig. 2-1 PSC TEL TriasTM Ta2O5 deposition system.
12 inch p-type (100) Si wafer
O3 Anneal Lamp Anneal Ta2O5 Deposition
Nitridation
RCA Clean with HF-last
NH : 10 sccm, 7003 °C, 1 min THK: 4.5±2Å
PET: 300 mg/min, O2: 2 slm, 430°C, THK: 85Å
O3 density: 200 g/m3, O2: 10 slm, Split Temperatures, 5 min,
O2: 10 slm, 800°C, 1 min
Interfacial layer SiOxNy
Ta2O5
Si
Fig. 2-2 Ta2O5 films process flow, device cross section and split conditions.
Fig. 2-3 Arrangement for corona charging and measurement used in SDI COCOS metrology [Ref. 37].
Fig. 2-4 Surface band diagram for Si/SiO2 system with a CPD reference electrode [Ref. 37].
n & k Opened Measure Mode
PDA Temperature (oC)
As-depo. 500 550 600 650 700
Dielectric Thickness (A)
90 95 100 105 110
(a)
n & k Open Measure Mode
PDA Temperature (oC)
As-depo. 500 550 600 650 700
Refractive Index
1.0 1.5 2.0 2.5 3.0 3.5 4.0
(b)
Fig. 2-5 (a) The physical Ta2O5 film thickness as a function of O3 annealing temperature determined by Rudolph ellipsometer in n & k opened mode. (b) The corresponding refractive index of the Ta2O5 films.
PDA Temperature (oC)
As-depo. 500 550 600 650 700 Capacitance (nF/cm2 )
0 500 1000 1500 2000
/
(a)
PDA Temperature (oC)
As-depo. 500 550 600 650 700
Effective Dielectric Constant
0 5 10 15 20 25
(b)
Fig. 2-6 (a) The dielectric capacitance (b) the effective dielectric constant (κ) of the Ta2O5
films as a function of PDA temperature.
(a) As-depo. (d) 600oC
(b) 500oC (e) 650oC
(c) 550oC (f) 700oC
Fig. 2-7 (a) ~ (f) Contact potential difference versus corona charge plot illustrating the determination of flat band voltage. Red line was the VCDP in the dark and the blue one showed the VCPD under illumination.
PDA Temperature (oC)
As-depo. 500 550 600 650 700
Flat Band Voltage Shift (V)
-1.0 -0.5 0.0 0.5 1.0
(a)
PDA Temperature (oC)
As-depo. 500 550 600 650 700 Q TOT (x1012 /cm2 )
-3 -2 -1 0 1 2 3
(b)
Fig. 2-8 (a) The flat band voltage shift (VFB) and (b) the total charge to flat band (QTOT) as a function of arising annealing temperature.
(a) As-depo. (d) 600oC
(b) 500oC (e) 650oC
(c) 550oC (f) 700oC
Fig. 2-9 The full mapping of the flat band voltage.
(a) As-depo. (d) 600oC
(b) 500oC (e) 650oC
(c) 550oC (f) 700oC
Fig. 2-10 The interface trap was manifested by the plateau on the VSB vs. corona dose curve.
(a) As-depo. (d) 600oC
(b) 500oC (e) 650oC
(c) 550oC (f) 700oC
Fig. 2-11 A Dit spectrum across the band gap obtained by plotting Dit versus VSB.
PDA Temperature (oC)
As-depo. 500 550 600 650 700 Interface Trap Density (x1012 cm-2 V-1 )
0 2 4 6 8 10 12 14 16
Fig. 2-12 Comparison the amount of interface trap densities as increasing the O3 annealing temperature.
(a) As-depo. (d) 600oC
(b) 500oC (e) 650oC
(c) 550oC (f) 700oC
Fig. 2-13 The full mapping of the interface trap density.
PDA Temperature (oC)
As-depo. 500 550 600 650 700
Soft Breakdown Field (MV/cm)
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Before CTS
CTS @ 170oC, 5min
Fig. 2-14 Soft breakdown field variation with and without corona temperature stress (CTS) at 170oC for 5 minutes.
Soft Breakdown Field (MV/cm)
Corona-Temperature-Stress @ 170oC, 5min
Soft Breakdown Field (MV/cm)
Fig. 2-15 The Weibull distributions of soft breakdown fields (a) without and (b) with corona temperature stress (CTS) at 170oC for 5 minutes.
(a) As-depo. (d) 600oC
(b) 500oC (e) 650oC
(c) 550oC (f) 700oC
Fig. 2-16 The full mapping of the soft breakdown field.
(a) As-depo. (d) 600oC
(b) 500oC (e) 650oC
(c) 550oC (f) 700oC
Fig. 2-17 The full mapping of the soft breakdown field during corona temperature stress (CTS) at 170oC for 5 minutes.
CHAPTER 3
Ozone Surface Treatment on the Characteristics and Reliabilities of HfO
2MOS Devices
3.1 Introduction
The shrinkage in metal-oxide-semiconductor field effect transistor dimensions is accompanied by a scaling of gate oxide thickness. It is well known that the scaling of conventional SiO2 is approaching the predicted limit due to large direct tunneling leakage current, thereby presenting a fundamental challenge to continual scaling [3]. Therefore, an alternative gate dielectric material is needed to replace SiO2. High-κ dielectrics, such as HfO2, are the potential candidates because a thicker film is utilized to reduce the direct tunneling leakage current while maintaining the same gate capacitance [41]-[44]. However, the control of SiO2-like interface between high-κ dielectrics and silicon substrate pays more and more important, since the device performances and reliability characteristics are strongly affected by the interface quality [44]. Nitridation of the Si surface using NH3 prior to the deposition of high-κ gate dielectrics has been shown to be effective in achieving the low EOT (equivalent oxide thickness) and preventing boron penetration [45, 46]. However this technique results in higher interface charges [47], which leads to higher hysteresis and reduced channel mobility.
Ozone-formed oxide (ozone oxide) has superior characteristics. Even when the formation temperature is less then 400°C, ozone oxide has a high film density comparable to that of the device-grade oxide film formed at higher temperature (e.g. 900°C) [48], a low interface trap density (Dit ~ 1010 cm2) [49], and a much thinner structural transition layer near the SiO2/Si
interface[48], [50]. The aim of this experiment was to investigate the interfacial issues at HfO2/silicon interface. The ozone surface treatment was employed to improve the interface quality between HfO2 and silicon substrate. Moreover, the rapid thermal oxidation (RTO) and the ammonia (NH3) surface treatment were also investigated as the reference in this thesis.
3.2 Experiment Details
3.2.1 Experiment Details of Ozone Oxide Growth
6 inch p-type (100) silicon wafers were cleaned by standard RCA processes with HF-last for the removal of the particles and native oxides. Figure 3-1 showed the schematic diagram of ozone water system. The ozone generator (AnserosPAP-2000) decomposed the oxygen molecular to generate ozone gas by high electrical field. The ozone gas was mixed with DI water in the dissolve unit and then pumped into the tank of wet bench. By changing the oxygen flow, DI water flux, and ozone generation power, the ozone concentration in the DI water could be adjusted. Ozone oxide was grown by immersing the Si wafer into the ozone water at room temperature. The relationship between the ozone concentration in the DI water and thickness change of ozone oxide was under investigation. Ellipsometer was utilized to measure the thickness and the etching rate in the hydrofluoboric acid (HF) of ozone oxide.
The micro-roughness of the wafer surface and the interface between ozone oxide/silicon were detected by atomic force microscopy (AFM).
3.2.2 Process Flow of HfO2 MOS Devices with Surface Treatments
LOCOS isolated MOS capacitors were fabricated on 6 inch p-type (100) silicon wafers.
After forming LOCOS isolation, wafers were cleaned by standard RCA processes with HF-last. Prior to high-κ dielectrics deposition, the samples were prepared either by Ozone, NH3 or RTO. Diluted ozone water (2ppm) was used to grow an ultra-thin ozone oxide about 7~8Å (measured by ellipsometer). NH3 nitridation was performed in a high temperature furnace at 800oC for 1 hour to generate an ultra-thin oxynitride layer (~7 Å). RTO was also intended to deposit a thin SiO2 layer (~8Å), at 800oC using a rapid thermal process system for 30 seconds. After one of the surface treatments, 50Å HfO2 was then deposited at 500oC by MOCVD system, as shown in Fig. 3-2, followed by a high temperature post deposition annealing (PDA) at 600oC in the nitrogen ambient for 30 seconds. Aluminum metal served as the gate electrode was created by a thermal evaporation system. After gate electrodes patterned and contact holes etched, backside contact was formed. The cross section and the total process flow were shown in Fig. 3-3. Square capacitors of 1×10-4 cm2 areas with LOCOS isolation are used to evaluate the gate oxide integrity. The equivalent oxide thickness (EOT) was extracted by fitting the measured high-frequency (10 kHz) capacitance-voltage (C-V) data from Hewlett-Packard (HP) 4284 LCR meter under accumulation condition.
UCLA CVC simulation program was utilized to obtain the accurate flat band voltage (VFB).
The C-V hysteresis phenomenon was measured by sweeping the gate voltage from accumulation to inversion then back. The tunneling leakage current density-electric field (J-E) and the reliability characteristics of MOS capacitors were measured by semiconductor parameter analyzer HP 4156C.
3.3 Results and Discussions
In this chapter, the influences of surface treatments prior to hafnium oxide (HfO2)
deposition were investigated. Comparisons between various surface treatments, including:
ozone water oxidation (Ozone), rapid thermal oxidation (RTO) and ammonia (NH3) nitridation were studied.
3.3.1 Basic Property Investigation of the Ozone Oxide
The growth curves of ozone oxide as a function of ozone water concentration were shown in Fig. 3-4. The growth rate was increased as raising the ozone quantity contained in DI water from 1ppm to 10ppm. A saturated oxidation was observed in the growth curves and the resultant self-limiting property could improve the thickness uniformity after furnace or/and rapid thermal oxidation.
Figure 3-5 compared the etching rate in diluted HF solution between ozone oxide and chemical oxide formed by RCA clean process. A higher etching rate for ozone oxide was discovered near the transition region. Generally, volume expansion due to silicone oxidation can generate compressively strained Si local structures with an excess of silicon atoms in the interface, and distort Si–O–Si bonds at the Si/SiO2 interface compressively [51]. Therefore, an imperfect, lower density transition layer was existed at the Si/SiO2 interface. In contrast, the utilization of ozone water to growth ultra-thin oxide may form a defect-free SiO2 network formation in the transition region, which generates more reactive oxygen atoms to saturate the Si dangling bonds [51]. The formation of a more homogeneous structure at the Si/SiO2
interface responded to a higher etching rate for the denser transition layer.
Appropriate surface treatment prior to high-κ dielectric deposition is necessary to improve the interface characteristics between high-κ dielectric and silicon substrate. In order to investigate the improvement of interfacial properties between HfO2 and Si substrate, silicon surface roughness was measured by AFM before and after surface treatment, which can be
achieved by dipping within dilute HF solution (HF:H2O=1:500). Figs. 3-6 to 3-8 displayed the AFM results for ammonia (NH3) nitridation, rapid thermal oxidation (RTO), and ozone water oxidation (Ozone) surface treatments, respectively. The surface roughness improvement was defined as the difference before and after the surface treatment, as shown in Fig. 3-9. After ozone water oxidation, the Si surface roughness was reduced from 1.37Å to 0.79Å (improved 41.38%), which was beneficial to suppress the leakage current density of the stacked gate dielectric. On the other hand, NH3 and RTO treatment prior to HfO2 deposition was less help to ameliorate Si surface roughness, which may be ascribed to higher stress introduced than Ozone treatment.
3.3.2 Comparison of Surface Treatments Prior to HfO2 Deposition with PDA Effect
Figure 3-10 showed the normalized capacitance-voltage (C-V) characteristics of HfO2
stacked gate dielectrics with various surface treatments for samples (a) without PDA and (b) with 600oC PDA. Post deposition annealing could reduce the interface trap density exhibited by less kink and more sharp C-V characteristics. Apparent C-V deterioration was observed in NH3-treated sample due to the excess nitrogen concentration compels more Si bonding constraints at the interface [52]. The C-V curve of Ozone-treated capacitors was kink free and exhibited good interface properties.
High-κ dielectric densification and interfacial oxidation mechanism were competed during high temperature annealing process which caused the little variations in equivalent oxide thickness (EOT) showed in Fig. 3-11. Ozone treatment slightly increased the EOT after 600oC PDA supposed to the incomplete oxidation in bulk ozone oxide owing to the low growth temperature.
The hysteresis of various surface treatments was compared in Fig. 3-12. The hysteresis
voltage was defined as the flat band voltage difference between the forward and backward swept C-V curves, which might be contributed from the trapped charges within high-κ bulk or interface. The samples without surface treatment revealed large hysteresis; even subsequently high temperature annealing would reduce C-V hysteresis. Similarly, NH3 nitridation also exhibited large hysteresis, regardless of the high temperature annealing. Fortunately, surface oxidation resulted in excellent hysteresis behavior, for both RTO and Ozone treatment.
Moreover, Ozone-treated sample exhibited almost hysteresis-free characteristics.
Figure 3-13 presented the dependence of VFB shift on surface treatment with and without PDA. NH3 nitridation exhibited large negative VFB shift compared to sample without treatment indicated positive charges accumulation after surface nitridation. After 600oC PDA, NH3-treated sample showed obvious VFB recovery due to interfacial N exchanged by O from annealing ambient. On the other hand, RTO- and Ozone-treated samples possessed less VFB
shift than NH3 nitridation which demonstrated superior interface than NH3-treated sample.
Negative VFB shift of Ozone-treated sample after PDA may indicate the increment of positive charges, which should be further investigated.
Leakage current density of HfO2 stacked gate dielectrics with various surface treatments as a function of effective electric field (Eeff) for samples (a) without PDA and (b) with 600oC PDA were demonstrates in Fig. 3-14. Both RTO and Ozone treatment could suppress the leakage current than sample without surface treatment, partially due to smoother interface roughness. As indicated in Fig. 3-15(a) for samples without PDA, surface treatments could lower the leakage current density at 6 MV/cm at least two orders. Figure 3-15(b) revealed that a suitable PDA can further improve the dielectric properties.
Synthesized above mentioned in Fig. 3-16, PDA and surface treatment could reduced current density at least 2 orders of magnitude with smaller than 3Å EOT increment. The calculated effective dielectric constant as a function of surface treatments was ranging from 8
to13, as observed in Fig. 3-17.
The time-zero dielectric breakdown (TZDB) and the time-dependent dielectric breakdown (TDDB) reliability investigation were shown in Figs. 3-18 and 3-19, respectively.
Surface treatments prior to high-κ dielectrics deposition and PDA can promote the reliability.
Sample without surface treatment was supposed to have poor interface between HfO2/Si, which will degrade the dielectric reliability. After surface treatments, the interface quality was improved, and the reliability therefore became superior. The ozone oxide treatment also revealed comparable results with RTO even under higher stressing voltage.
3.4 Summary
In this chapter, the basic properties of the ozone oxide were studied first. The growth rate of ozone oxide was increased as raising the ozone quantity contained in DI water. A saturated oxidation was observed in the growth curves and the resultant self-limiting property could improve the thickness uniformity after furnace or/and rapid thermal oxidation. The formation of a more homogeneous structure at the Si/ozone oxide interface performed a higher etching rate for the denser transition layer. Ozone oxide could improve Si surface roughness by 41%, which was beneficial to suppress the leakage current density of the stacked gate dielectric.
Then the influences of surface treatment prior to HfO2 gate dielectric deposition were investigated. Significantly large fixed charges and hysteresis of NH3 nitridation would degrade device performance. Albeit RTO treatment exhibited comparable leakage current with Ozone treatment, the time-to-breakdown value was still also less than Ozone treatment. As a result, sample with Ozone treatment revealed small leakage current, negligible hysteresis and
excellent dielectric reliability, which was considered to be one of the most potential alternative to improve the interface properties between high-κ dielectrics and silicon surface.
O2
N2
Buffer Tank
O3
Generator Dissolve Unit
PUMP O3
Destructor
O3 Analyzer Orbisphere
-3600
UV Lamp Tank
Bench DI Water
O3 Water
PUMP O3 Gas
O3 Water
Waste Water
Fig. 3-1 Schematic diagram of ozone oxide growth system.
Fig. 3-2 Schematic diagram of MOCVD system structure.
P P ro r oc ce es ss s F Fl lo ow w
RCA Clean with HF-last1. w/o Treatment
Al gate & backside contact formation by Thermal Evaporation System
Si
Fig. 3-3 HfO2 MOS devices process flow, device cross section and split conditions.
Growth Time (min)
0 1 2 3 4 5
Ozone Oxide Thickness (A)
0
Fig. 3-4 The growth curves of ozone oxide as a function of ozone water concentration.
HF:H2O=1:500
Fig. 3-5 Comparison the etching rate of ozone oxide at HF: H2O=1:500 to chemical oxide formed by RCA clean without HF-last.
(a) Bare-Si Roughness RMS Average =1.98 Å
(b) NH3 Nitridation Roughness RMS Average =1.85 Å
(c) HF-dipped Roughness RMS Average =1.81 Å
Fig. 3-6 AFM results of NH3 treatment for Si surface roughness improvement.
(a) Bare-Si Roughness RMS Average =2.13 Å
(b) RTO Roughness RMS Average =1.47 Å
(c) HF-dipped Roughness RMS Average =1.92 Å
Fig. 3-7 AFM results of RTO treatment for Si surface roughness improvement.
(a) Bare-Si Roughness RMS Average =1.37 Å
(b) Ozone oxide Roughness RMS Average =1.09 Å
(c) HF-dipped Roughness RMS Average =0.79 Å
Fig. 3-8 AFM results of ozone oxide treatment for Si surface roughness improvement.
NH3 RTO Ozone
Si Surface Roughness Improvement (%)
0 10 20 30 40 50
41.83%
8.60% 9.87%
Fig. 3-9 Comparison of the Si surface roughness improvement for three kinds of surface treatments.
w/o PDA Samples
PDA 600oC Samples
Gate Volatge (V)
Fig. 3-10 Normalized C-V characteristics of HfO2 stacked gate dielectrics with various surface treatments (a) without PDA and (b) with 600oC PDA.
w/o PDA Samples
PDA 600oC Samples
EOT(A)
Fig. 3-11 EOT Weibull distributions for samples (a) without PDA and (b) with 600oC PDA.
w/o Treatment NH3 RTO Ozone
Fig. 3-12 Hysteresis comparison between several surface treatments.
Extrated by CVC Program
w/o Treatment NH3 RTO Ozone
Flat Band Volatage ( V )
Fig. 3-13 Flat-band voltage variation as a function of surface treatments.
w/o PDA Samples
Effective Electric Field (MV/cm )
0 5 10 15 20 25
PDA 600oC Samples
Effective Electric Field (MV/cm )
0 5 10 15 20 25
Fig. 3-14 Leakage current density of HfO2 stacked gate dielectrics with various surface treatments as a function of effective electric field (a) without PDA and (b) with 600oC PDA.
w/o PDA Samples
PDA 600oC Samples
Current Density @ 6 MV/cm (A/cm2)
Fig. 3-15 Leakage current density Weibull distributions at 6 MV/cm for samples (a) without PDA and (b) with 600oC PDA.
w/o Treatment NH3 RTO Ozone
Current Density @ 6 MV/cm (A/cm2 ) 10-16
Fig. 3-16 Assembled the EOT and leakage current density at 6 MV/cm performances for different surface treatments.
w/o Treatment NH3 RTO Ozone
Effective Dielectric Constant
Fig. 3-17 Effective dielectric constant variation as a function of surface treatments.
w/o PDA Samples
PDA 600oC Samples
Effective Breakdown Field (MV/cm)
Fig. 3-18 TZDB reliabilities for samples (a) without PDA and (b) with 600oC PDA.
w/o PDA Samples
PDA 600oC Samples TDDB Weibull plots
Fig. 3-19 TDDB reliabilities for samples (a) without PDA and (b) with 600oC PDA.
CHAPTER 4
Trapping Characteristics and Current Transport Mechanism of the HfO
2Gate Dielectric
4.1 Introduction
According to the International Technology Roadmap for Semiconductors (ITRS), the further miniaturization of the integrated circuits in gigascale technology requires the use of high dielectric constants (high-κ) materials as charge storage insulators as well as alternative gate dielectrics in metal-oxide-semiconductor field-effect transistors (MOSFETs) [3].
Consequently, the high-κ oxides have been extensively studied to overcome the problems associated with the extremely thin conventional thermal SiO2. For example, these materials have to be introduced in integrated circuits to satisfy the increasing demands of the high-density capacitors for dynamic random access memory (DRAM) applications [54]-[55].
Recently many efforts have been devoted to understand the electrical properties including defects produced under various treatments of MOS structures with high permittivity insulators.
Very little is known about the reliability of the high-κ dielectrics. The degradation of the insulator in MOS devices is one of the most important issues for the ultralarge-scale integrated circuits and the reliability characteristics are greatly influenced by the bulk and interface traps. The problem with the high-κ dielectrics is that very often these traps exist in unacceptably high levels due to a nonstoichiometric composition and/or microstructure imperfections which usually are present in the as-fabricated films. These defects act as traps for the charge carriers injected into or generated in the dielectric. In order to meet the future
needs of the high-κ dielectrics reliability, a physical understanding of the conduction and degradation mechanisms is required for these materials. In this chapter, the surface treatment effects on the charge trapping characteristics and current transport mechanism of the HfO2
gate dielectric were studied.
4.2 Experiment Details
Mainly, the samples measured in this chapter were the same with those in chapter 3.
LOCOS isolated MOS capacitors were fabricated on 6 inch p-type (100) silicon wafers. After forming LOCOS isolation, wafers were cleaned by standard RCA processes with HF-last.
Prior to high-κ dielectrics deposition, the samples were prepared either by Ozone, NH3 or RTO. Diluted ozone water (2ppm) was used to grow an ultra-thin ozone oxide about 7~8Å (measured by ellipsometer). NH3 nitridation was performed in a high temperature furnace at 800oC for 1 hour to generate an ultra-thin oxynitride layer (~7Å). RTO was also intended to deposit a thin SiO2 layer (~8Å), at 800oC using a rapid thermal process system for 30 seconds.
Prior to high-κ dielectrics deposition, the samples were prepared either by Ozone, NH3 or RTO. Diluted ozone water (2ppm) was used to grow an ultra-thin ozone oxide about 7~8Å (measured by ellipsometer). NH3 nitridation was performed in a high temperature furnace at 800oC for 1 hour to generate an ultra-thin oxynitride layer (~7Å). RTO was also intended to deposit a thin SiO2 layer (~8Å), at 800oC using a rapid thermal process system for 30 seconds.