Surface Treatment Effects on the Charge Trapping Characteristics of HfO 2

4.3.1.1 Trapping Efficiency Characteristics

Figure 4-1 depicted the effects of surface treatment on transient charge trapping behaviors of HfO2 dielectrics with and without PDA under a constant voltage stress (CVS) of -3.8V. The decrease in the absolute gate current was obviously coming from hole trapping behavior. Figure 4-2 was the corresponding flat band voltage shift toward negative direction due to the positive charges trapped, i.e. hole trapping after stress. For going to details about reliability phenomenon, Fig. 4-3 demonstrated trapped charges under CVS with various injection charges and the slop was defined as the trapping efficiency (showed in Fig. 4-4) used to compare the dielectric quality.

In order to obtain low trapping efficiency, dielectrics with low bulk and interface trap

density should be deposited. However, the sample without surface treatment and PDA was not shown here because of significant degradation after CVS. Even though post deposition annealing could improve the dielectric quality, the trapping efficiency was still not as good as the samples with surface treatments. Ozone oxide exhibited the lowest trapping efficiency after 600^oC PDA than NH3 or RTO treatment partially due to the better interface properties.

On the other hand, the inferior trapping characteristics of Ozone-samples without PDA might be caused by the incomplete oxidation owing to the low growth temperature, which could be evidenced on lower etching rate shown in Fig. 3-5.

The corresponding band diagram including the two leakage current components under CVS condition was drawn in Fig. 4-5. Hole current from substrate was considered to be the dominant terms owing to the negative VFB shift and the decreasing of absolute gate current which consisted with that the interface layer quality influence the carriers injection.

4.3.1.2 Interface Trap Properties Information from Conductance Measurements

The conductance-voltage (G-V) measurement [56] is a useful and sensitive tool for investigating interface characters between Si and dielectrics. In the conductance method, interface trap levels are detected through the energy loss resulting from changes in interface traps occupancy produced by small variation of gate voltage. The small-signal equivalent parallel conductance of MOS capacitor Gp displays different behavior depending on the dominant loss mechanism. For a chosen ac frequency, vary the gate bias from accumulation to midgap. In accumulation, majority carrier density is very large near the Si/dielectric interface, so those interface trap capture rates are very rapid compared to the ac frequency. Interface trap levels respond immediately to the ac voltage, and no loss occurs. In depletion, majority carrier density at the Si/dielectric interface is reduced. Capture rates slow down, and interface

trap levels cannot keep in phase with the ac voltage. A loss therefore occurs. Still further in depletion, near midgap, majority carrier density becomes insufficient that almost no carriers are exchanged between interface trap levels and the silicon. Hence the loss is also low. In short, interface trap loss goes through a peak as a function of gate bias. Maximum loss occurs for the gate bias where majority carrier density makes the interface trap capture rate compare to the ac frequency.

Figure 4-6 illustrated the C-V and G-V curves variation after CVS for Ozone-treated samples with and without PDA. The conductance peak shift and the value increase were corresponding to the flat band voltage shift and the degraded Dit, respectively. Figure 4-7 compared the variation of conductance peak value after CVS for several surface treatments.

Two components should be noted: first is the initial conductance peak value and the second one is the change of the conductance peak value after CVS. Figure 4-8(a) compared the initial conductance peak values corresponding to the initial amount of Dit for various surface treatments. The sample without surface treatment and PDA was not shown because of the dielectric degradation after CVS. Post deposition annealing could reduce the conductance peak value as well as the interface trap density. NH3 nitridation exhibited large conductance peak value compared to sample without treatment indicated higher interface charges after surface nitridation. Ozone oxide performed the lowest Dit values than NH3 or RTO treatment due to the better interface properties.

The comparison of the peak value change after CVS was displayed in Fig. 4-8(b). Both surface treatments and PDA could suppress the Dit generation. However, Ozone-samples without PDA expressed poor results might cause by the rougher interface than 600^oC PDA samples shown in the HRTEM cross-sectional images in Fig.4-9.

4.3.1.3 SILC Reliabilities and Defect Generation Rate Properties

Stress-Induced-Leakage-Current (SILC) is an increase in gate oxide leakage current resulting from the application of a stress voltage or current [57]-[60]. It is an important concern in scaling gate oxide thickness because it can decrease DRAM refresh times, degrade EEPROM data retention, and increase MOSFET off-state power dissipation. During constant negative voltage stress, hole current from the substrate was injected through the interfacial layer and HfO2 gate dielectric of the MOS capacitor. Then, positive charge defects can be repeatedly generated in the gate dielectric.

To further investigate the degradation of reliability induced by defect generation in HfO2 dielectrics with various surface treatments, the SILC (∆J/J0) at the low electrical field of Eeff = 1.5 MV/cm as a function of injected charge is shown in Fig. 4-10. Figure 4-11 extracted the defect generation rate (Pg) from the linear portion of the relationship between (∆J/J0) and Qinj [61]. PDA could generally improve the films quality and further lowering the defect generation rate. The samples without surface treatment were not shown because of the leakage current after CVS exhibited a soft breakdown phenomena. It could be seen that the values of Pg for NH3 and Ozone treatment samples was relative low. For NH3-treated dielectric, strong Si−N bonding at the Si/dielectric interface against the defects generated, while for Ozone-treated dielectric, the robust interface properties would contribute to less Pg. RTO exhibited a poor defect generation resistance limited its applications.

Figure 4-12 presented the SILC for Ozone surface treatment with and without PDA.

Dielectric without PDA performed a serious leakage current during −|VFB|<VG<0 while others happened at VG<−|VFB|. The corresponding mechanism might be due to the low voltage SILC (LV-SILC) [62] caused by tunneling via a large amount of interfacial traps created from stress, rather than through bulk oxide traps. The difference in the SILC mechanism for Ozone oxide treatment caused by PDA should carefully investigate by eliminating other process

temperature effect such as implant activation.