In Chapter 2, we studied MOS capacitors and MOSFETs for different orientation on GaAs (100) and (111)A surface. The results of MOS capacitors electrical characteristics on GaAs (111)A surface are very different that compared to (100) surface. And then, we discussed series resistance including sheet resistivity and contact resistivity. We explored sheet resistivity and contact resistivity by CTLM structure. Next, we studied the junction for different activity temperature. Finally, we optimize conditions of sheet resistivity, contact resistivity, and Ohmic RTA time, and then, we applied these conditions on MOSFET.
In Chapter 3, we measured the electrical characteristic of GaAs capacitors with Al2O3
dielectric, including C-V measurement and conductance. We also studies electrical characteristic of sample with silane passivation and PDA compared to sample without passivation. Next, we analyzed reliability for silane passivation. A clear understanding of reliability of the different interfaces, via charge trapping/detrapping studies under different stressing condition. Finally, we applied this passivation on MOSFET.
In Chapter 4, we fabricate GaAs NMOSFET with embedded-Ge source/drain to solute the issues of low density of states (DOS) and the limited dopant level. But n+-Ge contact has been a challenge in EF pinning on metal/ n+-Ge interface. We used TiO2 interfacial layer to let the electrical characteristics of GaAs NMOSFET with embedded-Ge source/drain be imporved.
In Chapter 5, we conclude these studies including different orientation, silane
4
passivation, sheet resistivity, contact resistivity, junction and MOSFET. Finally, we gave some future works.
5
Reference
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Fig. 1.1 the device scaling roadmap of performance demonstrated by IMEC
Fig. 1.2 combination of III-V and Ge channel structure by Takagi et al.
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Chapter 2
Electrical characteristics of GaAs MOS capacitor for different surface
orientation
2.1 Introduction
In order to continue the scaling of silicon-based CMOS and maintain the historic progress in information processing and transmission, innovative device structures and new materials are required. A channel material with high mobility and therefore high injection velocity can increase ON current and reduce delay. Currently, strained-Si is the dominant technology for high performance MOSFETs. However, looking into future high mobility III-V materials can offer several advantages over even very highly strained Si.
The III-V compound semiconductors such as GaAs have high electron mobility, high breakdown field, low power consumption and wide band gap engineering [1, 2, 3]. Recently, GaAs is one of great importance for scientific understanding of III-V interface and GaAs compound semiconductor devices are applied as photodiodes, high electron mobility transistors (HEMT), and other high-frequency devices [4]. But the poor quality of the insulator/ substrate interface deposited such as SiO2 and Si3N4 degraded the performance of MOSFET. Therefore, the literature on the subject that research efforts on achieving low interfacial density of states (Dit) covers the past 40 years. The different surface orientation have different density of states (Dit), the researchers discovered that the Fermi-level on GaAs(111)A is unpinned compare with GaAs(100) [5-6]. This experimental result
9
demonstrated that Fermi-level pining is not an intrinsic property, but the orientation dependent.
The deposition mechanism of atomic-layer-deposited (ALD) is like chemical vapor deposition (CVD), but is a thin film growth technique that two sequential, self-limiting surface reaction between gas precursor such as tetrakis (ethylmethylamino) hafnium ( TEMAH, Hf[N(C2H5)(CH3)]4 ) and trimethylaluminum ( TMA, Al(CH3)3 ). ALD is a widely used insulator as gate dielectric due to its good insulated properties, grown films are conformal, pin-hole free, chemically bonding to reduce interfacial trap densities. After all, ALD is one of the CVD, so thermal annealing can further improve the quality of dielectric.
Meanwhile, during high temperature process it is important to inhibit the loss of As within the GaAs substrate and also suppress the formation and subsequent incorporation of native oxides.
The impact of thermal annealing on the properties of high-k/III-V interface has been researched [7].
This Electrical characteristics, such capacitance-voltage ( C-V ) and conductance characteristics, are regularly used in research and development to understand important parameters of MOS capacitor and MOSFETs. For example, capacitance-voltage (C-V) measurements are widely used to quantitatively study the MOS structures. There are several important parameters in evaluating high-k dielectrics on novel channel materials, such as hysteresis, frequency dispersion, and flat band shift and the dielectric/Ⅲ-Ⅴ interface quality.
C-V method is powerful to study the properties of the MOS structure, especially to explore the issues with interfacial layers. Otherwise, the C-V and conductance characteristics are the methods of choice to extensively study the interface characteristic because of the inherent sensitivity of the electrical measurements and the ease-of-use of the involved methods [8].
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2.2 Experimental process
2.2.1 Surface clean
MOS capacitor sample was prepared on high Si-doped (p-type, 1~5×1017 cm-3 and n-type, 1~5×1017 cm-3) GaAs with (100) and (111)A crystal orientation substrates. We have three clean steps. At first, the GaAs was rinsed in the diluted HCl ( HCl : H2O = 1 : 3 ) solution for 3 min for native oxide removal, followed by rinsed in deionized water ( D.I.
water ) for 5 min. Second, the GaAs was rinsed in the diluted NH4OH ( NH4OH : H2O = 1 : 10 ) solution for 10 min for excess elemental arsenic removal, followed by rinsed in D.I.
water for 5 min. Third, the GaAs was rinsed in the (NH4)2S solution at room temperture for 10 min for ex-situ surface passivation, followed by rinsed in D.I. water for 5 min.
2.2.2 ALD High-k Al2O3
The samples mounted in the ALD chamber and gave 20 trimethylaluminum (TMA) precursor pulses for reducing residual native oxide. And then, the Al2O3 gate dielectric was deposited by ALD at 250 ℃, followed by post deposition annealing ( PDA ) in a N2 ambient.
Thermal annealing can further improve the quality of dielectric.
2.2.3 Metal deposition
Thermal evaporated 400 nm Al were patterned as gate electrodes through the lithography. Finally, e-beam evaporated Ti/Pt/Au (50 Å /300 Å /1800 Å ) for p-type and Ni/Ge/Au (300 Å /700 Å /1800 Å ) for n-type was deposited as backside contact.
The complete process flow was shown in Fig. 2.1. The electrical characteristics of Al/Al2O3/p-GaAs/TiPtAu and Al/Al2O3/ n-GaAs/NiGeAu MOS capacitors were measured using an HP4284 and HP4200, respectively.
2.3 Effective reduction interfacial traps using thermal annealing
ALD is one of the CVD, so thermal annealing can further improve the quality of
11
dielectric. Meanwhile, during high temperature process it is important to inhibit the loss of As within the GaAs substrate and also suppress the formation and subsequent incorporation of native oxides.
The impacts of initial GaAs post-deposition annealing have been investigated. We used four conditions of PDA to optimize better post annealing condition that efficiently reduced native oxide. Reducing the high density of states on oxide/GaAs, particularly those near the GaAs midgap region, resulting in serious Fermi-level pinning, and thus preventing a proper inversion response required for the inversion-channel GaAs MOSFETs, is an important issue.
In this work, the interfacial traps are qualitative by performing C-V measurement. We designed that post annealing at 500 ℃ for 30s, 600 ℃ for 15s, 600 ℃ for 30s and 700 ℃ for 30s on samples to find the optimal condition to lead to significant reduction of density of states.
Capacitance-Voltage (C-V) characteristics of Al2O3/p-GaAs MOS capacitances annealed under various conditions have been summarized in Fig. 2.2 : (a) annealing at 500 ℃ for 30s, (b) at 600 ℃ for 15s, (c) at 600℃ for 30s, and (d) at 700 ℃ for 30s. All the C-V curves were measured by varies frequency (1kHz ~ 100kHz). According to these figures, we can find that post annealing at 600 ℃ for 15s on sample had better electrical characteristics.
Annealing at 500 ℃ for 30s on sample didn’t bend banding to accumulation that value of capacitance was low compared to other samples. Annealing at 600 ℃ for 30s and at 700 ℃ for 30s on samples had obvious stretch out behavior.
In summary, following to these characteristics of Capacitance-Voltage, we can optimize the condition that post annealing at 600 ℃ for 15s on sample had better electrical characteristics. It’s can significantly reduce native oxide, and then efficiently move Fermi-level.
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2.4 Capacitance-Voltage characteristics for different surface orientation
2.4.1 A C-V measurement result
First of all, we exhibit the basic properties of the GaAs (100) p-type and n-type MOS capacitor C-V curves with multi-frequency, as shown in Fig. 2.3 (a) and (b), respectively.
The quantities of measured capacitances could be used to evaluate the quality of high-k dielectrics and insulator-semiconductor. I defined frequency dispersion ratio≡∆C . The equation of ∆C is reproduced according to Eq.(2.1)
∆C ≡ (C (@1kHz) – C (@100kHz) )/ C (@1kHz) ( 2.1) The p-type GaAs (100) frequency dispersion (3.34%@-3V) are more excellent than n-type GaAs (100) frequency dispersion (9.99%@+3V). We believed that should be a large amount of density of states (Ga-Oxide) existed in upper half interfaces of bandgap. It slows the Fermi-level is pinned at the upper half interface of bandgap when we supply voltage to gate.
After introducing capacitance-voltage curves of GaAs (100), Fig. 2.4 (a) and (b) show the MOS capacitor C-V curves of the GaAs (111)A p-type and n-type that is different crystalline surface. The figures compare to Fig. 2.3 (a) and (b), n-GaAs (100) samples can’t reach accumulation even at +3V applied to the gate. This case is because the Fermi-level is pinned for a large amount of interface density of states. The MOS capacitor for n-GaAs (111)A revealed C-V behavior can reach accumulation and had low stretch-out in depletion.
The p-type GaAs (111)A frequency dispersion is 3.08% (@-3V) and n-type GaAs (111)A frequency dispersion is 8.28% (@+3V). The values revealed interface of states GaAs(111)A were lower compared to GaAs(100).
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2.4.2 Quasi-static C-V measurement result
Interface trapped charge, also known as interface traps or states are attributed to dangling bonds at the semiconductor/insulator interface. GaAs is a large bandgap material.
Therefore, there is a large density of very slow interface states inside the GaAs semiconductor bandgap. Quasi-static C-V provides information only on the interface trapped charge density, but not on their capture cross section. The quasi-static C-V for different surface orientation was shown in Fig. 2.5 (a) and (b) and calculating the surface potentialψs is a function of gate voltage that surface potential was calculated by Berglund method. Berglund is given by Eq.(2.2)
where CQSCV is the quasi-static C-V curve as a function of gate voltage. Integration from VG1
= VFB makes = 0, because band bending is zero at flatland. Integration from VFB to accumulation and from VFB to inversion gives the surface potential across the energy bandgap range. Fig. 2.6 displays the calculated result, surface potentialψs versus gate voltage VG.
According to Fig. 2.6, we can obviously know that these experimental results conclusively demonstrate that Fermi-level on the GaAs (111)A surface is indeed unpinned and Fermi-level pinning is not an intrinsic property of GaAs, but is orientation dependent thus related to surface chemistry.
Otherwise, Utilizing high-frequency C-V curve and quasi-static C-V to extract Dit as a function of gate voltage by high-low frequency method is described in Eq. (2.3).
where the value of Cox is defined on accumulation of quasi-static C-V. After Dit extracted by high-low frequency method and x-axis conversion by surface potential ψs versus gate voltage VG, result in Dit versus surface potentialψs is displayed in Fig. 2.7 (a) and (b).
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According to the Fig. 2.7 (a) and (b), we understand the difference between (111)A orientation and (100) orientation. It is the reason that the performance of GaAs on (111)A applied for MOSFETs is quite good compared to (100) orientation.
2.4.3 Charge neutrality level (CNL) measurement
The explanation of the Fermi level pinning phenomenon was first proposed by Bardeen, the pining point was assumed to take place at the charge neutrality level (CNL) of the surface states. Furthermore, extending this idea, Cowley and Sze derived the following well-known equation for a M-S system.
(2.4) Where is the location of the CNL measured form the vacuum level given by
with known c2 and c3 from experiments of varying . First, we found different metals such as Ti, Au, and Pt to extract those schottky barrier heights that we use Capacitance-Voltage method to get . The experimental results of the metal-n-type GaAs system are shown in Fig. 2.8. The slope is c2 and the intercept is c3.
Spicer et al. discovered that CNL) in GaAs is separately 0.5eV and 0.7eV above the valence band maximum (VBM) by photoemission and other experiments. However, According to experiment results, eV for GaAs(100) and eV for GaAs(111)A were not significantly different.
2.5
Admittance Behavior ofGaAs MOS capacitor
2.5.1 Conductance Method to Extract Dit
The conductance method is one of the most sensitive methods to determine Dit, so it is the means of choice to extensively study the interface passivation. Through understanding of the conductance method allow proper extraction of the interface trap across the bandgap. First of all, we have to understand that conductance is extracted since the substrate conductance
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only is contributed from interface density and the band diagram of MOS capacitor is showed in Fig. 2.9. Where is a gate voltage VG applied between the metal and the semiconductor, which fixes the value of the surface Fermi level. The C-V measurements consist in applying on top of the static gate bias voltage a small sinusoidal voltage with frequency f and amplitude of 25 mV. This small periodic gate voltage causes the bands and the surface potential in the semiconductor to periodically move up and down, causing the interface traps lying around the value of the surface potential to fill and empty. Only if the traps around the surface potential have a characteristic response time that is of the order of the measurement frequency f can they interact with the measurement ac signal and affect the total impedance of the MOS capacitor. The conductance uses a simplified equivalent circuit of the capacitance and the parallel conductance, as seen in equivalent circuit model of Fig. 2.10. It consists of the oxide capacitance Cox, the semiconductor capacitance Cs, and the interface state capacitance Cit. The capture-emission of carriers by Dit is a losing process, represented by the resistance Rit. It is convenient to replace the circuit of Fig. 2.10(a) by Fig. 2.10(b), where Cp and Gp are given by
where Cit = q2Dit , ω=2πf, f is measurement frequency, and = RitCit, the characteristic emission frequencies of trapped charge carriers, given by .
Equation (2.5) and Equation (2.6) is valid for an interface trap with single energy level in the bandgap. In reality, interface traps are continuously distributed across the bandgap. If the time constant dispersion and trap energy level distribution across bandgap are taken into account, eq. (2.6) is modified:
(2.7)
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When Gp/ is plotted as a function of f, the maximum appears at f , and at that maximum
(2.8) Gp/ plots are repeated at different gate voltages to scan trap energies to obtain an interface state density distribution across the bandgap. By utilizing eq. (2.9), can be determined from the measurement ( ) by eliminating the oxide capacitance.
(2.9)
The flows of conductance method to extract Dit in Fig. 2.11.
2.5.2 Conductance method application of GaAs MOS capacitor
It is worthy to note that according to the emission time constant ( ), the behavior of interface trap time constant as a function of temperature determines the part of interface traps in the bandgap observable in the MOS admittance characteristic. That is, traps located nearer to midgap become observable for higher temperatures while traps more located toward the band edges become observable for lower temperature. We assumed the capture cross section σ = 1×10-15 cm2 and plotted the characteristic emission frequencies of trapped charge carriers in GaAs at the different temperature as a function of the position of the trap in
the energy bandgap.For high band gap GaAs, midgap traps are not able to be observed at room temperature; if increasing the temperature, the observable energy windows shift toward
the midgap as shown in Fig 2.12, where the effective density of states of the conduction (Nc) and the valence (Nv) bands, electron and hole thermal velocity, change in GaAs bandgap with
temperature are all taken into account. Fig 2.13 and Fig. 2.14 illustrates the Gp/ versus f plots of MOS capacitor for different orientation and measurement is performed at room temperature. Gp/ curves are shown at the gate voltages Fermi level is only portions of the
17
bandgap where interface states are able to capture and emission with the small signal AC bias.
The peak value of each Gp/ curve corresponds to the interface state density and thus Dit as a function of gate voltage can be plotted. Then, the equation combined with
the value of maximum value of Gp/ transforms the Dit (VG) into Dit (E) plot.
2.5.3 High Temperature Measurement of GaAs MOS capacitor
In order to obtain the full distribution of Dit in the bandgap, conductance method is applied at high temperatures. The multi frequency CV characteristics measured at 423K are shown in Fig. 2.15 and Fig.2.16 for different orientation. Fig. 2.17 and Fig.2.18 Gp/ curves are shown at the gate voltages Fermi level is near the midgap where interface states are able to capture and emission with the small signal AC bias. The peak value of each Gp/ curve corresponds to the interface state density and thus Dit as a function of gate voltage can be plotted. We interpret the largest Gp/ω value to represent Dit at the specific position in bandgap.
the Dit profile of each sample for GaAs(100) is demonstrated in Fig 2.19 compared to GaAs(111)A.
According to these figures, we saw that Dit was not high for middle of the bandgap
According to these figures, we saw that Dit was not high for middle of the bandgap