Capacitance-Voltage characteristics for GaAs(100) with silane passivation

3.3.1 Capacitance –Voltage characteristics for GaAs(100)

First of all, we exhibit the basic properties of the GaAs (100) p-type and n-type MOS capacitor C-V curves with multi-frequency, as shown in Fig. 3.2 (a) and (b), respectively.

The quantities can evaluate the quality of high-k dielectrics and I-S interface. I will choose two quantities to explain electrical characteristics. First, I defined frequency dispersion ratio≡∆C . The equation of ∆C is reproduced according to Eq.(2.1)

∆C ≡ (C (@1kHz) – C (@100kHz) )/ C (@1kHz) ( 3.1)

The p-type GaAs (100) frequency dispersion (3.34%@V_FB) are more excellent than n-type GaAs (100) frequency dispersion (9.99%@+3V). We believed that the upper half interfaces of bandgap exist a large amount of density of states (Ga-Oxide). It slow the Fermi-level is pinned at the upper half interface of bandgap when we supply voltage to gate.

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The second is the hysteresis that results when the MOS capacitor is biasd from accumulation to inversion and then swept back. First, we must calculate V_FB. The equation(3.2) is show below:

max[[1/(C/C_ox)²] / dV_g]|_{Vg =V}FB (3.2) Fig. 3.3 (a) and (b) show the results of n-type and p-type VFB. After VFB are calculated, The p-type GaAs (100) hysteresis is 450mV, and n-type GaAs (100) hysteresis is 750mV as shown in Fig. 3.4 (a) and (b)

3.3.2 Capacitance –Voltage characteristics for GaAs (100) with silane passivation

After introducing capacitance-voltage of GaAs(100), Fig. 3.5 (a) and (b) show the MOS capacitor C-V curves of the GaAs (100) p-type and n-type with silane passivation. The figures compare to Fig. 3.2 (a) and (b), No silane passivation’s samples can’t reach accumulation even at +3V applied to the gate. This case is because the Firmi-level is pinned for a large of interface density of states. The MOS capacitor with silane passivation revealed C-V behavior can reach accumulation and had low stretch-out in depletion. The p-type GaAs (100) frequency dispersion is 5.08% (@-3V) and n-type GaAs (100) frequency dispersion is 5.9% (@+3V). The values revealed interface of states maybe were lower compared to sample without silane. Fig. 3.5 (c) and (d) show that The p-type GaAs (100) hysteresis is 300mV, and n-type GaAs (100) hysteresis is 650mV. However, p-type GaAs(100) with silane passivation degraded of electrical characteristics that maybe were due to generate As-As bond, so the interface trap states increased.

3.4 Effective reduction interfacial traps using thermal annealing

Thermal annealing can further improve the quality of dielectric and reduce the interface density of states. Meanwhile, during high temperature process it is important to inhibit the loss of As within the GaAs substrate and also suppress the formation and subsequent incorporation of native oxides.

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3.4.1 Capacitance –Voltage characteristics for GaAs(100) PDA

Recently, post-deposition anneal (PDA) can further improve the quality of dielectric materials. So, we used PDA into our processing procedure. we exhibit the basic properties of the GaAs (100) p-type PDA and n-type PDA MOS capacitor C-V curves with multi-frequency, as shown in Fig. 3.6 (a) and (b). In the figure, the p-type GaAs (100) frequency dispersion (3.2%@-3V) are more excellent than n-type GaAs (100) frequency dispersion (11%@+3V).

Fig. 3.6 (c) and (d) showed that the p-type GaAs (100) hysteresis is 300mV, and n-type GaAs (100) hysteresis is 600mV. We summarized 3.4.1 and 3.4.2 n-type have larger frequency dispersion and hysteresis than p-type GaAs(100). According to the literature, the Ga2O3 didn’t be removed completely, so the frequency dispersion is much worse on n-type GaAs substrate.

After PDA process, the frequency dispersion and hysteresis of n-type GaAs(100) both have significant improvement, but p-type GaAs(100) are not.

3.4.2 Capacitance –Voltage characteristics for GaAs (100) with silane passivation

Fig. 3.7 (a) and (b) show the MOS capacitor C-V curves of the GaAs (100) p-type As and n-type As with silane passivation. Similarly, we quantitated the electrical characteristics. The p-type GaAs (100) frequency dispersion is 3.54%(@-3V) and n-type GaAs (100) frequency dispersion is 5.78%(@+3V). Fig. 3.7 (c) and (d) show that The p-type GaAs (100) hysteresis is 300mV, and n-type GaAs (100) hysteresis is 350mV. However, the electrical characteristics of p-type GaAs(100) with silane passivation was degraded that the frequency dispersion was increased. We optimized conditions of annealing and silane time can reduce the density of states for good electrical characteristics of p-type and n-type.

3.5

GaAs MOS capacitor

3.5.1Conductance method application of GaAs MOS capacitor

First, we measured C-V at 25℃for different types in Fig. 3.8. According to the figures,

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Fermi-level is completely pinned, so the C-V behaviors can’t vary by gate bias. Why were the Fermi-level pinned? At present, we believe that the density of states (D_it) were large at interface of bandgap. In addition, we also measured C-V with at 25℃for different types in Fig. 3.9.

Fig 3.10 and Fig. 3.11 illustrates the Gp/ versus f plots of MOS capacitor without and with silane passivation, and measurement is performed at room temperature. Gp/ curves are shown at the gate voltages Fermi level is only portions of the bandgap where interface states are able to capture and emission with the small signal AC bias. The peak value of each Gp/ curve corresponds to the interface state density and thus Dit as a function of gate voltage can be plotted. Then, the equation combined with the value of maximum value of Gp/ transforms the Dit (VG) into Dit (E) plot. The peak value of Gp/ can’t be observed for GaAs(100) without silane. This reason maybe is a large of density of state nearer to midgap, so the Firmi-level is pinned. Therefore, the D_it profile of GaAs(100) without silane passivation can’t be extracted, and we only show Fig. 3.12 for GaAs(100) with SiH4

passivation.

3.5.2 High Temperature Measurement of GaAs MOS capacitor

In order to obtain the full distribution of D_it in the bandgap, conductance method is applied at high temperatures. The multi frequency CV characteristics measured at 423K are shown in Fig. 3.13 and Fig. 3.14 including without and with silane passivation. Fig. 3.15 and Fig.3.16 G_p/ curves are shown at the gate voltages Fermi level is near the midgap where interface states are able to capture and emission with the small signal AC bias. The peak value of each G_p/ curve corresponds to the interface state density and thus D_it as a function of gate voltage can be plotted. We interpret the largest G_p/ω value to represent Dit at the specific position in bandgap. the Dit profile of each sample near midgap for without passivation is demonstrated in Fig 3.17 and with passivation is demonstrated in Fig 3.18.

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According to these figures, we saw Dit decreased obviously for n-type GaAs(100) with silane passivation. Simultaneously, we saw D_it increased for p-type GaAs(100). Although, the value of Dit increase didn’t affect the capacitor reach accumulation. We still optimize the condition of annealing and silane time for future.